cpu_policy.hh revision 5553
11689SN/A/* 21689SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan 31689SN/A * All rights reserved. 41689SN/A * 51689SN/A * Redistribution and use in source and binary forms, with or without 61689SN/A * modification, are permitted provided that the following conditions are 71689SN/A * met: redistributions of source code must retain the above copyright 81689SN/A * notice, this list of conditions and the following disclaimer; 91689SN/A * redistributions in binary form must reproduce the above copyright 101689SN/A * notice, this list of conditions and the following disclaimer in the 111689SN/A * documentation and/or other materials provided with the distribution; 121689SN/A * neither the name of the copyright holders nor the names of its 131689SN/A * contributors may be used to endorse or promote products derived from 141689SN/A * this software without specific prior written permission. 151689SN/A * 161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 291689SN/A */ 301689SN/A 312292SN/A#ifndef __CPU_O3_CPU_POLICY_HH__ 322292SN/A#define __CPU_O3_CPU_POLICY_HH__ 331060SN/A 341717SN/A#include "cpu/o3/bpred_unit.hh" 351717SN/A#include "cpu/o3/free_list.hh" 361717SN/A#include "cpu/o3/inst_queue.hh" 372292SN/A#include "cpu/o3/lsq.hh" 382292SN/A#include "cpu/o3/lsq_unit.hh" 391717SN/A#include "cpu/o3/mem_dep_unit.hh" 401717SN/A#include "cpu/o3/regfile.hh" 411717SN/A#include "cpu/o3/rename_map.hh" 421717SN/A#include "cpu/o3/rob.hh" 431717SN/A#include "cpu/o3/store_set.hh" 441061SN/A 451717SN/A#include "cpu/o3/commit.hh" 461717SN/A#include "cpu/o3/decode.hh" 471717SN/A#include "cpu/o3/fetch.hh" 481717SN/A#include "cpu/o3/iew.hh" 491717SN/A#include "cpu/o3/rename.hh" 501060SN/A 511717SN/A#include "cpu/o3/comm.hh" 521060SN/A 532348SN/A/** 542348SN/A * Struct that defines the key classes to be used by the CPU. All 552348SN/A * classes use the typedefs defined here to determine what are the 562348SN/A * classes of the other stages and communication buffers. In order to 572348SN/A * change a structure such as the IQ, simply change the typedef here 582348SN/A * to use the desired class instead, and recompile. In order to 592348SN/A * create a different CPU to be used simultaneously with this one, see 602348SN/A * the alpha_impl.hh file for instructions. 612348SN/A */ 621060SN/Atemplate<class Impl> 631060SN/Astruct SimpleCPUPolicy 641060SN/A{ 652348SN/A /** Typedef for the branch prediction unit (which includes the BP, 662348SN/A * RAS, and BTB). 672348SN/A */ 685553Snate@binkert.org typedef ::BPredUnit<Impl> BPredUnit; 692348SN/A /** Typedef for the register file. Most classes assume a unified 702348SN/A * physical register file. 712348SN/A */ 721060SN/A typedef PhysRegFile<Impl> RegFile; 732348SN/A /** Typedef for the freelist of registers. */ 741060SN/A typedef SimpleFreeList FreeList; 752348SN/A /** Typedef for the rename map. */ 761060SN/A typedef SimpleRenameMap RenameMap; 772348SN/A /** Typedef for the ROB. */ 785553Snate@binkert.org typedef ::ROB<Impl> ROB; 792348SN/A /** Typedef for the instruction queue/scheduler. */ 801060SN/A typedef InstructionQueue<Impl> IQ; 812348SN/A /** Typedef for the memory dependence unit. */ 825553Snate@binkert.org typedef ::MemDepUnit<StoreSet, Impl> MemDepUnit; 832348SN/A /** Typedef for the LSQ. */ 845553Snate@binkert.org typedef ::LSQ<Impl> LSQ; 852348SN/A /** Typedef for the thread-specific LSQ units. */ 865553Snate@binkert.org typedef ::LSQUnit<Impl> LSQUnit; 871060SN/A 882348SN/A /** Typedef for fetch. */ 892292SN/A typedef DefaultFetch<Impl> Fetch; 902348SN/A /** Typedef for decode. */ 912292SN/A typedef DefaultDecode<Impl> Decode; 922348SN/A /** Typedef for rename. */ 932292SN/A typedef DefaultRename<Impl> Rename; 942348SN/A /** Typedef for Issue/Execute/Writeback. */ 952292SN/A typedef DefaultIEW<Impl> IEW; 962348SN/A /** Typedef for commit. */ 972292SN/A typedef DefaultCommit<Impl> Commit; 981061SN/A 991061SN/A /** The struct for communication between fetch and decode. */ 1002292SN/A typedef DefaultFetchDefaultDecode<Impl> FetchStruct; 1011061SN/A 1021061SN/A /** The struct for communication between decode and rename. */ 1032292SN/A typedef DefaultDecodeDefaultRename<Impl> DecodeStruct; 1041061SN/A 1051061SN/A /** The struct for communication between rename and IEW. */ 1062292SN/A typedef DefaultRenameDefaultIEW<Impl> RenameStruct; 1071061SN/A 1081061SN/A /** The struct for communication between IEW and commit. */ 1092292SN/A typedef DefaultIEWDefaultCommit<Impl> IEWStruct; 1101061SN/A 1111061SN/A /** The struct for communication within the IEW stage. */ 1125553Snate@binkert.org typedef ::IssueStruct<Impl> IssueStruct; 1131061SN/A 1141061SN/A /** The struct for all backwards communication. */ 1152292SN/A typedef TimeBufStruct<Impl> TimeStruct; 1161061SN/A 1171060SN/A}; 1181060SN/A 1192292SN/A#endif //__CPU_O3_CPU_POLICY_HH__ 120