cpu.hh revision 2332
1/* 2 * Copyright (c) 2004-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#ifndef __CPU_O3_CPU_HH__ 30#define __CPU_O3_CPU_HH__ 31 32#include <iostream> 33#include <list> 34#include <queue> 35#include <set> 36#include <vector> 37 38#include "base/statistics.hh" 39#include "base/timebuf.hh" 40#include "config/full_system.hh" 41#include "cpu/activity.hh" 42#include "cpu/base.hh" 43#include "cpu/cpu_exec_context.hh" 44#include "cpu/o3/comm.hh" 45#include "cpu/o3/cpu_policy.hh" 46#include "cpu/o3/scoreboard.hh" 47#include "cpu/o3/thread_state.hh" 48#include "sim/process.hh" 49 50template <class> 51class Checker; 52class ExecContext; 53class MemInterface; 54class Process; 55 56class BaseFullCPU : public BaseCPU 57{ 58 //Stuff that's pretty ISA independent will go here. 59 public: 60 typedef BaseCPU::Params Params; 61 62 BaseFullCPU(Params *params); 63 64 void regStats(); 65 66 protected: 67 int cpu_id; 68}; 69 70template <class Impl> 71class FullO3CPU : public BaseFullCPU 72{ 73 public: 74 // Typedefs from the Impl here. 75 typedef typename Impl::CPUPol CPUPolicy; 76 typedef typename Impl::Params Params; 77 typedef typename Impl::DynInstPtr DynInstPtr; 78 79 typedef O3ThreadState<Impl> Thread; 80 81 typedef typename std::list<DynInstPtr>::iterator ListIt; 82 83 public: 84 enum Status { 85 Running, 86 Idle, 87 Halted, 88 Blocked, 89 SwitchedOut 90 }; 91 92 /** Overall CPU status. */ 93 Status _status; 94 95 private: 96 class TickEvent : public Event 97 { 98 private: 99 /** Pointer to the CPU. */ 100 FullO3CPU<Impl> *cpu; 101 102 public: 103 /** Constructs a tick event. */ 104 TickEvent(FullO3CPU<Impl> *c); 105 106 /** Processes a tick event, calling tick() on the CPU. */ 107 void process(); 108 /** Returns the description of the tick event. */ 109 const char *description(); 110 }; 111 112 /** The tick event used for scheduling CPU ticks. */ 113 TickEvent tickEvent; 114 115 /** Schedule tick event, regardless of its current state. */ 116 void scheduleTickEvent(int delay) 117 { 118 if (tickEvent.squashed()) 119 tickEvent.reschedule(curTick + cycles(delay)); 120 else if (!tickEvent.scheduled()) 121 tickEvent.schedule(curTick + cycles(delay)); 122 } 123 124 /** Unschedule tick event, regardless of its current state. */ 125 void unscheduleTickEvent() 126 { 127 if (tickEvent.scheduled()) 128 tickEvent.squash(); 129 } 130 131 public: 132 /** Constructs a CPU with the given parameters. */ 133 FullO3CPU(Params *params); 134 /** Destructor. */ 135 ~FullO3CPU(); 136 137 /** Registers statistics. */ 138 void fullCPURegStats(); 139 140 /** Ticks CPU, calling tick() on each stage, and checking the overall 141 * activity to see if the CPU should deschedule itself. 142 */ 143 void tick(); 144 145 /** Initialize the CPU */ 146 void init(); 147 148 /** Setup CPU to insert a thread's context */ 149 void insertThread(unsigned tid); 150 151 /** Remove all of a thread's context from CPU */ 152 void removeThread(unsigned tid); 153 154 /** Count the Total Instructions Committed in the CPU. */ 155 virtual Counter totalInstructions() const 156 { 157 Counter total(0); 158 159 for (int i=0; i < thread.size(); i++) 160 total += thread[i]->numInst; 161 162 return total; 163 } 164 165 /** Add Thread to Active Threads List. */ 166 void activateContext(int tid, int delay); 167 168 /** Remove Thread from Active Threads List */ 169 void suspendContext(int tid); 170 171 /** Remove Thread from Active Threads List && 172 * Remove Thread Context from CPU. 173 */ 174 void deallocateContext(int tid); 175 176 /** Remove Thread from Active Threads List && 177 * Remove Thread Context from CPU. 178 */ 179 void haltContext(int tid); 180 181 /** Activate a Thread When CPU Resources are Available. */ 182 void activateWhenReady(int tid); 183 184 /** Add or Remove a Thread Context in the CPU. */ 185 void doContextSwitch(); 186 187 /** Update The Order In Which We Process Threads. */ 188 void updateThreadPriority(); 189 190 /** Executes a syscall on this cycle. 191 * --------------------------------------- 192 * Note: this is a virtual function. CPU-Specific 193 * functionality defined in derived classes 194 */ 195 virtual void syscall(int tid) { panic("Unimplemented!"); } 196 197 /** Check if there are any system calls pending. */ 198 void checkSyscalls(); 199 200 /** Switches out this CPU. 201 */ 202 void switchOut(Sampler *sampler); 203 204 void signalSwitched(); 205 206 /** Takes over from another CPU. 207 */ 208 void takeOverFrom(BaseCPU *oldCPU); 209 210 /** Get the current instruction sequence number, and increment it. */ 211 InstSeqNum getAndIncrementInstSeq() 212 { return globalSeqNum++; } 213 214#if FULL_SYSTEM 215 /** Check if this address is a valid instruction address. */ 216 bool validInstAddr(Addr addr) { return true; } 217 218 /** Check if this address is a valid data address. */ 219 bool validDataAddr(Addr addr) { return true; } 220 221 /** Get instruction asid. */ 222 int getInstAsid(unsigned tid) 223 { return regFile.miscRegs[tid].getInstAsid(); } 224 225 /** Get data asid. */ 226 int getDataAsid(unsigned tid) 227 { return regFile.miscRegs[tid].getDataAsid(); } 228#else 229 /** Check if this address is a valid instruction address. */ 230 bool validInstAddr(Addr addr,unsigned tid) 231 { return thread[tid]->validInstAddr(addr); } 232 233 /** Check if this address is a valid data address. */ 234 bool validDataAddr(Addr addr,unsigned tid) 235 { return thread[tid]->validDataAddr(addr); } 236 237 /** Get instruction asid. */ 238 int getInstAsid(unsigned tid) 239 { return thread[tid]->asid; } 240 241 /** Get data asid. */ 242 int getDataAsid(unsigned tid) 243 { return thread[tid]->asid; } 244 245#endif 246 247 // 248 // New accessors for new decoder. 249 // 250 uint64_t readIntReg(int reg_idx); 251 252 float readFloatRegSingle(int reg_idx); 253 254 double readFloatRegDouble(int reg_idx); 255 256 uint64_t readFloatRegInt(int reg_idx); 257 258 void setIntReg(int reg_idx, uint64_t val); 259 260 void setFloatRegSingle(int reg_idx, float val); 261 262 void setFloatRegDouble(int reg_idx, double val); 263 264 void setFloatRegInt(int reg_idx, uint64_t val); 265 266 uint64_t readArchIntReg(int reg_idx, unsigned tid); 267 268 float readArchFloatRegSingle(int reg_idx, unsigned tid); 269 270 double readArchFloatRegDouble(int reg_idx, unsigned tid); 271 272 uint64_t readArchFloatRegInt(int reg_idx, unsigned tid); 273 274 void setArchIntReg(int reg_idx, uint64_t val, unsigned tid); 275 276 void setArchFloatRegSingle(int reg_idx, float val, unsigned tid); 277 278 void setArchFloatRegDouble(int reg_idx, double val, unsigned tid); 279 280 void setArchFloatRegInt(int reg_idx, uint64_t val, unsigned tid); 281 282 uint64_t readPC(unsigned tid); 283 284 void setPC(Addr new_PC,unsigned tid); 285 286 uint64_t readNextPC(unsigned tid); 287 288 void setNextPC(uint64_t val,unsigned tid); 289 290 /** Function to add instruction onto the head of the list of the 291 * instructions. Used when new instructions are fetched. 292 */ 293 ListIt addInst(DynInstPtr &inst); 294 295 /** Function to tell the CPU that an instruction has completed. */ 296 void instDone(unsigned tid); 297 298 /** Add Instructions to the CPU Remove List*/ 299 void addToRemoveList(DynInstPtr &inst); 300 301 /** Remove an instruction from the front end of the list. There's 302 * no restriction on location of the instruction. 303 */ 304 void removeFrontInst(DynInstPtr &inst); 305 306 /** Remove all instructions that are not currently in the ROB. */ 307 void removeInstsNotInROB(unsigned tid); 308 309 /** Remove all instructions younger than the given sequence number. */ 310 void removeInstsUntil(const InstSeqNum &seq_num,unsigned tid); 311 312 inline void squashInstIt(const ListIt &instIt, const unsigned &tid); 313 314 void cleanUpRemovedInsts(); 315 316 /** Remove all instructions from the list. */ 317// void removeAllInsts(); 318 319 void dumpInsts(); 320 321 /** Basically a wrapper function so that instructions executed at 322 * commit can tell the instruction queue that they have 323 * completed. Eventually this hack should be removed. 324 */ 325// void wakeDependents(DynInstPtr &inst); 326 327 public: 328 /** List of all the instructions in flight. */ 329 std::list<DynInstPtr> instList; 330 331 /** List of all the instructions that will be removed at the end of this 332 * cycle. 333 */ 334 std::queue<ListIt> removeList; 335 336#ifdef DEBUG 337 std::set<InstSeqNum> snList; 338#endif 339 340 /** Records if instructions need to be removed this cycle due to 341 * being retired or squashed. 342 */ 343 bool removeInstsThisCycle; 344 345 protected: 346 /** The fetch stage. */ 347 typename CPUPolicy::Fetch fetch; 348 349 /** The decode stage. */ 350 typename CPUPolicy::Decode decode; 351 352 /** The dispatch stage. */ 353 typename CPUPolicy::Rename rename; 354 355 /** The issue/execute/writeback stages. */ 356 typename CPUPolicy::IEW iew; 357 358 /** The commit stage. */ 359 typename CPUPolicy::Commit commit; 360 361 /** The register file. */ 362 typename CPUPolicy::RegFile regFile; 363 364 /** The free list. */ 365 typename CPUPolicy::FreeList freeList; 366 367 /** The rename map. */ 368 typename CPUPolicy::RenameMap renameMap[Impl::MaxThreads]; 369 370 /** The commit rename map. */ 371 typename CPUPolicy::RenameMap commitRenameMap[Impl::MaxThreads]; 372 373 /** The re-order buffer. */ 374 typename CPUPolicy::ROB rob; 375 376 /** Active Threads List */ 377 std::list<unsigned> activeThreads; 378 379 /** Integer Register Scoreboard */ 380 Scoreboard scoreboard; 381 382 public: 383 /** Enum to give each stage a specific index, so when calling 384 * activateStage() or deactivateStage(), they can specify which stage 385 * is being activated/deactivated. 386 */ 387 enum StageIdx { 388 FetchIdx, 389 DecodeIdx, 390 RenameIdx, 391 IEWIdx, 392 CommitIdx, 393 NumStages }; 394 395 /** Typedefs from the Impl to get the structs that each of the 396 * time buffers should use. 397 */ 398 typedef typename CPUPolicy::TimeStruct TimeStruct; 399 400 typedef typename CPUPolicy::FetchStruct FetchStruct; 401 402 typedef typename CPUPolicy::DecodeStruct DecodeStruct; 403 404 typedef typename CPUPolicy::RenameStruct RenameStruct; 405 406 typedef typename CPUPolicy::IEWStruct IEWStruct; 407 408 /** The main time buffer to do backwards communication. */ 409 TimeBuffer<TimeStruct> timeBuffer; 410 411 /** The fetch stage's instruction queue. */ 412 TimeBuffer<FetchStruct> fetchQueue; 413 414 /** The decode stage's instruction queue. */ 415 TimeBuffer<DecodeStruct> decodeQueue; 416 417 /** The rename stage's instruction queue. */ 418 TimeBuffer<RenameStruct> renameQueue; 419 420 /** The IEW stage's instruction queue. */ 421 TimeBuffer<IEWStruct> iewQueue; 422 423 public: 424 ActivityRecorder activityRec; 425 426 void activityThisCycle() { activityRec.activity(); } 427 428 void activateStage(const StageIdx idx) 429 { activityRec.activateStage(idx); } 430 431 void deactivateStage(const StageIdx idx) 432 { activityRec.deactivateStage(idx); } 433 434 /** Wakes the CPU, rescheduling the CPU if it's not already active. */ 435 void wakeCPU(); 436 437 /** Gets a free thread id. Use if thread ids change across system. */ 438 int getFreeTid(); 439 440 public: 441 /** Temporary function to get pointer to exec context. */ 442 ExecContext *xcBase(unsigned tid) 443 { 444 return thread[tid]->getXCProxy(); 445 } 446 447 /** The global sequence number counter. */ 448 InstSeqNum globalSeqNum; 449 450 Checker<DynInstPtr> *checker; 451 452#if FULL_SYSTEM 453 /** Pointer to the system. */ 454 System *system; 455 456 /** Pointer to the memory controller. */ 457 MemoryController *memCtrl; 458 /** Pointer to physical memory. */ 459 PhysicalMemory *physmem; 460#endif 461 462 /** Pointer to memory. */ 463 FunctionalMemory *mem; 464 465 Sampler *sampler; 466 467 int switchCount; 468 469 // List of all ExecContexts. 470 std::vector<Thread *> thread; 471 472#if 0 473 /** Page table pointer. */ 474 PageTable *pTable; 475#endif 476 477 /** Pointer to the icache interface. */ 478 MemInterface *icacheInterface; 479 /** Pointer to the dcache interface. */ 480 MemInterface *dcacheInterface; 481 482 /** Whether or not the CPU should defer its registration. */ 483 bool deferRegistration; 484 485 /** Is there a context switch pending? */ 486 bool contextSwitch; 487 488 /** Threads Scheduled to Enter CPU */ 489 std::list<int> cpuWaitList; 490 491 /** The cycle that the CPU was last running, used for statistics. */ 492 Tick lastRunningCycle; 493 494 /** Number of Threads CPU can process */ 495 unsigned numThreads; 496 497 /** Mapping for system thread id to cpu id */ 498 std::map<unsigned,unsigned> threadMap; 499 500 /** Available thread ids in the cpu*/ 501 std::vector<unsigned> tids; 502 503 /** Stat for total number of times the CPU is descheduled. */ 504 Stats::Scalar<> timesIdled; 505 /** Stat for total number of cycles the CPU spends descheduled. */ 506 Stats::Scalar<> idleCycles; 507 /** Stat for the number of committed instructions per thread. */ 508 Stats::Vector<> committedInsts; 509 /** Stat for the total number of committed instructions. */ 510 Stats::Scalar<> totalCommittedInsts; 511 /** Stat for the CPI per thread. */ 512 Stats::Formula cpi; 513 /** Stat for the total CPI. */ 514 Stats::Formula totalCpi; 515 /** Stat for the IPC per thread. */ 516 Stats::Formula ipc; 517 /** Stat for the total IPC. */ 518 Stats::Formula totalIpc; 519}; 520 521#endif // __CPU_O3_CPU_HH__ 522