cpu.hh revision 2332
18889Sgeoffrey.blake@arm.com/* 28889Sgeoffrey.blake@arm.com * Copyright (c) 2004-2005 The Regents of The University of Michigan 38889Sgeoffrey.blake@arm.com * All rights reserved. 410036SAli.Saidi@ARM.com * 58889Sgeoffrey.blake@arm.com * Redistribution and use in source and binary forms, with or without 610036SAli.Saidi@ARM.com * modification, are permitted provided that the following conditions are 78889Sgeoffrey.blake@arm.com * met: redistributions of source code must retain the above copyright 88889Sgeoffrey.blake@arm.com * notice, this list of conditions and the following disclaimer; 98889Sgeoffrey.blake@arm.com * redistributions in binary form must reproduce the above copyright 108889Sgeoffrey.blake@arm.com * notice, this list of conditions and the following disclaimer in the 118889Sgeoffrey.blake@arm.com * documentation and/or other materials provided with the distribution; 128889Sgeoffrey.blake@arm.com * neither the name of the copyright holders nor the names of its 1310315Snilay@cs.wisc.edu * contributors may be used to endorse or promote products derived from 148889Sgeoffrey.blake@arm.com * this software without specific prior written permission. 159885Sstever@gmail.com * 169885Sstever@gmail.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1711570SCurtis.Dunham@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1810036SAli.Saidi@ARM.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1911312Santhony.gutierrez@amd.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 208889Sgeoffrey.blake@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 218889Sgeoffrey.blake@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2210315Snilay@cs.wisc.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 238889Sgeoffrey.blake@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2410038SAli.Saidi@ARM.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 259449SAli.Saidi@ARM.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 269449SAli.Saidi@ARM.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 278889Sgeoffrey.blake@arm.com */ 2810736Snilay@cs.wisc.edu 2911219Snilay@cs.wisc.edu#ifndef __CPU_O3_CPU_HH__ 308889Sgeoffrey.blake@arm.com#define __CPU_O3_CPU_HH__ 3111570SCurtis.Dunham@arm.com 3211570SCurtis.Dunham@arm.com#include <iostream> 3311570SCurtis.Dunham@arm.com#include <list> 3411570SCurtis.Dunham@arm.com#include <queue> 358889Sgeoffrey.blake@arm.com#include <set> 368889Sgeoffrey.blake@arm.com#include <vector> 3711440SCurtis.Dunham@arm.com 3811440SCurtis.Dunham@arm.com#include "base/statistics.hh" 398889Sgeoffrey.blake@arm.com#include "base/timebuf.hh" 408889Sgeoffrey.blake@arm.com#include "config/full_system.hh" 418889Sgeoffrey.blake@arm.com#include "cpu/activity.hh" 428889Sgeoffrey.blake@arm.com#include "cpu/base.hh" 438889Sgeoffrey.blake@arm.com#include "cpu/cpu_exec_context.hh" 448889Sgeoffrey.blake@arm.com#include "cpu/o3/comm.hh" 458889Sgeoffrey.blake@arm.com#include "cpu/o3/cpu_policy.hh" 468889Sgeoffrey.blake@arm.com#include "cpu/o3/scoreboard.hh" 478889Sgeoffrey.blake@arm.com#include "cpu/o3/thread_state.hh" 489885Sstever@gmail.com#include "sim/process.hh" 499885Sstever@gmail.com 509885Sstever@gmail.comtemplate <class> 5110315Snilay@cs.wisc.educlass Checker; 5210036SAli.Saidi@ARM.comclass ExecContext; 5310315Snilay@cs.wisc.educlass MemInterface; 549885Sstever@gmail.comclass Process; 559885Sstever@gmail.com 568889Sgeoffrey.blake@arm.comclass BaseFullCPU : public BaseCPU 578889Sgeoffrey.blake@arm.com{ 5810038SAli.Saidi@ARM.com //Stuff that's pretty ISA independent will go here. 598889Sgeoffrey.blake@arm.com public: 608889Sgeoffrey.blake@arm.com typedef BaseCPU::Params Params; 618889Sgeoffrey.blake@arm.com 628889Sgeoffrey.blake@arm.com BaseFullCPU(Params *params); 638889Sgeoffrey.blake@arm.com 648889Sgeoffrey.blake@arm.com void regStats(); 658889Sgeoffrey.blake@arm.com 668889Sgeoffrey.blake@arm.com protected: 679481Snilay@cs.wisc.edu int cpu_id; 688889Sgeoffrey.blake@arm.com}; 698889Sgeoffrey.blake@arm.com 709885Sstever@gmail.comtemplate <class Impl> 718889Sgeoffrey.blake@arm.comclass FullO3CPU : public BaseFullCPU 728889Sgeoffrey.blake@arm.com{ 738889Sgeoffrey.blake@arm.com public: 748889Sgeoffrey.blake@arm.com // Typedefs from the Impl here. 758889Sgeoffrey.blake@arm.com typedef typename Impl::CPUPol CPUPolicy; 768889Sgeoffrey.blake@arm.com typedef typename Impl::Params Params; 778889Sgeoffrey.blake@arm.com typedef typename Impl::DynInstPtr DynInstPtr; 788889Sgeoffrey.blake@arm.com 798889Sgeoffrey.blake@arm.com typedef O3ThreadState<Impl> Thread; 8011570SCurtis.Dunham@arm.com 818889Sgeoffrey.blake@arm.com typedef typename std::list<DynInstPtr>::iterator ListIt; 828889Sgeoffrey.blake@arm.com 838889Sgeoffrey.blake@arm.com public: 848889Sgeoffrey.blake@arm.com enum Status { 8510038SAli.Saidi@ARM.com Running, 868889Sgeoffrey.blake@arm.com Idle, 8710036SAli.Saidi@ARM.com Halted, 8810036SAli.Saidi@ARM.com Blocked, 8910451Snilay@cs.wisc.edu SwitchedOut 908889Sgeoffrey.blake@arm.com }; 918889Sgeoffrey.blake@arm.com 928889Sgeoffrey.blake@arm.com /** Overall CPU status. */ 938889Sgeoffrey.blake@arm.com Status _status; 948889Sgeoffrey.blake@arm.com 958889Sgeoffrey.blake@arm.com private: 968889Sgeoffrey.blake@arm.com class TickEvent : public Event 978889Sgeoffrey.blake@arm.com { 988889Sgeoffrey.blake@arm.com private: 998889Sgeoffrey.blake@arm.com /** Pointer to the CPU. */ 1008889Sgeoffrey.blake@arm.com FullO3CPU<Impl> *cpu; 1018889Sgeoffrey.blake@arm.com 1029449SAli.Saidi@ARM.com public: 1038889Sgeoffrey.blake@arm.com /** Constructs a tick event. */ 1048889Sgeoffrey.blake@arm.com TickEvent(FullO3CPU<Impl> *c); 10510038SAli.Saidi@ARM.com 1068889Sgeoffrey.blake@arm.com /** Processes a tick event, calling tick() on the CPU. */ 1078889Sgeoffrey.blake@arm.com void process(); 1088889Sgeoffrey.blake@arm.com /** Returns the description of the tick event. */ 1098889Sgeoffrey.blake@arm.com const char *description(); 1108889Sgeoffrey.blake@arm.com }; 1118889Sgeoffrey.blake@arm.com 1128889Sgeoffrey.blake@arm.com /** The tick event used for scheduling CPU ticks. */ 11310451Snilay@cs.wisc.edu TickEvent tickEvent; 1148889Sgeoffrey.blake@arm.com 1158889Sgeoffrey.blake@arm.com /** Schedule tick event, regardless of its current state. */ 1168889Sgeoffrey.blake@arm.com void scheduleTickEvent(int delay) 1178889Sgeoffrey.blake@arm.com { 1188889Sgeoffrey.blake@arm.com if (tickEvent.squashed()) 11911570SCurtis.Dunham@arm.com tickEvent.reschedule(curTick + cycles(delay)); 12011570SCurtis.Dunham@arm.com else if (!tickEvent.scheduled()) 12111570SCurtis.Dunham@arm.com tickEvent.schedule(curTick + cycles(delay)); 12211570SCurtis.Dunham@arm.com } 1238889Sgeoffrey.blake@arm.com 1248889Sgeoffrey.blake@arm.com /** Unschedule tick event, regardless of its current state. */ 1258889Sgeoffrey.blake@arm.com void unscheduleTickEvent() 1268889Sgeoffrey.blake@arm.com { 1278889Sgeoffrey.blake@arm.com if (tickEvent.scheduled()) 1288889Sgeoffrey.blake@arm.com tickEvent.squash(); 1298889Sgeoffrey.blake@arm.com } 1309885Sstever@gmail.com 1318889Sgeoffrey.blake@arm.com public: 1328889Sgeoffrey.blake@arm.com /** Constructs a CPU with the given parameters. */ 1338889Sgeoffrey.blake@arm.com FullO3CPU(Params *params); 1348889Sgeoffrey.blake@arm.com /** Destructor. */ 1358889Sgeoffrey.blake@arm.com ~FullO3CPU(); 1368889Sgeoffrey.blake@arm.com 1378889Sgeoffrey.blake@arm.com /** Registers statistics. */ 1388889Sgeoffrey.blake@arm.com void fullCPURegStats(); 1398889Sgeoffrey.blake@arm.com 14010242Ssteve.reinhardt@amd.com /** Ticks CPU, calling tick() on each stage, and checking the overall 1418889Sgeoffrey.blake@arm.com * activity to see if the CPU should deschedule itself. 1428889Sgeoffrey.blake@arm.com */ 1439449SAli.Saidi@ARM.com void tick(); 1448889Sgeoffrey.blake@arm.com 1458889Sgeoffrey.blake@arm.com /** Initialize the CPU */ 1468889Sgeoffrey.blake@arm.com void init(); 1478889Sgeoffrey.blake@arm.com 1488889Sgeoffrey.blake@arm.com /** Setup CPU to insert a thread's context */ 1498889Sgeoffrey.blake@arm.com void insertThread(unsigned tid); 1508889Sgeoffrey.blake@arm.com 1518889Sgeoffrey.blake@arm.com /** Remove all of a thread's context from CPU */ 1529481Snilay@cs.wisc.edu void removeThread(unsigned tid); 15310798Ssteve.reinhardt@amd.com 1549481Snilay@cs.wisc.edu /** Count the Total Instructions Committed in the CPU. */ 1559481Snilay@cs.wisc.edu virtual Counter totalInstructions() const 1569481Snilay@cs.wisc.edu { 1579481Snilay@cs.wisc.edu Counter total(0); 1589481Snilay@cs.wisc.edu 15910036SAli.Saidi@ARM.com for (int i=0; i < thread.size(); i++) 1609481Snilay@cs.wisc.edu total += thread[i]->numInst; 1619481Snilay@cs.wisc.edu 16211440SCurtis.Dunham@arm.com return total; 16311440SCurtis.Dunham@arm.com } 16411440SCurtis.Dunham@arm.com 16511440SCurtis.Dunham@arm.com /** Add Thread to Active Threads List. */ 16611440SCurtis.Dunham@arm.com void activateContext(int tid, int delay); 16711440SCurtis.Dunham@arm.com 1689481Snilay@cs.wisc.edu /** Remove Thread from Active Threads List */ 1699481Snilay@cs.wisc.edu void suspendContext(int tid); 1709481Snilay@cs.wisc.edu 1719481Snilay@cs.wisc.edu /** Remove Thread from Active Threads List && 1729481Snilay@cs.wisc.edu * Remove Thread Context from CPU. 17311440SCurtis.Dunham@arm.com */ 1749481Snilay@cs.wisc.edu void deallocateContext(int tid); 1758889Sgeoffrey.blake@arm.com 1768889Sgeoffrey.blake@arm.com /** Remove Thread from Active Threads List && 17710038SAli.Saidi@ARM.com * Remove Thread Context from CPU. 1788889Sgeoffrey.blake@arm.com */ 1799885Sstever@gmail.com void haltContext(int tid); 1809265SAli.Saidi@ARM.com 18111570SCurtis.Dunham@arm.com /** Activate a Thread When CPU Resources are Available. */ 1828889Sgeoffrey.blake@arm.com void activateWhenReady(int tid); 1838889Sgeoffrey.blake@arm.com 1848889Sgeoffrey.blake@arm.com /** Add or Remove a Thread Context in the CPU. */ 18510038SAli.Saidi@ARM.com void doContextSwitch(); 1868889Sgeoffrey.blake@arm.com 18710036SAli.Saidi@ARM.com /** Update The Order In Which We Process Threads. */ 1888889Sgeoffrey.blake@arm.com void updateThreadPriority(); 1898889Sgeoffrey.blake@arm.com 1908889Sgeoffrey.blake@arm.com /** Executes a syscall on this cycle. 19111219Snilay@cs.wisc.edu * --------------------------------------- 1929449SAli.Saidi@ARM.com * Note: this is a virtual function. CPU-Specific 19310038SAli.Saidi@ARM.com * functionality defined in derived classes 1948889Sgeoffrey.blake@arm.com */ 1958889Sgeoffrey.blake@arm.com virtual void syscall(int tid) { panic("Unimplemented!"); } 1968889Sgeoffrey.blake@arm.com 1978889Sgeoffrey.blake@arm.com /** Check if there are any system calls pending. */ 1988889Sgeoffrey.blake@arm.com void checkSyscalls(); 1998889Sgeoffrey.blake@arm.com 20011570SCurtis.Dunham@arm.com /** Switches out this CPU. 20111570SCurtis.Dunham@arm.com */ 20211570SCurtis.Dunham@arm.com void switchOut(Sampler *sampler); 20311570SCurtis.Dunham@arm.com 2048889Sgeoffrey.blake@arm.com void signalSwitched(); 2058889Sgeoffrey.blake@arm.com 2069885Sstever@gmail.com /** Takes over from another CPU. 20710242Ssteve.reinhardt@amd.com */ 2089449SAli.Saidi@ARM.com void takeOverFrom(BaseCPU *oldCPU); 2098889Sgeoffrey.blake@arm.com 2108889Sgeoffrey.blake@arm.com /** Get the current instruction sequence number, and increment it. */ 2118889Sgeoffrey.blake@arm.com InstSeqNum getAndIncrementInstSeq() 2128889Sgeoffrey.blake@arm.com { return globalSeqNum++; } 2138889Sgeoffrey.blake@arm.com 2148889Sgeoffrey.blake@arm.com#if FULL_SYSTEM 21510038SAli.Saidi@ARM.com /** Check if this address is a valid instruction address. */ 21610038SAli.Saidi@ARM.com bool validInstAddr(Addr addr) { return true; } 21710038SAli.Saidi@ARM.com 21810038SAli.Saidi@ARM.com /** Check if this address is a valid data address. */ 21910038SAli.Saidi@ARM.com bool validDataAddr(Addr addr) { return true; } 22010736Snilay@cs.wisc.edu 22110038SAli.Saidi@ARM.com /** Get instruction asid. */ 22210038SAli.Saidi@ARM.com int getInstAsid(unsigned tid) 22310038SAli.Saidi@ARM.com { return regFile.miscRegs[tid].getInstAsid(); } 22410038SAli.Saidi@ARM.com 22510038SAli.Saidi@ARM.com /** Get data asid. */ 22610038SAli.Saidi@ARM.com int getDataAsid(unsigned tid) 22710038SAli.Saidi@ARM.com { return regFile.miscRegs[tid].getDataAsid(); } 22810038SAli.Saidi@ARM.com#else 22910038SAli.Saidi@ARM.com /** Check if this address is a valid instruction address. */ 23010038SAli.Saidi@ARM.com bool validInstAddr(Addr addr,unsigned tid) 23110038SAli.Saidi@ARM.com { return thread[tid]->validInstAddr(addr); } 23210038SAli.Saidi@ARM.com 23310038SAli.Saidi@ARM.com /** Check if this address is a valid data address. */ 23411570SCurtis.Dunham@arm.com bool validDataAddr(Addr addr,unsigned tid) 23510038SAli.Saidi@ARM.com { return thread[tid]->validDataAddr(addr); } 23610038SAli.Saidi@ARM.com 23710038SAli.Saidi@ARM.com /** Get instruction asid. */ 23811570SCurtis.Dunham@arm.com int getInstAsid(unsigned tid) 23911570SCurtis.Dunham@arm.com { return thread[tid]->asid; } 24011570SCurtis.Dunham@arm.com 24111570SCurtis.Dunham@arm.com /** Get data asid. */ 24210038SAli.Saidi@ARM.com int getDataAsid(unsigned tid) 24310038SAli.Saidi@ARM.com { return thread[tid]->asid; } 2448889Sgeoffrey.blake@arm.com 2458889Sgeoffrey.blake@arm.com#endif 2468889Sgeoffrey.blake@arm.com 24710036SAli.Saidi@ARM.com // 24810038SAli.Saidi@ARM.com // New accessors for new decoder. 2498889Sgeoffrey.blake@arm.com // 2508889Sgeoffrey.blake@arm.com uint64_t readIntReg(int reg_idx); 2518889Sgeoffrey.blake@arm.com 2528889Sgeoffrey.blake@arm.com float readFloatRegSingle(int reg_idx); 2538889Sgeoffrey.blake@arm.com 2549885Sstever@gmail.com double readFloatRegDouble(int reg_idx); 25511570SCurtis.Dunham@arm.com 25610036SAli.Saidi@ARM.com uint64_t readFloatRegInt(int reg_idx); 25710038SAli.Saidi@ARM.com 2589265SAli.Saidi@ARM.com void setIntReg(int reg_idx, uint64_t val); 25911570SCurtis.Dunham@arm.com 26011570SCurtis.Dunham@arm.com void setFloatRegSingle(int reg_idx, float val); 26111570SCurtis.Dunham@arm.com 26211570SCurtis.Dunham@arm.com void setFloatRegDouble(int reg_idx, double val); 2638889Sgeoffrey.blake@arm.com 26410736Snilay@cs.wisc.edu void setFloatRegInt(int reg_idx, uint64_t val); 2658889Sgeoffrey.blake@arm.com 2669449SAli.Saidi@ARM.com uint64_t readArchIntReg(int reg_idx, unsigned tid); 2679449SAli.Saidi@ARM.com 26811219Snilay@cs.wisc.edu float readArchFloatRegSingle(int reg_idx, unsigned tid); 26910036SAli.Saidi@ARM.com 2709449SAli.Saidi@ARM.com double readArchFloatRegDouble(int reg_idx, unsigned tid); 27110038SAli.Saidi@ARM.com 27210038SAli.Saidi@ARM.com uint64_t readArchFloatRegInt(int reg_idx, unsigned tid); 27310038SAli.Saidi@ARM.com 27410038SAli.Saidi@ARM.com void setArchIntReg(int reg_idx, uint64_t val, unsigned tid); 27510038SAli.Saidi@ARM.com 27610038SAli.Saidi@ARM.com void setArchFloatRegSingle(int reg_idx, float val, unsigned tid); 27710038SAli.Saidi@ARM.com 27810038SAli.Saidi@ARM.com void setArchFloatRegDouble(int reg_idx, double val, unsigned tid); 27910038SAli.Saidi@ARM.com 28010038SAli.Saidi@ARM.com void setArchFloatRegInt(int reg_idx, uint64_t val, unsigned tid); 2819449SAli.Saidi@ARM.com 2829449SAli.Saidi@ARM.com uint64_t readPC(unsigned tid); 2839449SAli.Saidi@ARM.com 2849449SAli.Saidi@ARM.com void setPC(Addr new_PC,unsigned tid); 2859449SAli.Saidi@ARM.com 2869449SAli.Saidi@ARM.com uint64_t readNextPC(unsigned tid); 28710038SAli.Saidi@ARM.com 2889449SAli.Saidi@ARM.com void setNextPC(uint64_t val,unsigned tid); 2899449SAli.Saidi@ARM.com 29010038SAli.Saidi@ARM.com /** Function to add instruction onto the head of the list of the 2919449SAli.Saidi@ARM.com * instructions. Used when new instructions are fetched. 29210038SAli.Saidi@ARM.com */ 29310038SAli.Saidi@ARM.com ListIt addInst(DynInstPtr &inst); 29410736Snilay@cs.wisc.edu 29510038SAli.Saidi@ARM.com /** Function to tell the CPU that an instruction has completed. */ 29610038SAli.Saidi@ARM.com void instDone(unsigned tid); 29710038SAli.Saidi@ARM.com 29810038SAli.Saidi@ARM.com /** Add Instructions to the CPU Remove List*/ 29910038SAli.Saidi@ARM.com void addToRemoveList(DynInstPtr &inst); 30010038SAli.Saidi@ARM.com 30110038SAli.Saidi@ARM.com /** Remove an instruction from the front end of the list. There's 30210736Snilay@cs.wisc.edu * no restriction on location of the instruction. 30310038SAli.Saidi@ARM.com */ 30410038SAli.Saidi@ARM.com void removeFrontInst(DynInstPtr &inst); 30510038SAli.Saidi@ARM.com 30610038SAli.Saidi@ARM.com /** Remove all instructions that are not currently in the ROB. */ 30710038SAli.Saidi@ARM.com void removeInstsNotInROB(unsigned tid); 30810038SAli.Saidi@ARM.com 30910038SAli.Saidi@ARM.com /** Remove all instructions younger than the given sequence number. */ 31010038SAli.Saidi@ARM.com void removeInstsUntil(const InstSeqNum &seq_num,unsigned tid); 31110038SAli.Saidi@ARM.com 31210038SAli.Saidi@ARM.com inline void squashInstIt(const ListIt &instIt, const unsigned &tid); 31310038SAli.Saidi@ARM.com 31410038SAli.Saidi@ARM.com void cleanUpRemovedInsts(); 31510038SAli.Saidi@ARM.com 31611570SCurtis.Dunham@arm.com /** Remove all instructions from the list. */ 31710038SAli.Saidi@ARM.com// void removeAllInsts(); 31810038SAli.Saidi@ARM.com 31910038SAli.Saidi@ARM.com void dumpInsts(); 32011570SCurtis.Dunham@arm.com 32111570SCurtis.Dunham@arm.com /** Basically a wrapper function so that instructions executed at 32211570SCurtis.Dunham@arm.com * commit can tell the instruction queue that they have 32311570SCurtis.Dunham@arm.com * completed. Eventually this hack should be removed. 32410038SAli.Saidi@ARM.com */ 3259449SAli.Saidi@ARM.com// void wakeDependents(DynInstPtr &inst); 3268889Sgeoffrey.blake@arm.com 3278889Sgeoffrey.blake@arm.com public: 3288889Sgeoffrey.blake@arm.com /** List of all the instructions in flight. */ 32910036SAli.Saidi@ARM.com std::list<DynInstPtr> instList; 33010038SAli.Saidi@ARM.com 3318889Sgeoffrey.blake@arm.com /** List of all the instructions that will be removed at the end of this 3328889Sgeoffrey.blake@arm.com * cycle. 3338889Sgeoffrey.blake@arm.com */ 3348889Sgeoffrey.blake@arm.com std::queue<ListIt> removeList; 3358889Sgeoffrey.blake@arm.com 3369885Sstever@gmail.com#ifdef DEBUG 33711570SCurtis.Dunham@arm.com std::set<InstSeqNum> snList; 33810036SAli.Saidi@ARM.com#endif 33910038SAli.Saidi@ARM.com 3409265SAli.Saidi@ARM.com /** Records if instructions need to be removed this cycle due to 34111570SCurtis.Dunham@arm.com * being retired or squashed. 34211570SCurtis.Dunham@arm.com */ 34311570SCurtis.Dunham@arm.com bool removeInstsThisCycle; 34411570SCurtis.Dunham@arm.com 3458889Sgeoffrey.blake@arm.com protected: 34610736Snilay@cs.wisc.edu /** The fetch stage. */ 3478889Sgeoffrey.blake@arm.com typename CPUPolicy::Fetch fetch; 3488889Sgeoffrey.blake@arm.com 3498889Sgeoffrey.blake@arm.com /** The decode stage. */ 35010036SAli.Saidi@ARM.com typename CPUPolicy::Decode decode; 3518889Sgeoffrey.blake@arm.com 3528889Sgeoffrey.blake@arm.com /** The dispatch stage. */ 35311066Snilay@cs.wisc.edu typename CPUPolicy::Rename rename; 3549885Sstever@gmail.com 3558889Sgeoffrey.blake@arm.com /** The issue/execute/writeback stages. */ 3568889Sgeoffrey.blake@arm.com typename CPUPolicy::IEW iew; 3579885Sstever@gmail.com 35811219Snilay@cs.wisc.edu /** The commit stage. */ 35911570SCurtis.Dunham@arm.com typename CPUPolicy::Commit commit; 36010736Snilay@cs.wisc.edu 36110036SAli.Saidi@ARM.com /** The register file. */ 3629348SAli.Saidi@ARM.com typename CPUPolicy::RegFile regFile; 36311066Snilay@cs.wisc.edu 3648889Sgeoffrey.blake@arm.com /** The free list. */ 3659348SAli.Saidi@ARM.com typename CPUPolicy::FreeList freeList; 36611570SCurtis.Dunham@arm.com 36711570SCurtis.Dunham@arm.com /** The rename map. */ 36811570SCurtis.Dunham@arm.com typename CPUPolicy::RenameMap renameMap[Impl::MaxThreads]; 36911570SCurtis.Dunham@arm.com 3708889Sgeoffrey.blake@arm.com /** The commit rename map. */ 3718889Sgeoffrey.blake@arm.com typename CPUPolicy::RenameMap commitRenameMap[Impl::MaxThreads]; 3729348SAli.Saidi@ARM.com 37310036SAli.Saidi@ARM.com /** The re-order buffer. */ 3748889Sgeoffrey.blake@arm.com typename CPUPolicy::ROB rob; 3758889Sgeoffrey.blake@arm.com 3769885Sstever@gmail.com /** Active Threads List */ 3778889Sgeoffrey.blake@arm.com std::list<unsigned> activeThreads; 3788889Sgeoffrey.blake@arm.com 37911219Snilay@cs.wisc.edu /** Integer Register Scoreboard */ 3808889Sgeoffrey.blake@arm.com Scoreboard scoreboard; 3818889Sgeoffrey.blake@arm.com 3828889Sgeoffrey.blake@arm.com public: 3839885Sstever@gmail.com /** Enum to give each stage a specific index, so when calling 3849885Sstever@gmail.com * activateStage() or deactivateStage(), they can specify which stage 3859885Sstever@gmail.com * is being activated/deactivated. 3869885Sstever@gmail.com */ 3879885Sstever@gmail.com enum StageIdx { 38811570SCurtis.Dunham@arm.com FetchIdx, 38910036SAli.Saidi@ARM.com DecodeIdx, 3909885Sstever@gmail.com RenameIdx, 39111570SCurtis.Dunham@arm.com IEWIdx, 39211570SCurtis.Dunham@arm.com CommitIdx, 39311570SCurtis.Dunham@arm.com NumStages }; 39411570SCurtis.Dunham@arm.com 39510036SAli.Saidi@ARM.com /** Typedefs from the Impl to get the structs that each of the 3969885Sstever@gmail.com * time buffers should use. 3979885Sstever@gmail.com */ 39810038SAli.Saidi@ARM.com typedef typename CPUPolicy::TimeStruct TimeStruct; 39910038SAli.Saidi@ARM.com 40010038SAli.Saidi@ARM.com typedef typename CPUPolicy::FetchStruct FetchStruct; 40110038SAli.Saidi@ARM.com 40210038SAli.Saidi@ARM.com typedef typename CPUPolicy::DecodeStruct DecodeStruct; 40310736Snilay@cs.wisc.edu 40410038SAli.Saidi@ARM.com typedef typename CPUPolicy::RenameStruct RenameStruct; 40510038SAli.Saidi@ARM.com 40610038SAli.Saidi@ARM.com typedef typename CPUPolicy::IEWStruct IEWStruct; 40710038SAli.Saidi@ARM.com 40810038SAli.Saidi@ARM.com /** The main time buffer to do backwards communication. */ 40910038SAli.Saidi@ARM.com TimeBuffer<TimeStruct> timeBuffer; 41010038SAli.Saidi@ARM.com 41110038SAli.Saidi@ARM.com /** The fetch stage's instruction queue. */ 41210038SAli.Saidi@ARM.com TimeBuffer<FetchStruct> fetchQueue; 41310038SAli.Saidi@ARM.com 41410038SAli.Saidi@ARM.com /** The decode stage's instruction queue. */ 41510038SAli.Saidi@ARM.com TimeBuffer<DecodeStruct> decodeQueue; 41610038SAli.Saidi@ARM.com 41711570SCurtis.Dunham@arm.com /** The rename stage's instruction queue. */ 41810038SAli.Saidi@ARM.com TimeBuffer<RenameStruct> renameQueue; 41910038SAli.Saidi@ARM.com 42010038SAli.Saidi@ARM.com /** The IEW stage's instruction queue. */ 42111570SCurtis.Dunham@arm.com TimeBuffer<IEWStruct> iewQueue; 42211570SCurtis.Dunham@arm.com 42311570SCurtis.Dunham@arm.com public: 42411570SCurtis.Dunham@arm.com ActivityRecorder activityRec; 42510038SAli.Saidi@ARM.com 42610038SAli.Saidi@ARM.com void activityThisCycle() { activityRec.activity(); } 4278889Sgeoffrey.blake@arm.com 4288889Sgeoffrey.blake@arm.com void activateStage(const StageIdx idx) 4298889Sgeoffrey.blake@arm.com { activityRec.activateStage(idx); } 43010036SAli.Saidi@ARM.com 43110038SAli.Saidi@ARM.com void deactivateStage(const StageIdx idx) 4328889Sgeoffrey.blake@arm.com { activityRec.deactivateStage(idx); } 4338889Sgeoffrey.blake@arm.com 4348889Sgeoffrey.blake@arm.com /** Wakes the CPU, rescheduling the CPU if it's not already active. */ 4358889Sgeoffrey.blake@arm.com void wakeCPU(); 4368889Sgeoffrey.blake@arm.com 4379885Sstever@gmail.com /** Gets a free thread id. Use if thread ids change across system. */ 43811570SCurtis.Dunham@arm.com int getFreeTid(); 43910036SAli.Saidi@ARM.com 44010038SAli.Saidi@ARM.com public: 4419265SAli.Saidi@ARM.com /** Temporary function to get pointer to exec context. */ 44211570SCurtis.Dunham@arm.com ExecContext *xcBase(unsigned tid) 44311570SCurtis.Dunham@arm.com { 44411570SCurtis.Dunham@arm.com return thread[tid]->getXCProxy(); 44511570SCurtis.Dunham@arm.com } 4468889Sgeoffrey.blake@arm.com 4478889Sgeoffrey.blake@arm.com /** The global sequence number counter. */ 4488889Sgeoffrey.blake@arm.com InstSeqNum globalSeqNum; 4498889Sgeoffrey.blake@arm.com 4508889Sgeoffrey.blake@arm.com Checker<DynInstPtr> *checker; 4518889Sgeoffrey.blake@arm.com 4528889Sgeoffrey.blake@arm.com#if FULL_SYSTEM 45310036SAli.Saidi@ARM.com /** Pointer to the system. */ 4548889Sgeoffrey.blake@arm.com System *system; 4558889Sgeoffrey.blake@arm.com 4568889Sgeoffrey.blake@arm.com /** Pointer to the memory controller. */ 4578889Sgeoffrey.blake@arm.com MemoryController *memCtrl; 4588889Sgeoffrey.blake@arm.com /** Pointer to physical memory. */ 45910036SAli.Saidi@ARM.com PhysicalMemory *physmem; 4608889Sgeoffrey.blake@arm.com#endif 4618889Sgeoffrey.blake@arm.com 4628889Sgeoffrey.blake@arm.com /** Pointer to memory. */ 4638889Sgeoffrey.blake@arm.com FunctionalMemory *mem; 46410036SAli.Saidi@ARM.com 4658889Sgeoffrey.blake@arm.com Sampler *sampler; 4668889Sgeoffrey.blake@arm.com 46711066Snilay@cs.wisc.edu int switchCount; 4688889Sgeoffrey.blake@arm.com 4698889Sgeoffrey.blake@arm.com // List of all ExecContexts. 4708889Sgeoffrey.blake@arm.com std::vector<Thread *> thread; 4718889Sgeoffrey.blake@arm.com 4728889Sgeoffrey.blake@arm.com#if 0 47310036SAli.Saidi@ARM.com /** Page table pointer. */ 4748889Sgeoffrey.blake@arm.com PageTable *pTable; 4758889Sgeoffrey.blake@arm.com#endif 4768889Sgeoffrey.blake@arm.com 4778889Sgeoffrey.blake@arm.com /** Pointer to the icache interface. */ 47810036SAli.Saidi@ARM.com MemInterface *icacheInterface; 4798889Sgeoffrey.blake@arm.com /** Pointer to the dcache interface. */ 4808889Sgeoffrey.blake@arm.com MemInterface *dcacheInterface; 48111066Snilay@cs.wisc.edu 4828889Sgeoffrey.blake@arm.com /** Whether or not the CPU should defer its registration. */ 4838889Sgeoffrey.blake@arm.com bool deferRegistration; 4848889Sgeoffrey.blake@arm.com 48510036SAli.Saidi@ARM.com /** Is there a context switch pending? */ 4868889Sgeoffrey.blake@arm.com bool contextSwitch; 4878889Sgeoffrey.blake@arm.com 48811066Snilay@cs.wisc.edu /** Threads Scheduled to Enter CPU */ 4898889Sgeoffrey.blake@arm.com std::list<int> cpuWaitList; 4908889Sgeoffrey.blake@arm.com 4918889Sgeoffrey.blake@arm.com /** The cycle that the CPU was last running, used for statistics. */ 4928889Sgeoffrey.blake@arm.com Tick lastRunningCycle; 4938889Sgeoffrey.blake@arm.com 49410036SAli.Saidi@ARM.com /** Number of Threads CPU can process */ 4958889Sgeoffrey.blake@arm.com unsigned numThreads; 4968889Sgeoffrey.blake@arm.com 4978889Sgeoffrey.blake@arm.com /** Mapping for system thread id to cpu id */ 4988889Sgeoffrey.blake@arm.com std::map<unsigned,unsigned> threadMap; 49910036SAli.Saidi@ARM.com 5008889Sgeoffrey.blake@arm.com /** Available thread ids in the cpu*/ 5018889Sgeoffrey.blake@arm.com std::vector<unsigned> tids; 50211066Snilay@cs.wisc.edu 5038889Sgeoffrey.blake@arm.com /** Stat for total number of times the CPU is descheduled. */ 5048889Sgeoffrey.blake@arm.com Stats::Scalar<> timesIdled; 5058889Sgeoffrey.blake@arm.com /** Stat for total number of cycles the CPU spends descheduled. */ 50610036SAli.Saidi@ARM.com Stats::Scalar<> idleCycles; 5078889Sgeoffrey.blake@arm.com /** Stat for the number of committed instructions per thread. */ 5088889Sgeoffrey.blake@arm.com Stats::Vector<> committedInsts; 50911066Snilay@cs.wisc.edu /** Stat for the total number of committed instructions. */ 5108889Sgeoffrey.blake@arm.com Stats::Scalar<> totalCommittedInsts; 5118889Sgeoffrey.blake@arm.com /** Stat for the CPI per thread. */ 5128889Sgeoffrey.blake@arm.com Stats::Formula cpi; 51310036SAli.Saidi@ARM.com /** Stat for the total CPI. */ 5148889Sgeoffrey.blake@arm.com Stats::Formula totalCpi; 5158889Sgeoffrey.blake@arm.com /** Stat for the IPC per thread. */ 51611066Snilay@cs.wisc.edu Stats::Formula ipc; 5178889Sgeoffrey.blake@arm.com /** Stat for the total IPC. */ 5188889Sgeoffrey.blake@arm.com Stats::Formula totalIpc; 5198889Sgeoffrey.blake@arm.com}; 5208889Sgeoffrey.blake@arm.com 5218889Sgeoffrey.blake@arm.com#endif // __CPU_O3_CPU_HH__ 52210036SAli.Saidi@ARM.com