comm.hh revision 9046:a1104cc13db2 
1/*
2 * Copyright (c) 2011 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Kevin Lim
41 */
42
43#ifndef __CPU_O3_COMM_HH__
44#define __CPU_O3_COMM_HH__
45
46#include <vector>
47
48#include "arch/types.hh"
49#include "base/types.hh"
50#include "cpu/inst_seq.hh"
51#include "sim/faults.hh"
52
53// Typedef for physical register index type. Although the Impl would be the
54// most likely location for this, there are a few classes that need this
55// typedef yet are not templated on the Impl. For now it will be defined here.
56typedef short int PhysRegIndex;
57
58/** Struct that defines the information passed from fetch to decode. */
59template<class Impl>
60struct DefaultFetchDefaultDecode {
61    typedef typename Impl::DynInstPtr DynInstPtr;
62
63    int size;
64
65    DynInstPtr insts[Impl::MaxWidth];
66    Fault fetchFault;
67    InstSeqNum fetchFaultSN;
68    bool clearFetchFault;
69};
70
71/** Struct that defines the information passed from decode to rename. */
72template<class Impl>
73struct DefaultDecodeDefaultRename {
74    typedef typename Impl::DynInstPtr DynInstPtr;
75
76    int size;
77
78    DynInstPtr insts[Impl::MaxWidth];
79};
80
81/** Struct that defines the information passed from rename to IEW. */
82template<class Impl>
83struct DefaultRenameDefaultIEW {
84    typedef typename Impl::DynInstPtr DynInstPtr;
85
86    int size;
87
88    DynInstPtr insts[Impl::MaxWidth];
89};
90
91/** Struct that defines the information passed from IEW to commit. */
92template<class Impl>
93struct DefaultIEWDefaultCommit {
94    typedef typename Impl::DynInstPtr DynInstPtr;
95
96    int size;
97
98    DynInstPtr insts[Impl::MaxWidth];
99    DynInstPtr mispredictInst[Impl::MaxThreads];
100    Addr mispredPC[Impl::MaxThreads];
101    InstSeqNum squashedSeqNum[Impl::MaxThreads];
102    TheISA::PCState pc[Impl::MaxThreads];
103
104    bool squash[Impl::MaxThreads];
105    bool branchMispredict[Impl::MaxThreads];
106    bool branchTaken[Impl::MaxThreads];
107    bool includeSquashInst[Impl::MaxThreads];
108};
109
110template<class Impl>
111struct IssueStruct {
112    typedef typename Impl::DynInstPtr DynInstPtr;
113
114    int size;
115
116    DynInstPtr insts[Impl::MaxWidth];
117};
118
119/** Struct that defines all backwards communication. */
120template<class Impl>
121struct TimeBufStruct {
122    typedef typename Impl::DynInstPtr DynInstPtr;
123    struct decodeComm {
124        uint64_t branchAddr;
125        InstSeqNum doneSeqNum;
126        DynInstPtr mispredictInst;
127        DynInstPtr squashInst;
128        Addr mispredPC;
129        TheISA::PCState nextPC;
130        unsigned branchCount;
131        bool squash;
132        bool predIncorrect;
133        bool branchMispredict;
134        bool branchTaken;
135    };
136
137    decodeComm decodeInfo[Impl::MaxThreads];
138
139    struct renameComm {
140    };
141
142    renameComm renameInfo[Impl::MaxThreads];
143
144    struct iewComm {
145        // Also eventually include skid buffer space.
146        bool usedIQ;
147        unsigned freeIQEntries;
148        bool usedLSQ;
149        unsigned freeLSQEntries;
150
151        unsigned iqCount;
152        unsigned ldstqCount;
153
154        unsigned dispatched;
155        unsigned dispatchedToLSQ;
156    };
157
158    iewComm iewInfo[Impl::MaxThreads];
159
160    struct commitComm {
161
162        /////////////// For Decode, IEW, Rename, Fetch ///////////
163        bool squash;
164        bool robSquashing;
165
166        ////////// For Fetch & IEW /////////////
167        // Represents the instruction that has either been retired or
168        // squashed.  Similar to having a single bus that broadcasts the
169        // retired or squashed sequence number.
170        InstSeqNum doneSeqNum;
171
172        ////////////// For Rename /////////////////
173        // Rename should re-read number of free rob entries
174        bool usedROB;
175        // Notify Rename that the ROB is empty
176        bool emptyROB;
177        // Tell Rename how many free entries it has in the ROB
178        unsigned freeROBEntries;
179
180
181        ///////////// For Fetch //////////////////
182        // Provide fetch the instruction that mispredicted, if this
183        // pointer is not-null a misprediction occured
184        DynInstPtr mispredictInst;
185        // Was the branch taken or not
186        bool branchTaken;
187        // The pc of the next instruction to execute. This is the next
188        // instruction for a branch mispredict, but the same instruction for
189        // order violation and the like
190        TheISA::PCState pc;
191
192        // Instruction that caused the a non-mispredict squash
193        DynInstPtr squashInst;
194        // If an interrupt is pending and fetch should stall
195        bool interruptPending;
196        // If the interrupt ended up being cleared before being handled
197        bool clearInterrupt;
198
199        //////////// For IEW //////////////////
200        // Communication specifically to the IQ to tell the IQ that it can
201        // schedule a non-speculative instruction.
202        InstSeqNum nonSpecSeqNum;
203
204        // Hack for now to send back an uncached access to the IEW stage.
205        bool uncached;
206        DynInstPtr uncachedLoad;
207
208    };
209
210    commitComm commitInfo[Impl::MaxThreads];
211
212    bool decodeBlock[Impl::MaxThreads];
213    bool decodeUnblock[Impl::MaxThreads];
214    bool renameBlock[Impl::MaxThreads];
215    bool renameUnblock[Impl::MaxThreads];
216    bool iewBlock[Impl::MaxThreads];
217    bool iewUnblock[Impl::MaxThreads];
218    bool commitBlock[Impl::MaxThreads];
219    bool commitUnblock[Impl::MaxThreads];
220};
221
222#endif //__CPU_O3_COMM_HH__
223