comm.hh revision 4636:afc8da9f526e
1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim 29 */ 30 31#ifndef __CPU_O3_COMM_HH__ 32#define __CPU_O3_COMM_HH__ 33 34#include <vector> 35 36#include "sim/faults.hh" 37#include "cpu/inst_seq.hh" 38#include "sim/host.hh" 39 40// Typedef for physical register index type. Although the Impl would be the 41// most likely location for this, there are a few classes that need this 42// typedef yet are not templated on the Impl. For now it will be defined here. 43typedef short int PhysRegIndex; 44 45/** Struct that defines the information passed from fetch to decode. */ 46template<class Impl> 47struct DefaultFetchDefaultDecode { 48 typedef typename Impl::DynInstPtr DynInstPtr; 49 50 int size; 51 52 DynInstPtr insts[Impl::MaxWidth]; 53 Fault fetchFault; 54 InstSeqNum fetchFaultSN; 55 bool clearFetchFault; 56}; 57 58/** Struct that defines the information passed from decode to rename. */ 59template<class Impl> 60struct DefaultDecodeDefaultRename { 61 typedef typename Impl::DynInstPtr DynInstPtr; 62 63 int size; 64 65 DynInstPtr insts[Impl::MaxWidth]; 66}; 67 68/** Struct that defines the information passed from rename to IEW. */ 69template<class Impl> 70struct DefaultRenameDefaultIEW { 71 typedef typename Impl::DynInstPtr DynInstPtr; 72 73 int size; 74 75 DynInstPtr insts[Impl::MaxWidth]; 76}; 77 78/** Struct that defines the information passed from IEW to commit. */ 79template<class Impl> 80struct DefaultIEWDefaultCommit { 81 typedef typename Impl::DynInstPtr DynInstPtr; 82 83 int size; 84 85 DynInstPtr insts[Impl::MaxWidth]; 86 87 bool squash[Impl::MaxThreads]; 88 bool branchMispredict[Impl::MaxThreads]; 89 bool branchTaken[Impl::MaxThreads]; 90 Addr mispredPC[Impl::MaxThreads]; 91 Addr nextPC[Impl::MaxThreads]; 92 Addr nextNPC[Impl::MaxThreads]; 93 Addr nextMicroPC[Impl::MaxThreads]; 94 InstSeqNum squashedSeqNum[Impl::MaxThreads]; 95 96 bool includeSquashInst[Impl::MaxThreads]; 97}; 98 99template<class Impl> 100struct IssueStruct { 101 typedef typename Impl::DynInstPtr DynInstPtr; 102 103 int size; 104 105 DynInstPtr insts[Impl::MaxWidth]; 106}; 107 108/** Struct that defines all backwards communication. */ 109template<class Impl> 110struct TimeBufStruct { 111 struct decodeComm { 112 bool squash; 113 bool predIncorrect; 114 uint64_t branchAddr; 115 116 InstSeqNum doneSeqNum; 117 118 // @todo: Might want to package this kind of branch stuff into a single 119 // struct as it is used pretty frequently. 120 bool branchMispredict; 121 bool branchTaken; 122 Addr mispredPC; 123 Addr nextPC; 124 Addr nextNPC; 125 Addr nextMicroPC; 126 127 unsigned branchCount; 128 }; 129 130 decodeComm decodeInfo[Impl::MaxThreads]; 131 132 struct renameComm { 133 }; 134 135 renameComm renameInfo[Impl::MaxThreads]; 136 137 struct iewComm { 138 // Also eventually include skid buffer space. 139 bool usedIQ; 140 unsigned freeIQEntries; 141 bool usedLSQ; 142 unsigned freeLSQEntries; 143 144 unsigned iqCount; 145 unsigned ldstqCount; 146 147 unsigned dispatched; 148 unsigned dispatchedToLSQ; 149 }; 150 151 iewComm iewInfo[Impl::MaxThreads]; 152 153 struct commitComm { 154 bool usedROB; 155 unsigned freeROBEntries; 156 bool emptyROB; 157 158 bool squash; 159 bool robSquashing; 160 161 bool branchMispredict; 162 bool branchTaken; 163 Addr mispredPC; 164 Addr nextPC; 165 Addr nextNPC; 166 Addr nextMicroPC; 167 168 // Represents the instruction that has either been retired or 169 // squashed. Similar to having a single bus that broadcasts the 170 // retired or squashed sequence number. 171 InstSeqNum doneSeqNum; 172 173 //Just in case we want to do a commit/squash on a cycle 174 //(necessary for multiple ROBs?) 175 bool commitInsts; 176 InstSeqNum squashSeqNum; 177 178 // Communication specifically to the IQ to tell the IQ that it can 179 // schedule a non-speculative instruction. 180 InstSeqNum nonSpecSeqNum; 181 182 // Hack for now to send back an uncached access to the IEW stage. 183 typedef typename Impl::DynInstPtr DynInstPtr; 184 bool uncached; 185 DynInstPtr uncachedLoad; 186 187 bool interruptPending; 188 bool clearInterrupt; 189 }; 190 191 commitComm commitInfo[Impl::MaxThreads]; 192 193 bool decodeBlock[Impl::MaxThreads]; 194 bool decodeUnblock[Impl::MaxThreads]; 195 bool renameBlock[Impl::MaxThreads]; 196 bool renameUnblock[Impl::MaxThreads]; 197 bool iewBlock[Impl::MaxThreads]; 198 bool iewUnblock[Impl::MaxThreads]; 199 bool commitBlock[Impl::MaxThreads]; 200 bool commitUnblock[Impl::MaxThreads]; 201}; 202 203#endif //__CPU_O3_COMM_HH__ 204