comm.hh revision 2632:1bb2f91485ea
1/* 2 * Copyright (c) 2004-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#ifndef __CPU_O3_CPU_COMM_HH__ 30#define __CPU_O3_CPU_COMM_HH__ 31 32#include <vector> 33 34#include "arch/isa_traits.hh" 35#include "cpu/inst_seq.hh" 36#include "sim/host.hh" 37 38// Find better place to put this typedef. 39// The impl might be the best place for this. 40typedef short int PhysRegIndex; 41 42template<class Impl> 43struct SimpleFetchSimpleDecode { 44 typedef typename Impl::DynInstPtr DynInstPtr; 45 46 int size; 47 48 DynInstPtr insts[Impl::MaxWidth]; 49}; 50 51template<class Impl> 52struct SimpleDecodeSimpleRename { 53 typedef typename Impl::DynInstPtr DynInstPtr; 54 55 int size; 56 57 DynInstPtr insts[Impl::MaxWidth]; 58}; 59 60template<class Impl> 61struct SimpleRenameSimpleIEW { 62 typedef typename Impl::DynInstPtr DynInstPtr; 63 64 int size; 65 66 DynInstPtr insts[Impl::MaxWidth]; 67}; 68 69template<class Impl> 70struct SimpleIEWSimpleCommit { 71 typedef typename Impl::DynInstPtr DynInstPtr; 72 73 int size; 74 75 DynInstPtr insts[Impl::MaxWidth]; 76 77 bool squash; 78 bool branchMispredict; 79 bool branchTaken; 80 uint64_t mispredPC; 81 uint64_t nextPC; 82 InstSeqNum squashedSeqNum; 83}; 84 85template<class Impl> 86struct IssueStruct { 87 typedef typename Impl::DynInstPtr DynInstPtr; 88 89 int size; 90 91 DynInstPtr insts[Impl::MaxWidth]; 92}; 93 94struct TimeBufStruct { 95 struct decodeComm { 96 bool squash; 97 bool stall; 98 bool predIncorrect; 99 uint64_t branchAddr; 100 101 InstSeqNum doneSeqNum; 102 103 // Might want to package this kind of branch stuff into a single 104 // struct as it is used pretty frequently. 105 bool branchMispredict; 106 bool branchTaken; 107 uint64_t mispredPC; 108 uint64_t nextPC; 109 }; 110 111 decodeComm decodeInfo; 112 113 // Rename can't actually tell anything to squash or send a new PC back 114 // because it doesn't do anything along those lines. But maybe leave 115 // these fields in here to keep the stages mostly orthagonal. 116 struct renameComm { 117 bool squash; 118 bool stall; 119 120 uint64_t nextPC; 121 }; 122 123 renameComm renameInfo; 124 125 struct iewComm { 126 bool stall; 127 128 // Also eventually include skid buffer space. 129 unsigned freeIQEntries; 130 }; 131 132 iewComm iewInfo; 133 134 struct commitComm { 135 bool squash; 136 bool stall; 137 unsigned freeROBEntries; 138 139 bool branchMispredict; 140 bool branchTaken; 141 uint64_t mispredPC; 142 uint64_t nextPC; 143 144 bool robSquashing; 145 146 // Represents the instruction that has either been retired or 147 // squashed. Similar to having a single bus that broadcasts the 148 // retired or squashed sequence number. 149 InstSeqNum doneSeqNum; 150 151 // Extra bit of information so that the LDSTQ only updates when it 152 // needs to. 153 bool commitIsLoad; 154 155 // Communication specifically to the IQ to tell the IQ that it can 156 // schedule a non-speculative instruction. 157 InstSeqNum nonSpecSeqNum; 158 }; 159 160 commitComm commitInfo; 161}; 162 163#endif //__CPU_O3_CPU_COMM_HH__ 164