comm.hh revision 2292
112855Sgabeblack@google.com/* 212855Sgabeblack@google.com * Copyright (c) 2004-2005 The Regents of The University of Michigan 312855Sgabeblack@google.com * All rights reserved. 412855Sgabeblack@google.com * 512855Sgabeblack@google.com * Redistribution and use in source and binary forms, with or without 612855Sgabeblack@google.com * modification, are permitted provided that the following conditions are 712855Sgabeblack@google.com * met: redistributions of source code must retain the above copyright 812855Sgabeblack@google.com * notice, this list of conditions and the following disclaimer; 912855Sgabeblack@google.com * redistributions in binary form must reproduce the above copyright 1012855Sgabeblack@google.com * notice, this list of conditions and the following disclaimer in the 1112855Sgabeblack@google.com * documentation and/or other materials provided with the distribution; 1212855Sgabeblack@google.com * neither the name of the copyright holders nor the names of its 1312855Sgabeblack@google.com * contributors may be used to endorse or promote products derived from 1412855Sgabeblack@google.com * this software without specific prior written permission. 1512855Sgabeblack@google.com * 1612855Sgabeblack@google.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1712855Sgabeblack@google.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1812855Sgabeblack@google.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1912855Sgabeblack@google.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2012855Sgabeblack@google.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2112855Sgabeblack@google.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2212855Sgabeblack@google.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2312855Sgabeblack@google.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2412855Sgabeblack@google.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2512855Sgabeblack@google.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2612855Sgabeblack@google.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2712855Sgabeblack@google.com */ 2812855Sgabeblack@google.com 2912855Sgabeblack@google.com#ifndef __CPU_O3_COMM_HH__ 3012855Sgabeblack@google.com#define __CPU_O3_COMM_HH__ 3112855Sgabeblack@google.com 3212855Sgabeblack@google.com#include <vector> 3312855Sgabeblack@google.com 3412855Sgabeblack@google.com#include "arch/faults.hh" 3512855Sgabeblack@google.com#include "arch/isa_traits.hh" 3612855Sgabeblack@google.com#include "cpu/inst_seq.hh" 3712855Sgabeblack@google.com#include "sim/host.hh" 3812855Sgabeblack@google.com 3912855Sgabeblack@google.com// Typedef for physical register index type. Although the Impl would be the 4012855Sgabeblack@google.com// most likely location for this, there are a few classes that need this 4112855Sgabeblack@google.com// typedef yet are not templated on the Impl. For now it will be defined here. 4212855Sgabeblack@google.comtypedef short int PhysRegIndex; 4312855Sgabeblack@google.com 4412855Sgabeblack@google.comtemplate<class Impl> 4512855Sgabeblack@google.comstruct DefaultFetchDefaultDecode { 4612855Sgabeblack@google.com typedef typename Impl::DynInstPtr DynInstPtr; 4712855Sgabeblack@google.com 4812855Sgabeblack@google.com int size; 4912855Sgabeblack@google.com 5012855Sgabeblack@google.com DynInstPtr insts[Impl::MaxWidth]; 5112855Sgabeblack@google.com Fault fetchFault; 5212855Sgabeblack@google.com InstSeqNum fetchFaultSN; 5312855Sgabeblack@google.com bool clearFetchFault; 5412855Sgabeblack@google.com}; 5512855Sgabeblack@google.com 5612855Sgabeblack@google.comtemplate<class Impl> 5712855Sgabeblack@google.comstruct DefaultDecodeDefaultRename { 5812855Sgabeblack@google.com typedef typename Impl::DynInstPtr DynInstPtr; 5912855Sgabeblack@google.com 6012855Sgabeblack@google.com int size; 6112855Sgabeblack@google.com 6212855Sgabeblack@google.com DynInstPtr insts[Impl::MaxWidth]; 6312855Sgabeblack@google.com}; 6412855Sgabeblack@google.com 6512855Sgabeblack@google.comtemplate<class Impl> 66struct DefaultRenameDefaultIEW { 67 typedef typename Impl::DynInstPtr DynInstPtr; 68 69 int size; 70 71 DynInstPtr insts[Impl::MaxWidth]; 72}; 73 74template<class Impl> 75struct DefaultIEWDefaultCommit { 76 typedef typename Impl::DynInstPtr DynInstPtr; 77 78 int size; 79 80 DynInstPtr insts[Impl::MaxWidth]; 81 82 bool squash[Impl::MaxThreads]; 83 bool branchMispredict[Impl::MaxThreads]; 84 bool branchTaken[Impl::MaxThreads]; 85 uint64_t mispredPC[Impl::MaxThreads]; 86 uint64_t nextPC[Impl::MaxThreads]; 87 InstSeqNum squashedSeqNum[Impl::MaxThreads]; 88 89 bool includeSquashInst[Impl::MaxThreads]; 90}; 91 92template<class Impl> 93struct IssueStruct { 94 typedef typename Impl::DynInstPtr DynInstPtr; 95 96 int size; 97 98 DynInstPtr insts[Impl::MaxWidth]; 99}; 100 101template<class Impl> 102struct TimeBufStruct { 103 struct decodeComm { 104 bool squash; 105 bool predIncorrect; 106 uint64_t branchAddr; 107 108 InstSeqNum doneSeqNum; 109 110 // @todo: Might want to package this kind of branch stuff into a single 111 // struct as it is used pretty frequently. 112 bool branchMispredict; 113 bool branchTaken; 114 uint64_t mispredPC; 115 uint64_t nextPC; 116 117 unsigned branchCount; 118 }; 119 120 decodeComm decodeInfo[Impl::MaxThreads]; 121 122 // Rename can't actually tell anything to squash or send a new PC back 123 // because it doesn't do anything along those lines. But maybe leave 124 // these fields in here to keep the stages mostly orthagonal. 125 struct renameComm { 126 bool squash; 127 128 uint64_t nextPC; 129 }; 130 131 renameComm renameInfo[Impl::MaxThreads]; 132 133 struct iewComm { 134 // Also eventually include skid buffer space. 135 bool usedIQ; 136 unsigned freeIQEntries; 137 bool usedLSQ; 138 unsigned freeLSQEntries; 139 140 unsigned iqCount; 141 unsigned ldstqCount; 142 143 unsigned dispatched; 144 unsigned dispatchedToLSQ; 145 }; 146 147 iewComm iewInfo[Impl::MaxThreads]; 148 149 struct commitComm { 150 bool usedROB; 151 unsigned freeROBEntries; 152 bool emptyROB; 153 154 bool squash; 155 bool robSquashing; 156 157 bool branchMispredict; 158 bool branchTaken; 159 uint64_t mispredPC; 160 uint64_t nextPC; 161 162 // Represents the instruction that has either been retired or 163 // squashed. Similar to having a single bus that broadcasts the 164 // retired or squashed sequence number. 165 InstSeqNum doneSeqNum; 166 167 //Just in case we want to do a commit/squash on a cycle 168 //(necessary for multiple ROBs?) 169 bool commitInsts; 170 InstSeqNum squashSeqNum; 171 172 // Extra bit of information so that the LDSTQ only updates when it 173 // needs to. 174 bool commitIsLoad; 175 176 // Communication specifically to the IQ to tell the IQ that it can 177 // schedule a non-speculative instruction. 178 InstSeqNum nonSpecSeqNum; 179 180 // Hack for now to send back an uncached access to the IEW stage. 181 typedef typename Impl::DynInstPtr DynInstPtr; 182 bool uncached; 183 DynInstPtr uncachedLoad; 184 185 bool interruptPending; 186 bool clearInterrupt; 187 }; 188 189 commitComm commitInfo[Impl::MaxThreads]; 190 191 bool decodeBlock[Impl::MaxThreads]; 192 bool decodeUnblock[Impl::MaxThreads]; 193 bool renameBlock[Impl::MaxThreads]; 194 bool renameUnblock[Impl::MaxThreads]; 195 bool iewBlock[Impl::MaxThreads]; 196 bool iewUnblock[Impl::MaxThreads]; 197 bool commitBlock[Impl::MaxThreads]; 198 bool commitUnblock[Impl::MaxThreads]; 199}; 200 201#endif //__CPU_O3_COMM_HH__ 202