comm.hh revision 12105:742d80361989
1/* 2 * Copyright (c) 2011, 2016 ARM Limited 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating 9 * to a hardware implementation of the functionality of the software 10 * licensed hereunder. You may use the software subject to the license 11 * terms below provided that you ensure that this notice is replicated 12 * unmodified and in its entirety in all distributions of the software, 13 * modified or unmodified, in source code or in binary form. 14 * 15 * Copyright (c) 2004-2006 The Regents of The University of Michigan 16 * All rights reserved. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions are 20 * met: redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer; 22 * redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution; 25 * neither the name of the copyright holders nor the names of its 26 * contributors may be used to endorse or promote products derived from 27 * this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 * 41 * Authors: Kevin Lim 42 * Nathanael Premillieu 43 */ 44 45#ifndef __CPU_O3_COMM_HH__ 46#define __CPU_O3_COMM_HH__ 47 48#include <vector> 49 50#include "arch/types.hh" 51#include "base/types.hh" 52#include "cpu/inst_seq.hh" 53#include "sim/faults.hh" 54 55// Typedef for physical register index type. Although the Impl would be the 56// most likely location for this, there are a few classes that need this 57// typedef yet are not templated on the Impl. For now it will be defined here. 58typedef short int PhysRegIndex; 59// Physical register ID 60// Associate a physical register index to a register class and 61// so it is easy to track which type of register are used. 62// A flat index is also provided for when it is useful to have a unified 63// indexing (for the dependency graph and the scoreboard for example) 64struct PhysRegId { 65 RegClass regClass; 66 PhysRegIndex regIdx; 67 PhysRegIndex flatIdx; 68 PhysRegId(RegClass _regClass, PhysRegIndex _regIdx, 69 PhysRegIndex _flatIdx) 70 : regClass(_regClass), regIdx(_regIdx), flatIdx(_flatIdx) 71 {} 72 73 bool operator==(const PhysRegId& that) const { 74 return regClass == that.regClass && regIdx == that.regIdx; 75 } 76 77 bool operator!=(const PhysRegId& that) const { 78 return !(*this==that); 79 } 80 81 bool isZeroReg() const 82 { 83 return (regIdx == TheISA::ZeroReg && 84 (regClass == IntRegClass || 85 (THE_ISA == ALPHA_ISA && regClass == FloatRegClass))); 86 } 87 88 /** @return true if it is an integer physical register. */ 89 bool isIntPhysReg() const { return regClass == IntRegClass; } 90 91 /** @return true if it is a floating-point physical register. */ 92 bool isFloatPhysReg() const { return regClass == FloatRegClass; } 93 94 /** @Return true if it is a condition-code physical register. */ 95 bool isCCPhysReg() const { return regClass == CCRegClass; } 96 97 /** 98 * Returns true if this register is always associated to the same 99 * architectural register. 100 */ 101 bool isFixedMapping() const 102 { 103 return regClass == MiscRegClass; 104 } 105}; 106 107// PhysRegIds only need to be created once and then we can use the following 108// to work with them 109typedef const PhysRegId* PhysRegIdPtr; 110 111/** Struct that defines the information passed from fetch to decode. */ 112template<class Impl> 113struct DefaultFetchDefaultDecode { 114 typedef typename Impl::DynInstPtr DynInstPtr; 115 116 int size; 117 118 DynInstPtr insts[Impl::MaxWidth]; 119 Fault fetchFault; 120 InstSeqNum fetchFaultSN; 121 bool clearFetchFault; 122}; 123 124/** Struct that defines the information passed from decode to rename. */ 125template<class Impl> 126struct DefaultDecodeDefaultRename { 127 typedef typename Impl::DynInstPtr DynInstPtr; 128 129 int size; 130 131 DynInstPtr insts[Impl::MaxWidth]; 132}; 133 134/** Struct that defines the information passed from rename to IEW. */ 135template<class Impl> 136struct DefaultRenameDefaultIEW { 137 typedef typename Impl::DynInstPtr DynInstPtr; 138 139 int size; 140 141 DynInstPtr insts[Impl::MaxWidth]; 142}; 143 144/** Struct that defines the information passed from IEW to commit. */ 145template<class Impl> 146struct DefaultIEWDefaultCommit { 147 typedef typename Impl::DynInstPtr DynInstPtr; 148 149 int size; 150 151 DynInstPtr insts[Impl::MaxWidth]; 152 DynInstPtr mispredictInst[Impl::MaxThreads]; 153 Addr mispredPC[Impl::MaxThreads]; 154 InstSeqNum squashedSeqNum[Impl::MaxThreads]; 155 TheISA::PCState pc[Impl::MaxThreads]; 156 157 bool squash[Impl::MaxThreads]; 158 bool branchMispredict[Impl::MaxThreads]; 159 bool branchTaken[Impl::MaxThreads]; 160 bool includeSquashInst[Impl::MaxThreads]; 161}; 162 163template<class Impl> 164struct IssueStruct { 165 typedef typename Impl::DynInstPtr DynInstPtr; 166 167 int size; 168 169 DynInstPtr insts[Impl::MaxWidth]; 170}; 171 172/** Struct that defines all backwards communication. */ 173template<class Impl> 174struct TimeBufStruct { 175 typedef typename Impl::DynInstPtr DynInstPtr; 176 struct decodeComm { 177 TheISA::PCState nextPC; 178 DynInstPtr mispredictInst; 179 DynInstPtr squashInst; 180 InstSeqNum doneSeqNum; 181 Addr mispredPC; 182 uint64_t branchAddr; 183 unsigned branchCount; 184 bool squash; 185 bool predIncorrect; 186 bool branchMispredict; 187 bool branchTaken; 188 }; 189 190 decodeComm decodeInfo[Impl::MaxThreads]; 191 192 struct renameComm { 193 }; 194 195 renameComm renameInfo[Impl::MaxThreads]; 196 197 struct iewComm { 198 // Also eventually include skid buffer space. 199 unsigned freeIQEntries; 200 unsigned freeLQEntries; 201 unsigned freeSQEntries; 202 unsigned dispatchedToLQ; 203 unsigned dispatchedToSQ; 204 205 unsigned iqCount; 206 unsigned ldstqCount; 207 208 unsigned dispatched; 209 bool usedIQ; 210 bool usedLSQ; 211 }; 212 213 iewComm iewInfo[Impl::MaxThreads]; 214 215 struct commitComm { 216 ///////////////////////////////////////////////////////////////////// 217 // This code has been re-structured for better packing of variables 218 // instead of by stage which is the more logical way to arrange the 219 // data. 220 // F = Fetch 221 // D = Decode 222 // I = IEW 223 // R = Rename 224 // As such each member is annotated with who consumes it 225 // e.g. bool variable name // *F,R for Fetch and Rename 226 ///////////////////////////////////////////////////////////////////// 227 228 /// The pc of the next instruction to execute. This is the next 229 /// instruction for a branch mispredict, but the same instruction for 230 /// order violation and the like 231 TheISA::PCState pc; // *F 232 233 /// Provide fetch the instruction that mispredicted, if this 234 /// pointer is not-null a misprediction occured 235 DynInstPtr mispredictInst; // *F 236 237 /// Instruction that caused the a non-mispredict squash 238 DynInstPtr squashInst; // *F 239 240 /// Hack for now to send back a strictly ordered access to the 241 /// IEW stage. 242 DynInstPtr strictlyOrderedLoad; // *I 243 244 /// Communication specifically to the IQ to tell the IQ that it can 245 /// schedule a non-speculative instruction. 246 InstSeqNum nonSpecSeqNum; // *I 247 248 /// Represents the instruction that has either been retired or 249 /// squashed. Similar to having a single bus that broadcasts the 250 /// retired or squashed sequence number. 251 InstSeqNum doneSeqNum; // *F, I 252 253 /// Tell Rename how many free entries it has in the ROB 254 unsigned freeROBEntries; // *R 255 256 bool squash; // *F, D, R, I 257 bool robSquashing; // *F, D, R, I 258 259 /// Rename should re-read number of free rob entries 260 bool usedROB; // *R 261 262 /// Notify Rename that the ROB is empty 263 bool emptyROB; // *R 264 265 /// Was the branch taken or not 266 bool branchTaken; // *F 267 /// If an interrupt is pending and fetch should stall 268 bool interruptPending; // *F 269 /// If the interrupt ended up being cleared before being handled 270 bool clearInterrupt; // *F 271 272 /// Hack for now to send back an strictly ordered access to 273 /// the IEW stage. 274 bool strictlyOrdered; // *I 275 276 }; 277 278 commitComm commitInfo[Impl::MaxThreads]; 279 280 bool decodeBlock[Impl::MaxThreads]; 281 bool decodeUnblock[Impl::MaxThreads]; 282 bool renameBlock[Impl::MaxThreads]; 283 bool renameUnblock[Impl::MaxThreads]; 284 bool iewBlock[Impl::MaxThreads]; 285 bool iewUnblock[Impl::MaxThreads]; 286}; 287 288#endif //__CPU_O3_COMM_HH__ 289