comm.hh revision 10239:592f0bb6bd6f
14486Sbinkertn@umich.edu/* 27897Shestness@cs.utexas.edu * Copyright (c) 2011 ARM Limited 34486Sbinkertn@umich.edu * Copyright (c) 2013 Advanced Micro Devices, Inc. 44486Sbinkertn@umich.edu * All rights reserved 54486Sbinkertn@umich.edu * 64486Sbinkertn@umich.edu * The license below extends only to copyright in the software and shall 74486Sbinkertn@umich.edu * not be construed as granting a license to any other intellectual 84486Sbinkertn@umich.edu * property including but not limited to intellectual property relating 94486Sbinkertn@umich.edu * to a hardware implementation of the functionality of the software 104486Sbinkertn@umich.edu * licensed hereunder. You may use the software subject to the license 114486Sbinkertn@umich.edu * terms below provided that you ensure that this notice is replicated 124486Sbinkertn@umich.edu * unmodified and in its entirety in all distributions of the software, 134486Sbinkertn@umich.edu * modified or unmodified, in source code or in binary form. 144486Sbinkertn@umich.edu * 154486Sbinkertn@umich.edu * Copyright (c) 2004-2006 The Regents of The University of Michigan 164486Sbinkertn@umich.edu * All rights reserved. 174486Sbinkertn@umich.edu * 184486Sbinkertn@umich.edu * Redistribution and use in source and binary forms, with or without 194486Sbinkertn@umich.edu * modification, are permitted provided that the following conditions are 204486Sbinkertn@umich.edu * met: redistributions of source code must retain the above copyright 214486Sbinkertn@umich.edu * notice, this list of conditions and the following disclaimer; 224486Sbinkertn@umich.edu * redistributions in binary form must reproduce the above copyright 234486Sbinkertn@umich.edu * notice, this list of conditions and the following disclaimer in the 244486Sbinkertn@umich.edu * documentation and/or other materials provided with the distribution; 254486Sbinkertn@umich.edu * neither the name of the copyright holders nor the names of its 264486Sbinkertn@umich.edu * contributors may be used to endorse or promote products derived from 274486Sbinkertn@umich.edu * this software without specific prior written permission. 284486Sbinkertn@umich.edu * 297897Shestness@cs.utexas.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 304486Sbinkertn@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 3111988Sandreas.sandberg@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 3211839SCurtis.Dunham@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 333102SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 343102SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 356654Snate@binkert.org * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3610249Sstephan.diestelhorst@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 378931Sandreas.hansson@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382212SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 399524SAndreas.Sandberg@ARM.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 409524SAndreas.Sandberg@ARM.com * 412902SN/A * Authors: Kevin Lim 428703Sandreas.hansson@arm.com */ 431783SN/A 449338SAndreas.Sandberg@arm.com#ifndef __CPU_O3_COMM_HH__ 458839Sandreas.hansson@arm.com#define __CPU_O3_COMM_HH__ 467673Snate@binkert.org 4711988Sandreas.sandberg@arm.com#include <vector> 4811988Sandreas.sandberg@arm.com 4911988Sandreas.sandberg@arm.com#include "arch/types.hh" 5011988Sandreas.sandberg@arm.com#include "base/types.hh" 514859Snate@binkert.org#include "cpu/inst_seq.hh" 528931Sandreas.hansson@arm.com#include "sim/faults.hh" 538931Sandreas.hansson@arm.com 542902SN/A// Typedef for physical register index type. Although the Impl would be the 559408Sandreas.hansson@arm.com// most likely location for this, there are a few classes that need this 5611420Sdavid.guillen@arm.com// typedef yet are not templated on the Impl. For now it will be defined here. 5711420Sdavid.guillen@arm.comtypedef short int PhysRegIndex; 5811420Sdavid.guillen@arm.com 5911420Sdavid.guillen@arm.com/** Struct that defines the information passed from fetch to decode. */ 6010700Sandreas.hansson@arm.comtemplate<class Impl> 6110700Sandreas.hansson@arm.comstruct DefaultFetchDefaultDecode { 6211838SCurtis.Dunham@arm.com typedef typename Impl::DynInstPtr DynInstPtr; 6310700Sandreas.hansson@arm.com 6410700Sandreas.hansson@arm.com int size; 6510700Sandreas.hansson@arm.com 6610700Sandreas.hansson@arm.com DynInstPtr insts[Impl::MaxWidth]; 679408Sandreas.hansson@arm.com Fault fetchFault; 689408Sandreas.hansson@arm.com InstSeqNum fetchFaultSN; 699408Sandreas.hansson@arm.com bool clearFetchFault; 709408Sandreas.hansson@arm.com}; 719408Sandreas.hansson@arm.com 729814Sandreas.hansson@arm.com/** Struct that defines the information passed from decode to rename. */ 739814Sandreas.hansson@arm.comtemplate<class Impl> 7411273Sandreas.sandberg@arm.comstruct DefaultDecodeDefaultRename { 7511270Sandreas.sandberg@arm.com typedef typename Impl::DynInstPtr DynInstPtr; 767914SBrad.Beckmann@amd.com 778666SPrakash.Ramrakhyani@arm.com int size; 787914SBrad.Beckmann@amd.com 797914SBrad.Beckmann@amd.com DynInstPtr insts[Impl::MaxWidth]; 807914SBrad.Beckmann@amd.com}; 817914SBrad.Beckmann@amd.com 827914SBrad.Beckmann@amd.com/** Struct that defines the information passed from rename to IEW. */ 837914SBrad.Beckmann@amd.comtemplate<class Impl> 847914SBrad.Beckmann@amd.comstruct DefaultRenameDefaultIEW { 857914SBrad.Beckmann@amd.com typedef typename Impl::DynInstPtr DynInstPtr; 867914SBrad.Beckmann@amd.com 877914SBrad.Beckmann@amd.com int size; 887914SBrad.Beckmann@amd.com 897914SBrad.Beckmann@amd.com DynInstPtr insts[Impl::MaxWidth]; 907914SBrad.Beckmann@amd.com}; 918769Sgblack@eecs.umich.edu 928769Sgblack@eecs.umich.edu/** Struct that defines the information passed from IEW to commit. */ 938769Sgblack@eecs.umich.edutemplate<class Impl> 9410282Sdam.sunwoo@arm.comstruct DefaultIEWDefaultCommit { 9510282Sdam.sunwoo@arm.com typedef typename Impl::DynInstPtr DynInstPtr; 968769Sgblack@eecs.umich.edu 978769Sgblack@eecs.umich.edu int size; 988769Sgblack@eecs.umich.edu 9910037SARM gem5 Developers DynInstPtr insts[Impl::MaxWidth]; 10010037SARM gem5 Developers DynInstPtr mispredictInst[Impl::MaxThreads]; 10110249Sstephan.diestelhorst@arm.com Addr mispredPC[Impl::MaxThreads]; 10211146Smitch.hayenga@arm.com InstSeqNum squashedSeqNum[Impl::MaxThreads]; 10311146Smitch.hayenga@arm.com TheISA::PCState pc[Impl::MaxThreads]; 10411146Smitch.hayenga@arm.com 10510249Sstephan.diestelhorst@arm.com bool squash[Impl::MaxThreads]; 10610249Sstephan.diestelhorst@arm.com bool branchMispredict[Impl::MaxThreads]; 10710249Sstephan.diestelhorst@arm.com bool branchTaken[Impl::MaxThreads]; 10811839SCurtis.Dunham@arm.com bool includeSquashInst[Impl::MaxThreads]; 10911839SCurtis.Dunham@arm.com}; 11011839SCurtis.Dunham@arm.com 111template<class Impl> 112struct IssueStruct { 113 typedef typename Impl::DynInstPtr DynInstPtr; 114 115 int size; 116 117 DynInstPtr insts[Impl::MaxWidth]; 118}; 119 120/** Struct that defines all backwards communication. */ 121template<class Impl> 122struct TimeBufStruct { 123 typedef typename Impl::DynInstPtr DynInstPtr; 124 struct decodeComm { 125 TheISA::PCState nextPC; 126 DynInstPtr mispredictInst; 127 DynInstPtr squashInst; 128 InstSeqNum doneSeqNum; 129 Addr mispredPC; 130 uint64_t branchAddr; 131 unsigned branchCount; 132 bool squash; 133 bool predIncorrect; 134 bool branchMispredict; 135 bool branchTaken; 136 }; 137 138 decodeComm decodeInfo[Impl::MaxThreads]; 139 140 struct renameComm { 141 }; 142 143 renameComm renameInfo[Impl::MaxThreads]; 144 145 struct iewComm { 146 // Also eventually include skid buffer space. 147 unsigned freeIQEntries; 148 unsigned freeLQEntries; 149 unsigned freeSQEntries; 150 unsigned dispatchedToLQ; 151 unsigned dispatchedToSQ; 152 153 unsigned iqCount; 154 unsigned ldstqCount; 155 156 unsigned dispatched; 157 bool usedIQ; 158 bool usedLSQ; 159 }; 160 161 iewComm iewInfo[Impl::MaxThreads]; 162 163 struct commitComm { 164 ///////////////////////////////////////////////////////////////////// 165 // This code has been re-structured for better packing of variables 166 // instead of by stage which is the more logical way to arrange the 167 // data. 168 // F = Fetch 169 // D = Decode 170 // I = IEW 171 // R = Rename 172 // As such each member is annotated with who consumes it 173 // e.g. bool variable name // *F,R for Fetch and Rename 174 ///////////////////////////////////////////////////////////////////// 175 176 /// The pc of the next instruction to execute. This is the next 177 /// instruction for a branch mispredict, but the same instruction for 178 /// order violation and the like 179 TheISA::PCState pc; // *F 180 181 /// Provide fetch the instruction that mispredicted, if this 182 /// pointer is not-null a misprediction occured 183 DynInstPtr mispredictInst; // *F 184 185 /// Instruction that caused the a non-mispredict squash 186 DynInstPtr squashInst; // *F 187 188 /// Hack for now to send back an uncached access to the IEW stage. 189 DynInstPtr uncachedLoad; // *I 190 191 /// Communication specifically to the IQ to tell the IQ that it can 192 /// schedule a non-speculative instruction. 193 InstSeqNum nonSpecSeqNum; // *I 194 195 /// Represents the instruction that has either been retired or 196 /// squashed. Similar to having a single bus that broadcasts the 197 /// retired or squashed sequence number. 198 InstSeqNum doneSeqNum; // *F, I 199 200 /// Tell Rename how many free entries it has in the ROB 201 unsigned freeROBEntries; // *R 202 203 bool squash; // *F, D, R, I 204 bool robSquashing; // *F, D, R, I 205 206 /// Rename should re-read number of free rob entries 207 bool usedROB; // *R 208 209 /// Notify Rename that the ROB is empty 210 bool emptyROB; // *R 211 212 /// Was the branch taken or not 213 bool branchTaken; // *F 214 /// If an interrupt is pending and fetch should stall 215 bool interruptPending; // *F 216 /// If the interrupt ended up being cleared before being handled 217 bool clearInterrupt; // *F 218 219 /// Hack for now to send back an uncached access to the IEW stage. 220 bool uncached; // *I 221 222 }; 223 224 commitComm commitInfo[Impl::MaxThreads]; 225 226 bool decodeBlock[Impl::MaxThreads]; 227 bool decodeUnblock[Impl::MaxThreads]; 228 bool renameBlock[Impl::MaxThreads]; 229 bool renameUnblock[Impl::MaxThreads]; 230 bool iewBlock[Impl::MaxThreads]; 231 bool iewUnblock[Impl::MaxThreads]; 232 bool commitBlock[Impl::MaxThreads]; 233 bool commitUnblock[Impl::MaxThreads]; 234}; 235 236#endif //__CPU_O3_COMM_HH__ 237