comm.hh revision 9046
11689SN/A/* 28137SAli.Saidi@ARM.com * Copyright (c) 2011 ARM Limited 38137SAli.Saidi@ARM.com * All rights reserved 48137SAli.Saidi@ARM.com * 58137SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 68137SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 78137SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 88137SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 98137SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 108137SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 118137SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 128137SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 138137SAli.Saidi@ARM.com * 142329SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 151689SN/A * All rights reserved. 161689SN/A * 171689SN/A * Redistribution and use in source and binary forms, with or without 181689SN/A * modification, are permitted provided that the following conditions are 191689SN/A * met: redistributions of source code must retain the above copyright 201689SN/A * notice, this list of conditions and the following disclaimer; 211689SN/A * redistributions in binary form must reproduce the above copyright 221689SN/A * notice, this list of conditions and the following disclaimer in the 231689SN/A * documentation and/or other materials provided with the distribution; 241689SN/A * neither the name of the copyright holders nor the names of its 251689SN/A * contributors may be used to endorse or promote products derived from 261689SN/A * this software without specific prior written permission. 271689SN/A * 281689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 291689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 301689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 311689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 321689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 331689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 341689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 351689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 361689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 371689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 381689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392665Ssaidi@eecs.umich.edu * 402665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 411689SN/A */ 421689SN/A 432292SN/A#ifndef __CPU_O3_COMM_HH__ 442292SN/A#define __CPU_O3_COMM_HH__ 451060SN/A 461061SN/A#include <vector> 471684SN/A 487720Sgblack@eecs.umich.edu#include "arch/types.hh" 496216Snate@binkert.org#include "base/types.hh" 506216Snate@binkert.org#include "cpu/inst_seq.hh" 512980Sgblack@eecs.umich.edu#include "sim/faults.hh" 521060SN/A 532292SN/A// Typedef for physical register index type. Although the Impl would be the 542292SN/A// most likely location for this, there are a few classes that need this 552292SN/A// typedef yet are not templated on the Impl. For now it will be defined here. 561060SN/Atypedef short int PhysRegIndex; 571060SN/A 582348SN/A/** Struct that defines the information passed from fetch to decode. */ 591060SN/Atemplate<class Impl> 602292SN/Astruct DefaultFetchDefaultDecode { 612292SN/A typedef typename Impl::DynInstPtr DynInstPtr; 622292SN/A 632292SN/A int size; 642292SN/A 652292SN/A DynInstPtr insts[Impl::MaxWidth]; 662292SN/A Fault fetchFault; 672292SN/A InstSeqNum fetchFaultSN; 682292SN/A bool clearFetchFault; 692292SN/A}; 702292SN/A 712348SN/A/** Struct that defines the information passed from decode to rename. */ 722292SN/Atemplate<class Impl> 732292SN/Astruct DefaultDecodeDefaultRename { 741061SN/A typedef typename Impl::DynInstPtr DynInstPtr; 751061SN/A 761061SN/A int size; 771061SN/A 781461SN/A DynInstPtr insts[Impl::MaxWidth]; 791060SN/A}; 801060SN/A 812348SN/A/** Struct that defines the information passed from rename to IEW. */ 821060SN/Atemplate<class Impl> 832292SN/Astruct DefaultRenameDefaultIEW { 841061SN/A typedef typename Impl::DynInstPtr DynInstPtr; 851061SN/A 861061SN/A int size; 871061SN/A 881461SN/A DynInstPtr insts[Impl::MaxWidth]; 891060SN/A}; 901060SN/A 912348SN/A/** Struct that defines the information passed from IEW to commit. */ 921060SN/Atemplate<class Impl> 932292SN/Astruct DefaultIEWDefaultCommit { 941061SN/A typedef typename Impl::DynInstPtr DynInstPtr; 951061SN/A 961061SN/A int size; 971061SN/A 981461SN/A DynInstPtr insts[Impl::MaxWidth]; 999046SAli.Saidi@ARM.com DynInstPtr mispredictInst[Impl::MaxThreads]; 1009046SAli.Saidi@ARM.com Addr mispredPC[Impl::MaxThreads]; 1019046SAli.Saidi@ARM.com InstSeqNum squashedSeqNum[Impl::MaxThreads]; 1029046SAli.Saidi@ARM.com TheISA::PCState pc[Impl::MaxThreads]; 1031062SN/A 1042292SN/A bool squash[Impl::MaxThreads]; 1052292SN/A bool branchMispredict[Impl::MaxThreads]; 1062292SN/A bool branchTaken[Impl::MaxThreads]; 1072292SN/A bool includeSquashInst[Impl::MaxThreads]; 1081060SN/A}; 1091060SN/A 1101060SN/Atemplate<class Impl> 1111060SN/Astruct IssueStruct { 1121061SN/A typedef typename Impl::DynInstPtr DynInstPtr; 1131061SN/A 1141061SN/A int size; 1151061SN/A 1161461SN/A DynInstPtr insts[Impl::MaxWidth]; 1171060SN/A}; 1181060SN/A 1192348SN/A/** Struct that defines all backwards communication. */ 1202292SN/Atemplate<class Impl> 1211060SN/Astruct TimeBufStruct { 1227851SMatt.Horsnell@arm.com typedef typename Impl::DynInstPtr DynInstPtr; 1231060SN/A struct decodeComm { 1249046SAli.Saidi@ARM.com uint64_t branchAddr; 1259046SAli.Saidi@ARM.com InstSeqNum doneSeqNum; 1269046SAli.Saidi@ARM.com DynInstPtr mispredictInst; 1279046SAli.Saidi@ARM.com DynInstPtr squashInst; 1289046SAli.Saidi@ARM.com Addr mispredPC; 1299046SAli.Saidi@ARM.com TheISA::PCState nextPC; 1309046SAli.Saidi@ARM.com unsigned branchCount; 1311060SN/A bool squash; 1321060SN/A bool predIncorrect; 1331061SN/A bool branchMispredict; 1341061SN/A bool branchTaken; 1351060SN/A }; 1361060SN/A 1372292SN/A decodeComm decodeInfo[Impl::MaxThreads]; 1381060SN/A 1391060SN/A struct renameComm { 1401060SN/A }; 1411060SN/A 1422292SN/A renameComm renameInfo[Impl::MaxThreads]; 1431060SN/A 1441060SN/A struct iewComm { 1452292SN/A // Also eventually include skid buffer space. 1462292SN/A bool usedIQ; 1472292SN/A unsigned freeIQEntries; 1482292SN/A bool usedLSQ; 1492292SN/A unsigned freeLSQEntries; 1501060SN/A 1512292SN/A unsigned iqCount; 1522292SN/A unsigned ldstqCount; 1532292SN/A 1542292SN/A unsigned dispatched; 1552292SN/A unsigned dispatchedToLSQ; 1561060SN/A }; 1571060SN/A 1582292SN/A iewComm iewInfo[Impl::MaxThreads]; 1591060SN/A 1601060SN/A struct commitComm { 1612292SN/A 1628137SAli.Saidi@ARM.com /////////////// For Decode, IEW, Rename, Fetch /////////// 1631060SN/A bool squash; 1642292SN/A bool robSquashing; 1651060SN/A 1668137SAli.Saidi@ARM.com ////////// For Fetch & IEW ///////////// 1671060SN/A // Represents the instruction that has either been retired or 1681060SN/A // squashed. Similar to having a single bus that broadcasts the 1691060SN/A // retired or squashed sequence number. 1701060SN/A InstSeqNum doneSeqNum; 1711061SN/A 1728137SAli.Saidi@ARM.com ////////////// For Rename ///////////////// 1738137SAli.Saidi@ARM.com // Rename should re-read number of free rob entries 1748137SAli.Saidi@ARM.com bool usedROB; 1758137SAli.Saidi@ARM.com // Notify Rename that the ROB is empty 1768137SAli.Saidi@ARM.com bool emptyROB; 1778137SAli.Saidi@ARM.com // Tell Rename how many free entries it has in the ROB 1788137SAli.Saidi@ARM.com unsigned freeROBEntries; 1791061SN/A 1808137SAli.Saidi@ARM.com 1818137SAli.Saidi@ARM.com ///////////// For Fetch ////////////////// 1828137SAli.Saidi@ARM.com // Provide fetch the instruction that mispredicted, if this 1838137SAli.Saidi@ARM.com // pointer is not-null a misprediction occured 1848137SAli.Saidi@ARM.com DynInstPtr mispredictInst; 1858137SAli.Saidi@ARM.com // Was the branch taken or not 1868137SAli.Saidi@ARM.com bool branchTaken; 1878137SAli.Saidi@ARM.com // The pc of the next instruction to execute. This is the next 1888137SAli.Saidi@ARM.com // instruction for a branch mispredict, but the same instruction for 1898137SAli.Saidi@ARM.com // order violation and the like 1908137SAli.Saidi@ARM.com TheISA::PCState pc; 1918137SAli.Saidi@ARM.com 1928137SAli.Saidi@ARM.com // Instruction that caused the a non-mispredict squash 1938137SAli.Saidi@ARM.com DynInstPtr squashInst; 1948137SAli.Saidi@ARM.com // If an interrupt is pending and fetch should stall 1958137SAli.Saidi@ARM.com bool interruptPending; 1968137SAli.Saidi@ARM.com // If the interrupt ended up being cleared before being handled 1978137SAli.Saidi@ARM.com bool clearInterrupt; 1988137SAli.Saidi@ARM.com 1998137SAli.Saidi@ARM.com //////////// For IEW ////////////////// 2001061SN/A // Communication specifically to the IQ to tell the IQ that it can 2011061SN/A // schedule a non-speculative instruction. 2021061SN/A InstSeqNum nonSpecSeqNum; 2032292SN/A 2042292SN/A // Hack for now to send back an uncached access to the IEW stage. 2052292SN/A bool uncached; 2062292SN/A DynInstPtr uncachedLoad; 2072292SN/A 2081060SN/A }; 2091060SN/A 2102292SN/A commitComm commitInfo[Impl::MaxThreads]; 2112292SN/A 2122292SN/A bool decodeBlock[Impl::MaxThreads]; 2132292SN/A bool decodeUnblock[Impl::MaxThreads]; 2142292SN/A bool renameBlock[Impl::MaxThreads]; 2152292SN/A bool renameUnblock[Impl::MaxThreads]; 2162292SN/A bool iewBlock[Impl::MaxThreads]; 2172292SN/A bool iewUnblock[Impl::MaxThreads]; 2182292SN/A bool commitBlock[Impl::MaxThreads]; 2192292SN/A bool commitUnblock[Impl::MaxThreads]; 2201060SN/A}; 2211060SN/A 2222292SN/A#endif //__CPU_O3_COMM_HH__ 223