comm.hh revision 7851
11689SN/A/* 22329SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 31689SN/A * All rights reserved. 41689SN/A * 51689SN/A * Redistribution and use in source and binary forms, with or without 61689SN/A * modification, are permitted provided that the following conditions are 71689SN/A * met: redistributions of source code must retain the above copyright 81689SN/A * notice, this list of conditions and the following disclaimer; 91689SN/A * redistributions in binary form must reproduce the above copyright 101689SN/A * notice, this list of conditions and the following disclaimer in the 111689SN/A * documentation and/or other materials provided with the distribution; 121689SN/A * neither the name of the copyright holders nor the names of its 131689SN/A * contributors may be used to endorse or promote products derived from 141689SN/A * this software without specific prior written permission. 151689SN/A * 161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 291689SN/A */ 301689SN/A 312292SN/A#ifndef __CPU_O3_COMM_HH__ 322292SN/A#define __CPU_O3_COMM_HH__ 331060SN/A 341061SN/A#include <vector> 351684SN/A 367720Sgblack@eecs.umich.edu#include "arch/types.hh" 376216Snate@binkert.org#include "base/types.hh" 386216Snate@binkert.org#include "cpu/inst_seq.hh" 392980Sgblack@eecs.umich.edu#include "sim/faults.hh" 401060SN/A 412292SN/A// Typedef for physical register index type. Although the Impl would be the 422292SN/A// most likely location for this, there are a few classes that need this 432292SN/A// typedef yet are not templated on the Impl. For now it will be defined here. 441060SN/Atypedef short int PhysRegIndex; 451060SN/A 462348SN/A/** Struct that defines the information passed from fetch to decode. */ 471060SN/Atemplate<class Impl> 482292SN/Astruct DefaultFetchDefaultDecode { 492292SN/A typedef typename Impl::DynInstPtr DynInstPtr; 502292SN/A 512292SN/A int size; 522292SN/A 532292SN/A DynInstPtr insts[Impl::MaxWidth]; 542292SN/A Fault fetchFault; 552292SN/A InstSeqNum fetchFaultSN; 562292SN/A bool clearFetchFault; 572292SN/A}; 582292SN/A 592348SN/A/** Struct that defines the information passed from decode to rename. */ 602292SN/Atemplate<class Impl> 612292SN/Astruct DefaultDecodeDefaultRename { 621061SN/A typedef typename Impl::DynInstPtr DynInstPtr; 631061SN/A 641061SN/A int size; 651061SN/A 661461SN/A DynInstPtr insts[Impl::MaxWidth]; 671060SN/A}; 681060SN/A 692348SN/A/** Struct that defines the information passed from rename to IEW. */ 701060SN/Atemplate<class Impl> 712292SN/Astruct DefaultRenameDefaultIEW { 721061SN/A typedef typename Impl::DynInstPtr DynInstPtr; 731061SN/A 741061SN/A int size; 751061SN/A 761461SN/A DynInstPtr insts[Impl::MaxWidth]; 771060SN/A}; 781060SN/A 792348SN/A/** Struct that defines the information passed from IEW to commit. */ 801060SN/Atemplate<class Impl> 812292SN/Astruct DefaultIEWDefaultCommit { 821061SN/A typedef typename Impl::DynInstPtr DynInstPtr; 831061SN/A 841061SN/A int size; 851061SN/A 861461SN/A DynInstPtr insts[Impl::MaxWidth]; 871062SN/A 882292SN/A bool squash[Impl::MaxThreads]; 892292SN/A bool branchMispredict[Impl::MaxThreads]; 907851SMatt.Horsnell@arm.com DynInstPtr mispredictInst[Impl::MaxThreads]; 912292SN/A bool branchTaken[Impl::MaxThreads]; 924636Sgblack@eecs.umich.edu Addr mispredPC[Impl::MaxThreads]; 937720Sgblack@eecs.umich.edu TheISA::PCState pc[Impl::MaxThreads]; 942292SN/A InstSeqNum squashedSeqNum[Impl::MaxThreads]; 952292SN/A 962292SN/A bool includeSquashInst[Impl::MaxThreads]; 971060SN/A}; 981060SN/A 991060SN/Atemplate<class Impl> 1001060SN/Astruct IssueStruct { 1011061SN/A typedef typename Impl::DynInstPtr DynInstPtr; 1021061SN/A 1031061SN/A int size; 1041061SN/A 1051461SN/A DynInstPtr insts[Impl::MaxWidth]; 1061060SN/A}; 1071060SN/A 1082348SN/A/** Struct that defines all backwards communication. */ 1092292SN/Atemplate<class Impl> 1101060SN/Astruct TimeBufStruct { 1117851SMatt.Horsnell@arm.com typedef typename Impl::DynInstPtr DynInstPtr; 1121060SN/A struct decodeComm { 1131060SN/A bool squash; 1141060SN/A bool predIncorrect; 1151060SN/A uint64_t branchAddr; 1161060SN/A 1171062SN/A InstSeqNum doneSeqNum; 1181062SN/A 1192292SN/A // @todo: Might want to package this kind of branch stuff into a single 1201062SN/A // struct as it is used pretty frequently. 1211061SN/A bool branchMispredict; 1227851SMatt.Horsnell@arm.com DynInstPtr mispredictInst; 1231061SN/A bool branchTaken; 1244636Sgblack@eecs.umich.edu Addr mispredPC; 1257720Sgblack@eecs.umich.edu TheISA::PCState nextPC; 1262292SN/A 1272292SN/A unsigned branchCount; 1281060SN/A }; 1291060SN/A 1302292SN/A decodeComm decodeInfo[Impl::MaxThreads]; 1311060SN/A 1321060SN/A struct renameComm { 1331060SN/A }; 1341060SN/A 1352292SN/A renameComm renameInfo[Impl::MaxThreads]; 1361060SN/A 1371060SN/A struct iewComm { 1382292SN/A // Also eventually include skid buffer space. 1392292SN/A bool usedIQ; 1402292SN/A unsigned freeIQEntries; 1412292SN/A bool usedLSQ; 1422292SN/A unsigned freeLSQEntries; 1431060SN/A 1442292SN/A unsigned iqCount; 1452292SN/A unsigned ldstqCount; 1462292SN/A 1472292SN/A unsigned dispatched; 1482292SN/A unsigned dispatchedToLSQ; 1491060SN/A }; 1501060SN/A 1512292SN/A iewComm iewInfo[Impl::MaxThreads]; 1521060SN/A 1531060SN/A struct commitComm { 1542292SN/A bool usedROB; 1552292SN/A unsigned freeROBEntries; 1562292SN/A bool emptyROB; 1572292SN/A 1581060SN/A bool squash; 1592292SN/A bool robSquashing; 1601060SN/A 1611061SN/A bool branchMispredict; 1627851SMatt.Horsnell@arm.com DynInstPtr mispredictInst; 1631061SN/A bool branchTaken; 1644636Sgblack@eecs.umich.edu Addr mispredPC; 1657720Sgblack@eecs.umich.edu TheISA::PCState pc; 1661060SN/A 1671060SN/A // Represents the instruction that has either been retired or 1681060SN/A // squashed. Similar to having a single bus that broadcasts the 1691060SN/A // retired or squashed sequence number. 1701060SN/A InstSeqNum doneSeqNum; 1711061SN/A 1722292SN/A //Just in case we want to do a commit/squash on a cycle 1732292SN/A //(necessary for multiple ROBs?) 1742292SN/A bool commitInsts; 1752292SN/A InstSeqNum squashSeqNum; 1761061SN/A 1771061SN/A // Communication specifically to the IQ to tell the IQ that it can 1781061SN/A // schedule a non-speculative instruction. 1791061SN/A InstSeqNum nonSpecSeqNum; 1802292SN/A 1812292SN/A // Hack for now to send back an uncached access to the IEW stage. 1822292SN/A bool uncached; 1832292SN/A DynInstPtr uncachedLoad; 1842292SN/A 1852292SN/A bool interruptPending; 1862292SN/A bool clearInterrupt; 1871060SN/A }; 1881060SN/A 1892292SN/A commitComm commitInfo[Impl::MaxThreads]; 1902292SN/A 1912292SN/A bool decodeBlock[Impl::MaxThreads]; 1922292SN/A bool decodeUnblock[Impl::MaxThreads]; 1932292SN/A bool renameBlock[Impl::MaxThreads]; 1942292SN/A bool renameUnblock[Impl::MaxThreads]; 1952292SN/A bool iewBlock[Impl::MaxThreads]; 1962292SN/A bool iewUnblock[Impl::MaxThreads]; 1972292SN/A bool commitBlock[Impl::MaxThreads]; 1982292SN/A bool commitUnblock[Impl::MaxThreads]; 1991060SN/A}; 2001060SN/A 2012292SN/A#endif //__CPU_O3_COMM_HH__ 202