comm.hh revision 2348 
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#ifndef __CPU_O3_COMM_HH__
30#define __CPU_O3_COMM_HH__
31
32#include <vector>
33
34#include "arch/faults.hh"
35#include "arch/isa_traits.hh"
36#include "cpu/inst_seq.hh"
37#include "sim/host.hh"
38
39// Typedef for physical register index type. Although the Impl would be the
40// most likely location for this, there are a few classes that need this
41// typedef yet are not templated on the Impl. For now it will be defined here.
42typedef short int PhysRegIndex;
43
44/** Struct that defines the information passed from fetch to decode. */
45template<class Impl>
46struct DefaultFetchDefaultDecode {
47    typedef typename Impl::DynInstPtr DynInstPtr;
48
49    int size;
50
51    DynInstPtr insts[Impl::MaxWidth];
52    Fault fetchFault;
53    InstSeqNum fetchFaultSN;
54    bool clearFetchFault;
55};
56
57/** Struct that defines the information passed from decode to rename. */
58template<class Impl>
59struct DefaultDecodeDefaultRename {
60    typedef typename Impl::DynInstPtr DynInstPtr;
61
62    int size;
63
64    DynInstPtr insts[Impl::MaxWidth];
65};
66
67/** Struct that defines the information passed from rename to IEW. */
68template<class Impl>
69struct DefaultRenameDefaultIEW {
70    typedef typename Impl::DynInstPtr DynInstPtr;
71
72    int size;
73
74    DynInstPtr insts[Impl::MaxWidth];
75};
76
77/** Struct that defines the information passed from IEW to commit. */
78template<class Impl>
79struct DefaultIEWDefaultCommit {
80    typedef typename Impl::DynInstPtr DynInstPtr;
81
82    int size;
83
84    DynInstPtr insts[Impl::MaxWidth];
85
86    bool squash[Impl::MaxThreads];
87    bool branchMispredict[Impl::MaxThreads];
88    bool branchTaken[Impl::MaxThreads];
89    uint64_t mispredPC[Impl::MaxThreads];
90    uint64_t nextPC[Impl::MaxThreads];
91    InstSeqNum squashedSeqNum[Impl::MaxThreads];
92
93    bool includeSquashInst[Impl::MaxThreads];
94};
95
96template<class Impl>
97struct IssueStruct {
98    typedef typename Impl::DynInstPtr DynInstPtr;
99
100    int size;
101
102    DynInstPtr insts[Impl::MaxWidth];
103};
104
105/** Struct that defines all backwards communication. */
106template<class Impl>
107struct TimeBufStruct {
108    struct decodeComm {
109        bool squash;
110        bool predIncorrect;
111        uint64_t branchAddr;
112
113        InstSeqNum doneSeqNum;
114
115        // @todo: Might want to package this kind of branch stuff into a single
116        // struct as it is used pretty frequently.
117        bool branchMispredict;
118        bool branchTaken;
119        uint64_t mispredPC;
120        uint64_t nextPC;
121
122        unsigned branchCount;
123    };
124
125    decodeComm decodeInfo[Impl::MaxThreads];
126
127    struct renameComm {
128    };
129
130    renameComm renameInfo[Impl::MaxThreads];
131
132    struct iewComm {
133        // Also eventually include skid buffer space.
134        bool usedIQ;
135        unsigned freeIQEntries;
136        bool usedLSQ;
137        unsigned freeLSQEntries;
138
139        unsigned iqCount;
140        unsigned ldstqCount;
141
142        unsigned dispatched;
143        unsigned dispatchedToLSQ;
144    };
145
146    iewComm iewInfo[Impl::MaxThreads];
147
148    struct commitComm {
149        bool usedROB;
150        unsigned freeROBEntries;
151        bool emptyROB;
152
153        bool squash;
154        bool robSquashing;
155
156        bool branchMispredict;
157        bool branchTaken;
158        uint64_t mispredPC;
159        uint64_t nextPC;
160
161        // Represents the instruction that has either been retired or
162        // squashed.  Similar to having a single bus that broadcasts the
163        // retired or squashed sequence number.
164        InstSeqNum doneSeqNum;
165
166        //Just in case we want to do a commit/squash on a cycle
167        //(necessary for multiple ROBs?)
168        bool commitInsts;
169        InstSeqNum squashSeqNum;
170
171        // Communication specifically to the IQ to tell the IQ that it can
172        // schedule a non-speculative instruction.
173        InstSeqNum nonSpecSeqNum;
174
175        // Hack for now to send back an uncached access to the IEW stage.
176        typedef typename Impl::DynInstPtr DynInstPtr;
177        bool uncached;
178        DynInstPtr uncachedLoad;
179
180        bool interruptPending;
181        bool clearInterrupt;
182    };
183
184    commitComm commitInfo[Impl::MaxThreads];
185
186    bool decodeBlock[Impl::MaxThreads];
187    bool decodeUnblock[Impl::MaxThreads];
188    bool renameBlock[Impl::MaxThreads];
189    bool renameUnblock[Impl::MaxThreads];
190    bool iewBlock[Impl::MaxThreads];
191    bool iewUnblock[Impl::MaxThreads];
192    bool commitBlock[Impl::MaxThreads];
193    bool commitUnblock[Impl::MaxThreads];
194};
195
196#endif //__CPU_O3_COMM_HH__
197