comm.hh revision 2329
19100SBrad.Beckmann@amd.com/* 29100SBrad.Beckmann@amd.com * Copyright (c) 2004-2006 The Regents of The University of Michigan 39100SBrad.Beckmann@amd.com * All rights reserved. 49100SBrad.Beckmann@amd.com * 59100SBrad.Beckmann@amd.com * Redistribution and use in source and binary forms, with or without 69100SBrad.Beckmann@amd.com * modification, are permitted provided that the following conditions are 79100SBrad.Beckmann@amd.com * met: redistributions of source code must retain the above copyright 89100SBrad.Beckmann@amd.com * notice, this list of conditions and the following disclaimer; 99100SBrad.Beckmann@amd.com * redistributions in binary form must reproduce the above copyright 109100SBrad.Beckmann@amd.com * notice, this list of conditions and the following disclaimer in the 119100SBrad.Beckmann@amd.com * documentation and/or other materials provided with the distribution; 129100SBrad.Beckmann@amd.com * neither the name of the copyright holders nor the names of its 139100SBrad.Beckmann@amd.com * contributors may be used to endorse or promote products derived from 149100SBrad.Beckmann@amd.com * this software without specific prior written permission. 159100SBrad.Beckmann@amd.com * 169100SBrad.Beckmann@amd.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 179100SBrad.Beckmann@amd.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 189100SBrad.Beckmann@amd.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 199100SBrad.Beckmann@amd.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 209100SBrad.Beckmann@amd.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 219100SBrad.Beckmann@amd.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 229100SBrad.Beckmann@amd.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 239100SBrad.Beckmann@amd.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 249100SBrad.Beckmann@amd.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 259100SBrad.Beckmann@amd.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 269100SBrad.Beckmann@amd.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 279100SBrad.Beckmann@amd.com */ 289100SBrad.Beckmann@amd.com 299100SBrad.Beckmann@amd.com#ifndef __CPU_O3_COMM_HH__ 309100SBrad.Beckmann@amd.com#define __CPU_O3_COMM_HH__ 319100SBrad.Beckmann@amd.com 329100SBrad.Beckmann@amd.com#include <vector> 339100SBrad.Beckmann@amd.com 349100SBrad.Beckmann@amd.com#include "arch/faults.hh" 359100SBrad.Beckmann@amd.com#include "arch/isa_traits.hh" 369100SBrad.Beckmann@amd.com#include "cpu/inst_seq.hh" 379100SBrad.Beckmann@amd.com#include "sim/host.hh" 389100SBrad.Beckmann@amd.com 399100SBrad.Beckmann@amd.com// Typedef for physical register index type. Although the Impl would be the 409100SBrad.Beckmann@amd.com// most likely location for this, there are a few classes that need this 419100SBrad.Beckmann@amd.com// typedef yet are not templated on the Impl. For now it will be defined here. 429100SBrad.Beckmann@amd.comtypedef short int PhysRegIndex; 439100SBrad.Beckmann@amd.com 449100SBrad.Beckmann@amd.comtemplate<class Impl> 459100SBrad.Beckmann@amd.comstruct DefaultFetchDefaultDecode { 469100SBrad.Beckmann@amd.com typedef typename Impl::DynInstPtr DynInstPtr; 479100SBrad.Beckmann@amd.com 489100SBrad.Beckmann@amd.com int size; 499100SBrad.Beckmann@amd.com 509100SBrad.Beckmann@amd.com DynInstPtr insts[Impl::MaxWidth]; 519100SBrad.Beckmann@amd.com Fault fetchFault; 529100SBrad.Beckmann@amd.com InstSeqNum fetchFaultSN; 539100SBrad.Beckmann@amd.com bool clearFetchFault; 549100SBrad.Beckmann@amd.com}; 559100SBrad.Beckmann@amd.com 569100SBrad.Beckmann@amd.comtemplate<class Impl> 579100SBrad.Beckmann@amd.comstruct DefaultDecodeDefaultRename { 589100SBrad.Beckmann@amd.com typedef typename Impl::DynInstPtr DynInstPtr; 599100SBrad.Beckmann@amd.com 609100SBrad.Beckmann@amd.com int size; 619100SBrad.Beckmann@amd.com 629100SBrad.Beckmann@amd.com DynInstPtr insts[Impl::MaxWidth]; 639100SBrad.Beckmann@amd.com}; 649100SBrad.Beckmann@amd.com 659100SBrad.Beckmann@amd.comtemplate<class Impl> 669100SBrad.Beckmann@amd.comstruct DefaultRenameDefaultIEW { 679100SBrad.Beckmann@amd.com typedef typename Impl::DynInstPtr DynInstPtr; 689100SBrad.Beckmann@amd.com 699100SBrad.Beckmann@amd.com int size; 709100SBrad.Beckmann@amd.com 719100SBrad.Beckmann@amd.com DynInstPtr insts[Impl::MaxWidth]; 729100SBrad.Beckmann@amd.com}; 739100SBrad.Beckmann@amd.com 749100SBrad.Beckmann@amd.comtemplate<class Impl> 759100SBrad.Beckmann@amd.comstruct DefaultIEWDefaultCommit { 769862Snilay@cs.wisc.edu typedef typename Impl::DynInstPtr DynInstPtr; 779100SBrad.Beckmann@amd.com 789100SBrad.Beckmann@amd.com int size; 799100SBrad.Beckmann@amd.com 809100SBrad.Beckmann@amd.com DynInstPtr insts[Impl::MaxWidth]; 819100SBrad.Beckmann@amd.com 829862Snilay@cs.wisc.edu bool squash[Impl::MaxThreads]; 839862Snilay@cs.wisc.edu bool branchMispredict[Impl::MaxThreads]; 849100SBrad.Beckmann@amd.com bool branchTaken[Impl::MaxThreads]; 859100SBrad.Beckmann@amd.com uint64_t mispredPC[Impl::MaxThreads]; 869862Snilay@cs.wisc.edu uint64_t nextPC[Impl::MaxThreads]; 879100SBrad.Beckmann@amd.com InstSeqNum squashedSeqNum[Impl::MaxThreads]; 889100SBrad.Beckmann@amd.com 8910088Snilay@cs.wisc.edu bool includeSquashInst[Impl::MaxThreads]; 9010088Snilay@cs.wisc.edu}; 9110088Snilay@cs.wisc.edu 929100SBrad.Beckmann@amd.comtemplate<class Impl> 939100SBrad.Beckmann@amd.comstruct IssueStruct { 9410088Snilay@cs.wisc.edu typedef typename Impl::DynInstPtr DynInstPtr; 9510088Snilay@cs.wisc.edu 9610088Snilay@cs.wisc.edu int size; 9710088Snilay@cs.wisc.edu 989100SBrad.Beckmann@amd.com DynInstPtr insts[Impl::MaxWidth]; 999100SBrad.Beckmann@amd.com}; 1009100SBrad.Beckmann@amd.com 1019100SBrad.Beckmann@amd.comtemplate<class Impl> 1029100SBrad.Beckmann@amd.comstruct TimeBufStruct { 1039100SBrad.Beckmann@amd.com struct decodeComm { 1049100SBrad.Beckmann@amd.com bool squash; 1059862Snilay@cs.wisc.edu bool predIncorrect; 1069100SBrad.Beckmann@amd.com uint64_t branchAddr; 10710088Snilay@cs.wisc.edu 10810088Snilay@cs.wisc.edu InstSeqNum doneSeqNum; 10910088Snilay@cs.wisc.edu 11010088Snilay@cs.wisc.edu // @todo: Might want to package this kind of branch stuff into a single 11110088Snilay@cs.wisc.edu // struct as it is used pretty frequently. 1129100SBrad.Beckmann@amd.com bool branchMispredict; 1139100SBrad.Beckmann@amd.com bool branchTaken; 1149100SBrad.Beckmann@amd.com uint64_t mispredPC; 1159100SBrad.Beckmann@amd.com uint64_t nextPC; 1169100SBrad.Beckmann@amd.com 1179862Snilay@cs.wisc.edu unsigned branchCount; 1189100SBrad.Beckmann@amd.com }; 1199148Spowerjg@cs.wisc.edu 1209148Spowerjg@cs.wisc.edu decodeComm decodeInfo[Impl::MaxThreads]; 1219148Spowerjg@cs.wisc.edu 122 // Rename can't actually tell anything to squash or send a new PC back 123 // because it doesn't do anything along those lines. But maybe leave 124 // these fields in here to keep the stages mostly orthagonal. 125 struct renameComm { 126 bool squash; 127 128 uint64_t nextPC; 129 }; 130 131 renameComm renameInfo[Impl::MaxThreads]; 132 133 struct iewComm { 134 // Also eventually include skid buffer space. 135 bool usedIQ; 136 unsigned freeIQEntries; 137 bool usedLSQ; 138 unsigned freeLSQEntries; 139 140 unsigned iqCount; 141 unsigned ldstqCount; 142 143 unsigned dispatched; 144 unsigned dispatchedToLSQ; 145 }; 146 147 iewComm iewInfo[Impl::MaxThreads]; 148 149 struct commitComm { 150 bool usedROB; 151 unsigned freeROBEntries; 152 bool emptyROB; 153 154 bool squash; 155 bool robSquashing; 156 157 bool branchMispredict; 158 bool branchTaken; 159 uint64_t mispredPC; 160 uint64_t nextPC; 161 162 // Represents the instruction that has either been retired or 163 // squashed. Similar to having a single bus that broadcasts the 164 // retired or squashed sequence number. 165 InstSeqNum doneSeqNum; 166 167 //Just in case we want to do a commit/squash on a cycle 168 //(necessary for multiple ROBs?) 169 bool commitInsts; 170 InstSeqNum squashSeqNum; 171 172 // Communication specifically to the IQ to tell the IQ that it can 173 // schedule a non-speculative instruction. 174 InstSeqNum nonSpecSeqNum; 175 176 // Hack for now to send back an uncached access to the IEW stage. 177 typedef typename Impl::DynInstPtr DynInstPtr; 178 bool uncached; 179 DynInstPtr uncachedLoad; 180 181 bool interruptPending; 182 bool clearInterrupt; 183 }; 184 185 commitComm commitInfo[Impl::MaxThreads]; 186 187 bool decodeBlock[Impl::MaxThreads]; 188 bool decodeUnblock[Impl::MaxThreads]; 189 bool renameBlock[Impl::MaxThreads]; 190 bool renameUnblock[Impl::MaxThreads]; 191 bool iewBlock[Impl::MaxThreads]; 192 bool iewUnblock[Impl::MaxThreads]; 193 bool commitBlock[Impl::MaxThreads]; 194 bool commitUnblock[Impl::MaxThreads]; 195}; 196 197#endif //__CPU_O3_COMM_HH__ 198