comm.hh revision 1684 
1#ifndef __CPU_BETA_CPU_COMM_HH__
2#define __CPU_BETA_CPU_COMM_HH__
3
4#include <stdint.h>
5#include <vector>
6
7#include "arch/alpha/isa_traits.hh"
8#include "cpu/inst_seq.hh"
9
10// Find better place to put this typedef.
11// The impl might be the best place for this.
12typedef short int PhysRegIndex;
13
14template<class Impl>
15struct SimpleFetchSimpleDecode {
16    typedef typename Impl::DynInstPtr DynInstPtr;
17
18    int size;
19
20    DynInstPtr insts[Impl::MaxWidth];
21};
22
23template<class Impl>
24struct SimpleDecodeSimpleRename {
25    typedef typename Impl::DynInstPtr DynInstPtr;
26
27    int size;
28
29    DynInstPtr insts[Impl::MaxWidth];
30};
31
32template<class Impl>
33struct SimpleRenameSimpleIEW {
34    typedef typename Impl::DynInstPtr DynInstPtr;
35
36    int size;
37
38    DynInstPtr insts[Impl::MaxWidth];
39};
40
41template<class Impl>
42struct SimpleIEWSimpleCommit {
43    typedef typename Impl::DynInstPtr DynInstPtr;
44
45    int size;
46
47    DynInstPtr insts[Impl::MaxWidth];
48
49    bool squash;
50    bool branchMispredict;
51    bool branchTaken;
52    uint64_t mispredPC;
53    uint64_t nextPC;
54    InstSeqNum squashedSeqNum;
55};
56
57template<class Impl>
58struct IssueStruct {
59    typedef typename Impl::DynInstPtr DynInstPtr;
60
61    int size;
62
63    DynInstPtr insts[Impl::MaxWidth];
64};
65
66struct TimeBufStruct {
67    struct decodeComm {
68        bool squash;
69        bool stall;
70        bool predIncorrect;
71        uint64_t branchAddr;
72
73        InstSeqNum doneSeqNum;
74
75        // Might want to package this kind of branch stuff into a single
76        // struct as it is used pretty frequently.
77        bool branchMispredict;
78        bool branchTaken;
79        uint64_t mispredPC;
80        uint64_t nextPC;
81    };
82
83    decodeComm decodeInfo;
84
85    // Rename can't actually tell anything to squash or send a new PC back
86    // because it doesn't do anything along those lines.  But maybe leave
87    // these fields in here to keep the stages mostly orthagonal.
88    struct renameComm {
89        bool squash;
90        bool stall;
91
92        uint64_t nextPC;
93    };
94
95    renameComm renameInfo;
96
97    struct iewComm {
98        bool stall;
99
100        // Also eventually include skid buffer space.
101        unsigned freeIQEntries;
102    };
103
104    iewComm iewInfo;
105
106    struct commitComm {
107        bool squash;
108        bool stall;
109        unsigned freeROBEntries;
110
111        bool branchMispredict;
112        bool branchTaken;
113        uint64_t mispredPC;
114        uint64_t nextPC;
115
116        bool robSquashing;
117
118        // Represents the instruction that has either been retired or
119        // squashed.  Similar to having a single bus that broadcasts the
120        // retired or squashed sequence number.
121        InstSeqNum doneSeqNum;
122
123        // Extra bit of information so that the LDSTQ only updates when it
124        // needs to.
125        bool commitIsLoad;
126
127        // Communication specifically to the IQ to tell the IQ that it can
128        // schedule a non-speculative instruction.
129        InstSeqNum nonSpecSeqNum;
130    };
131
132    commitComm commitInfo;
133};
134
135#endif //__CPU_BETA_CPU_COMM_HH__
136