comm.hh revision 13610
11689SN/A/* 213610Sgiacomo.gabrielli@arm.com * Copyright (c) 2011, 2016-2017 ARM Limited 310239Sbinhpham@cs.rutgers.edu * Copyright (c) 2013 Advanced Micro Devices, Inc. 48137SAli.Saidi@ARM.com * All rights reserved 58137SAli.Saidi@ARM.com * 68137SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 78137SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 88137SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 98137SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 108137SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 118137SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 128137SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 138137SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 148137SAli.Saidi@ARM.com * 152329SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 161689SN/A * All rights reserved. 171689SN/A * 181689SN/A * Redistribution and use in source and binary forms, with or without 191689SN/A * modification, are permitted provided that the following conditions are 201689SN/A * met: redistributions of source code must retain the above copyright 211689SN/A * notice, this list of conditions and the following disclaimer; 221689SN/A * redistributions in binary form must reproduce the above copyright 231689SN/A * notice, this list of conditions and the following disclaimer in the 241689SN/A * documentation and/or other materials provided with the distribution; 251689SN/A * neither the name of the copyright holders nor the names of its 261689SN/A * contributors may be used to endorse or promote products derived from 271689SN/A * this software without specific prior written permission. 281689SN/A * 291689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 301689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 311689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 321689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 331689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 341689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 351689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 361689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 371689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 381689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 391689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665Ssaidi@eecs.umich.edu * 412665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 4212105Snathanael.premillieu@arm.com * Nathanael Premillieu 431689SN/A */ 441689SN/A 452292SN/A#ifndef __CPU_O3_COMM_HH__ 462292SN/A#define __CPU_O3_COMM_HH__ 471060SN/A 481061SN/A#include <vector> 491684SN/A 507720Sgblack@eecs.umich.edu#include "arch/types.hh" 516216Snate@binkert.org#include "base/types.hh" 526216Snate@binkert.org#include "cpu/inst_seq.hh" 532980Sgblack@eecs.umich.edu#include "sim/faults.hh" 541060SN/A 5512106SRekai.GonzalezAlberquilla@arm.com/** Physical register index type. 5612106SRekai.GonzalezAlberquilla@arm.com * Although the Impl might be a better for this, but there are a few classes 5712106SRekai.GonzalezAlberquilla@arm.com * that need this typedef yet are not templated on the Impl. 5812106SRekai.GonzalezAlberquilla@arm.com */ 5912106SRekai.GonzalezAlberquilla@arm.comusing PhysRegIndex = short int; 6012106SRekai.GonzalezAlberquilla@arm.com 6112106SRekai.GonzalezAlberquilla@arm.com/** Physical register ID. 6212106SRekai.GonzalezAlberquilla@arm.com * Like a register ID but physical. The inheritance is private because the 6312106SRekai.GonzalezAlberquilla@arm.com * only relationship between this types is functional, and it is done to 6412106SRekai.GonzalezAlberquilla@arm.com * prevent code replication. */ 6512106SRekai.GonzalezAlberquilla@arm.comclass PhysRegId : private RegId { 6612106SRekai.GonzalezAlberquilla@arm.com private: 6712105Snathanael.premillieu@arm.com PhysRegIndex flatIdx; 6812106SRekai.GonzalezAlberquilla@arm.com 6912106SRekai.GonzalezAlberquilla@arm.com public: 7012106SRekai.GonzalezAlberquilla@arm.com explicit PhysRegId() : RegId(IntRegClass, -1), flatIdx(-1) {} 7112106SRekai.GonzalezAlberquilla@arm.com 7212106SRekai.GonzalezAlberquilla@arm.com /** Scalar PhysRegId constructor. */ 7312106SRekai.GonzalezAlberquilla@arm.com explicit PhysRegId(RegClass _regClass, PhysRegIndex _regIdx, 7412105Snathanael.premillieu@arm.com PhysRegIndex _flatIdx) 7512106SRekai.GonzalezAlberquilla@arm.com : RegId(_regClass, _regIdx), flatIdx(_flatIdx) 7612105Snathanael.premillieu@arm.com {} 7712105Snathanael.premillieu@arm.com 7812109SRekai.GonzalezAlberquilla@arm.com /** Vector PhysRegId constructor (w/ elemIndex). */ 7912109SRekai.GonzalezAlberquilla@arm.com explicit PhysRegId(RegClass _regClass, PhysRegIndex _regIdx, 8012109SRekai.GonzalezAlberquilla@arm.com ElemIndex elem_idx, PhysRegIndex flat_idx) 8112109SRekai.GonzalezAlberquilla@arm.com : RegId(_regClass, _regIdx, elem_idx), flatIdx(flat_idx) { } 8212109SRekai.GonzalezAlberquilla@arm.com 8312106SRekai.GonzalezAlberquilla@arm.com /** Visible RegId methods */ 8412106SRekai.GonzalezAlberquilla@arm.com /** @{ */ 8512106SRekai.GonzalezAlberquilla@arm.com using RegId::index; 8612106SRekai.GonzalezAlberquilla@arm.com using RegId::classValue; 8712106SRekai.GonzalezAlberquilla@arm.com using RegId::isZeroReg; 8812106SRekai.GonzalezAlberquilla@arm.com using RegId::className; 8912109SRekai.GonzalezAlberquilla@arm.com using RegId::elemIndex; 9012106SRekai.GonzalezAlberquilla@arm.com /** @} */ 9112106SRekai.GonzalezAlberquilla@arm.com /** 9212106SRekai.GonzalezAlberquilla@arm.com * Explicit forward methods, to prevent comparisons of PhysRegId with 9312106SRekai.GonzalezAlberquilla@arm.com * RegIds. 9412106SRekai.GonzalezAlberquilla@arm.com */ 9512106SRekai.GonzalezAlberquilla@arm.com /** @{ */ 9612106SRekai.GonzalezAlberquilla@arm.com bool operator<(const PhysRegId& that) const { 9712106SRekai.GonzalezAlberquilla@arm.com return RegId::operator<(that); 9812106SRekai.GonzalezAlberquilla@arm.com } 9912106SRekai.GonzalezAlberquilla@arm.com 10012105Snathanael.premillieu@arm.com bool operator==(const PhysRegId& that) const { 10112106SRekai.GonzalezAlberquilla@arm.com return RegId::operator==(that); 10212105Snathanael.premillieu@arm.com } 10312105Snathanael.premillieu@arm.com 10412105Snathanael.premillieu@arm.com bool operator!=(const PhysRegId& that) const { 10512106SRekai.GonzalezAlberquilla@arm.com return RegId::operator!=(that); 10612105Snathanael.premillieu@arm.com } 10712106SRekai.GonzalezAlberquilla@arm.com /** @} */ 10812105Snathanael.premillieu@arm.com 10912105Snathanael.premillieu@arm.com /** @return true if it is an integer physical register. */ 11012106SRekai.GonzalezAlberquilla@arm.com bool isIntPhysReg() const { return isIntReg(); } 11112105Snathanael.premillieu@arm.com 11212105Snathanael.premillieu@arm.com /** @return true if it is a floating-point physical register. */ 11312106SRekai.GonzalezAlberquilla@arm.com bool isFloatPhysReg() const { return isFloatReg(); } 11412105Snathanael.premillieu@arm.com 11512105Snathanael.premillieu@arm.com /** @Return true if it is a condition-code physical register. */ 11612106SRekai.GonzalezAlberquilla@arm.com bool isCCPhysReg() const { return isCCReg(); } 11712106SRekai.GonzalezAlberquilla@arm.com 11812109SRekai.GonzalezAlberquilla@arm.com /** @Return true if it is a vector physical register. */ 11912109SRekai.GonzalezAlberquilla@arm.com bool isVectorPhysReg() const { return isVecReg(); } 12012109SRekai.GonzalezAlberquilla@arm.com 12112109SRekai.GonzalezAlberquilla@arm.com /** @Return true if it is a vector element physical register. */ 12212109SRekai.GonzalezAlberquilla@arm.com bool isVectorPhysElem() const { return isVecElem(); } 12312109SRekai.GonzalezAlberquilla@arm.com 12413610Sgiacomo.gabrielli@arm.com /** @return true if it is a vector predicate physical register. */ 12513610Sgiacomo.gabrielli@arm.com bool isVecPredPhysReg() const { return isVecPredReg(); } 12613610Sgiacomo.gabrielli@arm.com 12712106SRekai.GonzalezAlberquilla@arm.com /** @Return true if it is a condition-code physical register. */ 12812106SRekai.GonzalezAlberquilla@arm.com bool isMiscPhysReg() const { return isMiscReg(); } 12912105Snathanael.premillieu@arm.com 13012105Snathanael.premillieu@arm.com /** 13112105Snathanael.premillieu@arm.com * Returns true if this register is always associated to the same 13212105Snathanael.premillieu@arm.com * architectural register. 13312105Snathanael.premillieu@arm.com */ 13412105Snathanael.premillieu@arm.com bool isFixedMapping() const 13512105Snathanael.premillieu@arm.com { 13612106SRekai.GonzalezAlberquilla@arm.com return !isRenameable(); 13712105Snathanael.premillieu@arm.com } 13812106SRekai.GonzalezAlberquilla@arm.com 13912106SRekai.GonzalezAlberquilla@arm.com /** Flat index accessor */ 14012106SRekai.GonzalezAlberquilla@arm.com const PhysRegIndex& flatIndex() const { return flatIdx; } 14112109SRekai.GonzalezAlberquilla@arm.com 14212109SRekai.GonzalezAlberquilla@arm.com static PhysRegId elemId(const PhysRegId* vid, ElemIndex elem) 14312109SRekai.GonzalezAlberquilla@arm.com { 14412109SRekai.GonzalezAlberquilla@arm.com assert(vid->isVectorPhysReg()); 14512109SRekai.GonzalezAlberquilla@arm.com return PhysRegId(VecElemClass, vid->index(), elem); 14612109SRekai.GonzalezAlberquilla@arm.com } 14712105Snathanael.premillieu@arm.com}; 14812105Snathanael.premillieu@arm.com 14912109SRekai.GonzalezAlberquilla@arm.com/** Constant pointer definition. 15012109SRekai.GonzalezAlberquilla@arm.com * PhysRegIds only need to be created once and then we can just share 15112109SRekai.GonzalezAlberquilla@arm.com * pointers */ 15212109SRekai.GonzalezAlberquilla@arm.comusing PhysRegIdPtr = const PhysRegId*; 1531060SN/A 1542348SN/A/** Struct that defines the information passed from fetch to decode. */ 1551060SN/Atemplate<class Impl> 1562292SN/Astruct DefaultFetchDefaultDecode { 1572292SN/A typedef typename Impl::DynInstPtr DynInstPtr; 1582292SN/A 1592292SN/A int size; 1602292SN/A 1612292SN/A DynInstPtr insts[Impl::MaxWidth]; 1622292SN/A Fault fetchFault; 1632292SN/A InstSeqNum fetchFaultSN; 1642292SN/A bool clearFetchFault; 1652292SN/A}; 1662292SN/A 1672348SN/A/** Struct that defines the information passed from decode to rename. */ 1682292SN/Atemplate<class Impl> 1692292SN/Astruct DefaultDecodeDefaultRename { 1701061SN/A typedef typename Impl::DynInstPtr DynInstPtr; 1711061SN/A 1721061SN/A int size; 1731061SN/A 1741461SN/A DynInstPtr insts[Impl::MaxWidth]; 1751060SN/A}; 1761060SN/A 1772348SN/A/** Struct that defines the information passed from rename to IEW. */ 1781060SN/Atemplate<class Impl> 1792292SN/Astruct DefaultRenameDefaultIEW { 1801061SN/A typedef typename Impl::DynInstPtr DynInstPtr; 1811061SN/A 1821061SN/A int size; 1831061SN/A 1841461SN/A DynInstPtr insts[Impl::MaxWidth]; 1851060SN/A}; 1861060SN/A 1872348SN/A/** Struct that defines the information passed from IEW to commit. */ 1881060SN/Atemplate<class Impl> 1892292SN/Astruct DefaultIEWDefaultCommit { 1901061SN/A typedef typename Impl::DynInstPtr DynInstPtr; 1911061SN/A 1921061SN/A int size; 1931061SN/A 1941461SN/A DynInstPtr insts[Impl::MaxWidth]; 1959046SAli.Saidi@ARM.com DynInstPtr mispredictInst[Impl::MaxThreads]; 1969046SAli.Saidi@ARM.com Addr mispredPC[Impl::MaxThreads]; 1979046SAli.Saidi@ARM.com InstSeqNum squashedSeqNum[Impl::MaxThreads]; 1989046SAli.Saidi@ARM.com TheISA::PCState pc[Impl::MaxThreads]; 1991062SN/A 2002292SN/A bool squash[Impl::MaxThreads]; 2012292SN/A bool branchMispredict[Impl::MaxThreads]; 2022292SN/A bool branchTaken[Impl::MaxThreads]; 2032292SN/A bool includeSquashInst[Impl::MaxThreads]; 2041060SN/A}; 2051060SN/A 2061060SN/Atemplate<class Impl> 2071060SN/Astruct IssueStruct { 2081061SN/A typedef typename Impl::DynInstPtr DynInstPtr; 2091061SN/A 2101061SN/A int size; 2111061SN/A 2121461SN/A DynInstPtr insts[Impl::MaxWidth]; 2131060SN/A}; 2141060SN/A 2152348SN/A/** Struct that defines all backwards communication. */ 2162292SN/Atemplate<class Impl> 2171060SN/Astruct TimeBufStruct { 2187851SMatt.Horsnell@arm.com typedef typename Impl::DynInstPtr DynInstPtr; 2191060SN/A struct decodeComm { 2209260SAli.Saidi@ARM.com TheISA::PCState nextPC; 2219046SAli.Saidi@ARM.com DynInstPtr mispredictInst; 2229046SAli.Saidi@ARM.com DynInstPtr squashInst; 2239260SAli.Saidi@ARM.com InstSeqNum doneSeqNum; 2249046SAli.Saidi@ARM.com Addr mispredPC; 2259260SAli.Saidi@ARM.com uint64_t branchAddr; 2269046SAli.Saidi@ARM.com unsigned branchCount; 2271060SN/A bool squash; 2281060SN/A bool predIncorrect; 2291061SN/A bool branchMispredict; 2301061SN/A bool branchTaken; 2311060SN/A }; 2321060SN/A 2332292SN/A decodeComm decodeInfo[Impl::MaxThreads]; 2341060SN/A 2351060SN/A struct renameComm { 2361060SN/A }; 2371060SN/A 2382292SN/A renameComm renameInfo[Impl::MaxThreads]; 2391060SN/A 2401060SN/A struct iewComm { 2412292SN/A // Also eventually include skid buffer space. 2422292SN/A unsigned freeIQEntries; 24310239Sbinhpham@cs.rutgers.edu unsigned freeLQEntries; 24410239Sbinhpham@cs.rutgers.edu unsigned freeSQEntries; 24510239Sbinhpham@cs.rutgers.edu unsigned dispatchedToLQ; 24610239Sbinhpham@cs.rutgers.edu unsigned dispatchedToSQ; 2471060SN/A 2482292SN/A unsigned iqCount; 2492292SN/A unsigned ldstqCount; 2502292SN/A 2512292SN/A unsigned dispatched; 2529260SAli.Saidi@ARM.com bool usedIQ; 2539260SAli.Saidi@ARM.com bool usedLSQ; 2541060SN/A }; 2551060SN/A 2562292SN/A iewComm iewInfo[Impl::MaxThreads]; 2571060SN/A 2581060SN/A struct commitComm { 2599260SAli.Saidi@ARM.com ///////////////////////////////////////////////////////////////////// 2609260SAli.Saidi@ARM.com // This code has been re-structured for better packing of variables 2619260SAli.Saidi@ARM.com // instead of by stage which is the more logical way to arrange the 2629260SAli.Saidi@ARM.com // data. 2639260SAli.Saidi@ARM.com // F = Fetch 2649260SAli.Saidi@ARM.com // D = Decode 2659260SAli.Saidi@ARM.com // I = IEW 2669260SAli.Saidi@ARM.com // R = Rename 2679260SAli.Saidi@ARM.com // As such each member is annotated with who consumes it 2689260SAli.Saidi@ARM.com // e.g. bool variable name // *F,R for Fetch and Rename 2699260SAli.Saidi@ARM.com ///////////////////////////////////////////////////////////////////// 2702292SN/A 2719260SAli.Saidi@ARM.com /// The pc of the next instruction to execute. This is the next 2729260SAli.Saidi@ARM.com /// instruction for a branch mispredict, but the same instruction for 2739260SAli.Saidi@ARM.com /// order violation and the like 2749260SAli.Saidi@ARM.com TheISA::PCState pc; // *F 2751060SN/A 2769260SAli.Saidi@ARM.com /// Provide fetch the instruction that mispredicted, if this 2779260SAli.Saidi@ARM.com /// pointer is not-null a misprediction occured 2789260SAli.Saidi@ARM.com DynInstPtr mispredictInst; // *F 2791061SN/A 2809260SAli.Saidi@ARM.com /// Instruction that caused the a non-mispredict squash 2819260SAli.Saidi@ARM.com DynInstPtr squashInst; // *F 2821061SN/A 28310824SAndreas.Sandberg@ARM.com /// Hack for now to send back a strictly ordered access to the 28410824SAndreas.Sandberg@ARM.com /// IEW stage. 28510824SAndreas.Sandberg@ARM.com DynInstPtr strictlyOrderedLoad; // *I 2868137SAli.Saidi@ARM.com 2879260SAli.Saidi@ARM.com /// Communication specifically to the IQ to tell the IQ that it can 2889260SAli.Saidi@ARM.com /// schedule a non-speculative instruction. 2899260SAli.Saidi@ARM.com InstSeqNum nonSpecSeqNum; // *I 2908137SAli.Saidi@ARM.com 2919260SAli.Saidi@ARM.com /// Represents the instruction that has either been retired or 2929260SAli.Saidi@ARM.com /// squashed. Similar to having a single bus that broadcasts the 2939260SAli.Saidi@ARM.com /// retired or squashed sequence number. 2949260SAli.Saidi@ARM.com InstSeqNum doneSeqNum; // *F, I 2958137SAli.Saidi@ARM.com 2969260SAli.Saidi@ARM.com /// Tell Rename how many free entries it has in the ROB 2979260SAli.Saidi@ARM.com unsigned freeROBEntries; // *R 2982292SN/A 2999260SAli.Saidi@ARM.com bool squash; // *F, D, R, I 3009260SAli.Saidi@ARM.com bool robSquashing; // *F, D, R, I 3019260SAli.Saidi@ARM.com 3029260SAli.Saidi@ARM.com /// Rename should re-read number of free rob entries 3039260SAli.Saidi@ARM.com bool usedROB; // *R 3049260SAli.Saidi@ARM.com 3059260SAli.Saidi@ARM.com /// Notify Rename that the ROB is empty 3069260SAli.Saidi@ARM.com bool emptyROB; // *R 3079260SAli.Saidi@ARM.com 3089260SAli.Saidi@ARM.com /// Was the branch taken or not 3099260SAli.Saidi@ARM.com bool branchTaken; // *F 3109260SAli.Saidi@ARM.com /// If an interrupt is pending and fetch should stall 3119260SAli.Saidi@ARM.com bool interruptPending; // *F 3129260SAli.Saidi@ARM.com /// If the interrupt ended up being cleared before being handled 3139260SAli.Saidi@ARM.com bool clearInterrupt; // *F 3149260SAli.Saidi@ARM.com 31510824SAndreas.Sandberg@ARM.com /// Hack for now to send back an strictly ordered access to 31610824SAndreas.Sandberg@ARM.com /// the IEW stage. 31710824SAndreas.Sandberg@ARM.com bool strictlyOrdered; // *I 3182292SN/A 3191060SN/A }; 3201060SN/A 3212292SN/A commitComm commitInfo[Impl::MaxThreads]; 3222292SN/A 3232292SN/A bool decodeBlock[Impl::MaxThreads]; 3242292SN/A bool decodeUnblock[Impl::MaxThreads]; 3252292SN/A bool renameBlock[Impl::MaxThreads]; 3262292SN/A bool renameUnblock[Impl::MaxThreads]; 3272292SN/A bool iewBlock[Impl::MaxThreads]; 3282292SN/A bool iewUnblock[Impl::MaxThreads]; 3291060SN/A}; 3301060SN/A 3312292SN/A#endif //__CPU_O3_COMM_HH__ 332