comm.hh revision 12106
11689SN/A/* 212105Snathanael.premillieu@arm.com * Copyright (c) 2011, 2016 ARM Limited 310239Sbinhpham@cs.rutgers.edu * Copyright (c) 2013 Advanced Micro Devices, Inc. 48137SAli.Saidi@ARM.com * All rights reserved 58137SAli.Saidi@ARM.com * 68137SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 78137SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 88137SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 98137SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 108137SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 118137SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 128137SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 138137SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 148137SAli.Saidi@ARM.com * 152329SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 161689SN/A * All rights reserved. 171689SN/A * 181689SN/A * Redistribution and use in source and binary forms, with or without 191689SN/A * modification, are permitted provided that the following conditions are 201689SN/A * met: redistributions of source code must retain the above copyright 211689SN/A * notice, this list of conditions and the following disclaimer; 221689SN/A * redistributions in binary form must reproduce the above copyright 231689SN/A * notice, this list of conditions and the following disclaimer in the 241689SN/A * documentation and/or other materials provided with the distribution; 251689SN/A * neither the name of the copyright holders nor the names of its 261689SN/A * contributors may be used to endorse or promote products derived from 271689SN/A * this software without specific prior written permission. 281689SN/A * 291689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 301689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 311689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 321689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 331689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 341689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 351689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 361689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 371689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 381689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 391689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665Ssaidi@eecs.umich.edu * 412665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 4212105Snathanael.premillieu@arm.com * Nathanael Premillieu 431689SN/A */ 441689SN/A 452292SN/A#ifndef __CPU_O3_COMM_HH__ 462292SN/A#define __CPU_O3_COMM_HH__ 471060SN/A 481061SN/A#include <vector> 491684SN/A 507720Sgblack@eecs.umich.edu#include "arch/types.hh" 516216Snate@binkert.org#include "base/types.hh" 526216Snate@binkert.org#include "cpu/inst_seq.hh" 532980Sgblack@eecs.umich.edu#include "sim/faults.hh" 541060SN/A 5512106SRekai.GonzalezAlberquilla@arm.com/** Physical register index type. 5612106SRekai.GonzalezAlberquilla@arm.com * Although the Impl might be a better for this, but there are a few classes 5712106SRekai.GonzalezAlberquilla@arm.com * that need this typedef yet are not templated on the Impl. 5812106SRekai.GonzalezAlberquilla@arm.com */ 5912106SRekai.GonzalezAlberquilla@arm.comusing PhysRegIndex = short int; 6012106SRekai.GonzalezAlberquilla@arm.com 6112106SRekai.GonzalezAlberquilla@arm.com/** Physical register ID. 6212106SRekai.GonzalezAlberquilla@arm.com * Like a register ID but physical. The inheritance is private because the 6312106SRekai.GonzalezAlberquilla@arm.com * only relationship between this types is functional, and it is done to 6412106SRekai.GonzalezAlberquilla@arm.com * prevent code replication. */ 6512106SRekai.GonzalezAlberquilla@arm.comclass PhysRegId : private RegId { 6612106SRekai.GonzalezAlberquilla@arm.com private: 6712105Snathanael.premillieu@arm.com PhysRegIndex flatIdx; 6812106SRekai.GonzalezAlberquilla@arm.com 6912106SRekai.GonzalezAlberquilla@arm.com public: 7012106SRekai.GonzalezAlberquilla@arm.com explicit PhysRegId() : RegId(IntRegClass, -1), flatIdx(-1) {} 7112106SRekai.GonzalezAlberquilla@arm.com 7212106SRekai.GonzalezAlberquilla@arm.com /** Scalar PhysRegId constructor. */ 7312106SRekai.GonzalezAlberquilla@arm.com explicit PhysRegId(RegClass _regClass, PhysRegIndex _regIdx, 7412105Snathanael.premillieu@arm.com PhysRegIndex _flatIdx) 7512106SRekai.GonzalezAlberquilla@arm.com : RegId(_regClass, _regIdx), flatIdx(_flatIdx) 7612105Snathanael.premillieu@arm.com {} 7712105Snathanael.premillieu@arm.com 7812106SRekai.GonzalezAlberquilla@arm.com /** Visible RegId methods */ 7912106SRekai.GonzalezAlberquilla@arm.com /** @{ */ 8012106SRekai.GonzalezAlberquilla@arm.com using RegId::index; 8112106SRekai.GonzalezAlberquilla@arm.com using RegId::classValue; 8212106SRekai.GonzalezAlberquilla@arm.com using RegId::isZeroReg; 8312106SRekai.GonzalezAlberquilla@arm.com using RegId::className; 8412106SRekai.GonzalezAlberquilla@arm.com /** @} */ 8512106SRekai.GonzalezAlberquilla@arm.com /** 8612106SRekai.GonzalezAlberquilla@arm.com * Explicit forward methods, to prevent comparisons of PhysRegId with 8712106SRekai.GonzalezAlberquilla@arm.com * RegIds. 8812106SRekai.GonzalezAlberquilla@arm.com */ 8912106SRekai.GonzalezAlberquilla@arm.com /** @{ */ 9012106SRekai.GonzalezAlberquilla@arm.com bool operator<(const PhysRegId& that) const { 9112106SRekai.GonzalezAlberquilla@arm.com return RegId::operator<(that); 9212106SRekai.GonzalezAlberquilla@arm.com } 9312106SRekai.GonzalezAlberquilla@arm.com 9412105Snathanael.premillieu@arm.com bool operator==(const PhysRegId& that) const { 9512106SRekai.GonzalezAlberquilla@arm.com return RegId::operator==(that); 9612105Snathanael.premillieu@arm.com } 9712105Snathanael.premillieu@arm.com 9812105Snathanael.premillieu@arm.com bool operator!=(const PhysRegId& that) const { 9912106SRekai.GonzalezAlberquilla@arm.com return RegId::operator!=(that); 10012105Snathanael.premillieu@arm.com } 10112106SRekai.GonzalezAlberquilla@arm.com /** @} */ 10212105Snathanael.premillieu@arm.com 10312105Snathanael.premillieu@arm.com /** @return true if it is an integer physical register. */ 10412106SRekai.GonzalezAlberquilla@arm.com bool isIntPhysReg() const { return isIntReg(); } 10512105Snathanael.premillieu@arm.com 10612105Snathanael.premillieu@arm.com /** @return true if it is a floating-point physical register. */ 10712106SRekai.GonzalezAlberquilla@arm.com bool isFloatPhysReg() const { return isFloatReg(); } 10812105Snathanael.premillieu@arm.com 10912105Snathanael.premillieu@arm.com /** @Return true if it is a condition-code physical register. */ 11012106SRekai.GonzalezAlberquilla@arm.com bool isCCPhysReg() const { return isCCReg(); } 11112106SRekai.GonzalezAlberquilla@arm.com 11212106SRekai.GonzalezAlberquilla@arm.com /** @Return true if it is a condition-code physical register. */ 11312106SRekai.GonzalezAlberquilla@arm.com bool isMiscPhysReg() const { return isMiscReg(); } 11412105Snathanael.premillieu@arm.com 11512105Snathanael.premillieu@arm.com /** 11612105Snathanael.premillieu@arm.com * Returns true if this register is always associated to the same 11712105Snathanael.premillieu@arm.com * architectural register. 11812105Snathanael.premillieu@arm.com */ 11912105Snathanael.premillieu@arm.com bool isFixedMapping() const 12012105Snathanael.premillieu@arm.com { 12112106SRekai.GonzalezAlberquilla@arm.com return !isRenameable(); 12212105Snathanael.premillieu@arm.com } 12312106SRekai.GonzalezAlberquilla@arm.com 12412106SRekai.GonzalezAlberquilla@arm.com /** Flat index accessor */ 12512106SRekai.GonzalezAlberquilla@arm.com const PhysRegIndex& flatIndex() const { return flatIdx; } 12612105Snathanael.premillieu@arm.com}; 12712105Snathanael.premillieu@arm.com 12812105Snathanael.premillieu@arm.com// PhysRegIds only need to be created once and then we can use the following 12912105Snathanael.premillieu@arm.com// to work with them 13012105Snathanael.premillieu@arm.comtypedef const PhysRegId* PhysRegIdPtr; 1311060SN/A 1322348SN/A/** Struct that defines the information passed from fetch to decode. */ 1331060SN/Atemplate<class Impl> 1342292SN/Astruct DefaultFetchDefaultDecode { 1352292SN/A typedef typename Impl::DynInstPtr DynInstPtr; 1362292SN/A 1372292SN/A int size; 1382292SN/A 1392292SN/A DynInstPtr insts[Impl::MaxWidth]; 1402292SN/A Fault fetchFault; 1412292SN/A InstSeqNum fetchFaultSN; 1422292SN/A bool clearFetchFault; 1432292SN/A}; 1442292SN/A 1452348SN/A/** Struct that defines the information passed from decode to rename. */ 1462292SN/Atemplate<class Impl> 1472292SN/Astruct DefaultDecodeDefaultRename { 1481061SN/A typedef typename Impl::DynInstPtr DynInstPtr; 1491061SN/A 1501061SN/A int size; 1511061SN/A 1521461SN/A DynInstPtr insts[Impl::MaxWidth]; 1531060SN/A}; 1541060SN/A 1552348SN/A/** Struct that defines the information passed from rename to IEW. */ 1561060SN/Atemplate<class Impl> 1572292SN/Astruct DefaultRenameDefaultIEW { 1581061SN/A typedef typename Impl::DynInstPtr DynInstPtr; 1591061SN/A 1601061SN/A int size; 1611061SN/A 1621461SN/A DynInstPtr insts[Impl::MaxWidth]; 1631060SN/A}; 1641060SN/A 1652348SN/A/** Struct that defines the information passed from IEW to commit. */ 1661060SN/Atemplate<class Impl> 1672292SN/Astruct DefaultIEWDefaultCommit { 1681061SN/A typedef typename Impl::DynInstPtr DynInstPtr; 1691061SN/A 1701061SN/A int size; 1711061SN/A 1721461SN/A DynInstPtr insts[Impl::MaxWidth]; 1739046SAli.Saidi@ARM.com DynInstPtr mispredictInst[Impl::MaxThreads]; 1749046SAli.Saidi@ARM.com Addr mispredPC[Impl::MaxThreads]; 1759046SAli.Saidi@ARM.com InstSeqNum squashedSeqNum[Impl::MaxThreads]; 1769046SAli.Saidi@ARM.com TheISA::PCState pc[Impl::MaxThreads]; 1771062SN/A 1782292SN/A bool squash[Impl::MaxThreads]; 1792292SN/A bool branchMispredict[Impl::MaxThreads]; 1802292SN/A bool branchTaken[Impl::MaxThreads]; 1812292SN/A bool includeSquashInst[Impl::MaxThreads]; 1821060SN/A}; 1831060SN/A 1841060SN/Atemplate<class Impl> 1851060SN/Astruct IssueStruct { 1861061SN/A typedef typename Impl::DynInstPtr DynInstPtr; 1871061SN/A 1881061SN/A int size; 1891061SN/A 1901461SN/A DynInstPtr insts[Impl::MaxWidth]; 1911060SN/A}; 1921060SN/A 1932348SN/A/** Struct that defines all backwards communication. */ 1942292SN/Atemplate<class Impl> 1951060SN/Astruct TimeBufStruct { 1967851SMatt.Horsnell@arm.com typedef typename Impl::DynInstPtr DynInstPtr; 1971060SN/A struct decodeComm { 1989260SAli.Saidi@ARM.com TheISA::PCState nextPC; 1999046SAli.Saidi@ARM.com DynInstPtr mispredictInst; 2009046SAli.Saidi@ARM.com DynInstPtr squashInst; 2019260SAli.Saidi@ARM.com InstSeqNum doneSeqNum; 2029046SAli.Saidi@ARM.com Addr mispredPC; 2039260SAli.Saidi@ARM.com uint64_t branchAddr; 2049046SAli.Saidi@ARM.com unsigned branchCount; 2051060SN/A bool squash; 2061060SN/A bool predIncorrect; 2071061SN/A bool branchMispredict; 2081061SN/A bool branchTaken; 2091060SN/A }; 2101060SN/A 2112292SN/A decodeComm decodeInfo[Impl::MaxThreads]; 2121060SN/A 2131060SN/A struct renameComm { 2141060SN/A }; 2151060SN/A 2162292SN/A renameComm renameInfo[Impl::MaxThreads]; 2171060SN/A 2181060SN/A struct iewComm { 2192292SN/A // Also eventually include skid buffer space. 2202292SN/A unsigned freeIQEntries; 22110239Sbinhpham@cs.rutgers.edu unsigned freeLQEntries; 22210239Sbinhpham@cs.rutgers.edu unsigned freeSQEntries; 22310239Sbinhpham@cs.rutgers.edu unsigned dispatchedToLQ; 22410239Sbinhpham@cs.rutgers.edu unsigned dispatchedToSQ; 2251060SN/A 2262292SN/A unsigned iqCount; 2272292SN/A unsigned ldstqCount; 2282292SN/A 2292292SN/A unsigned dispatched; 2309260SAli.Saidi@ARM.com bool usedIQ; 2319260SAli.Saidi@ARM.com bool usedLSQ; 2321060SN/A }; 2331060SN/A 2342292SN/A iewComm iewInfo[Impl::MaxThreads]; 2351060SN/A 2361060SN/A struct commitComm { 2379260SAli.Saidi@ARM.com ///////////////////////////////////////////////////////////////////// 2389260SAli.Saidi@ARM.com // This code has been re-structured for better packing of variables 2399260SAli.Saidi@ARM.com // instead of by stage which is the more logical way to arrange the 2409260SAli.Saidi@ARM.com // data. 2419260SAli.Saidi@ARM.com // F = Fetch 2429260SAli.Saidi@ARM.com // D = Decode 2439260SAli.Saidi@ARM.com // I = IEW 2449260SAli.Saidi@ARM.com // R = Rename 2459260SAli.Saidi@ARM.com // As such each member is annotated with who consumes it 2469260SAli.Saidi@ARM.com // e.g. bool variable name // *F,R for Fetch and Rename 2479260SAli.Saidi@ARM.com ///////////////////////////////////////////////////////////////////// 2482292SN/A 2499260SAli.Saidi@ARM.com /// The pc of the next instruction to execute. This is the next 2509260SAli.Saidi@ARM.com /// instruction for a branch mispredict, but the same instruction for 2519260SAli.Saidi@ARM.com /// order violation and the like 2529260SAli.Saidi@ARM.com TheISA::PCState pc; // *F 2531060SN/A 2549260SAli.Saidi@ARM.com /// Provide fetch the instruction that mispredicted, if this 2559260SAli.Saidi@ARM.com /// pointer is not-null a misprediction occured 2569260SAli.Saidi@ARM.com DynInstPtr mispredictInst; // *F 2571061SN/A 2589260SAli.Saidi@ARM.com /// Instruction that caused the a non-mispredict squash 2599260SAli.Saidi@ARM.com DynInstPtr squashInst; // *F 2601061SN/A 26110824SAndreas.Sandberg@ARM.com /// Hack for now to send back a strictly ordered access to the 26210824SAndreas.Sandberg@ARM.com /// IEW stage. 26310824SAndreas.Sandberg@ARM.com DynInstPtr strictlyOrderedLoad; // *I 2648137SAli.Saidi@ARM.com 2659260SAli.Saidi@ARM.com /// Communication specifically to the IQ to tell the IQ that it can 2669260SAli.Saidi@ARM.com /// schedule a non-speculative instruction. 2679260SAli.Saidi@ARM.com InstSeqNum nonSpecSeqNum; // *I 2688137SAli.Saidi@ARM.com 2699260SAli.Saidi@ARM.com /// Represents the instruction that has either been retired or 2709260SAli.Saidi@ARM.com /// squashed. Similar to having a single bus that broadcasts the 2719260SAli.Saidi@ARM.com /// retired or squashed sequence number. 2729260SAli.Saidi@ARM.com InstSeqNum doneSeqNum; // *F, I 2738137SAli.Saidi@ARM.com 2749260SAli.Saidi@ARM.com /// Tell Rename how many free entries it has in the ROB 2759260SAli.Saidi@ARM.com unsigned freeROBEntries; // *R 2762292SN/A 2779260SAli.Saidi@ARM.com bool squash; // *F, D, R, I 2789260SAli.Saidi@ARM.com bool robSquashing; // *F, D, R, I 2799260SAli.Saidi@ARM.com 2809260SAli.Saidi@ARM.com /// Rename should re-read number of free rob entries 2819260SAli.Saidi@ARM.com bool usedROB; // *R 2829260SAli.Saidi@ARM.com 2839260SAli.Saidi@ARM.com /// Notify Rename that the ROB is empty 2849260SAli.Saidi@ARM.com bool emptyROB; // *R 2859260SAli.Saidi@ARM.com 2869260SAli.Saidi@ARM.com /// Was the branch taken or not 2879260SAli.Saidi@ARM.com bool branchTaken; // *F 2889260SAli.Saidi@ARM.com /// If an interrupt is pending and fetch should stall 2899260SAli.Saidi@ARM.com bool interruptPending; // *F 2909260SAli.Saidi@ARM.com /// If the interrupt ended up being cleared before being handled 2919260SAli.Saidi@ARM.com bool clearInterrupt; // *F 2929260SAli.Saidi@ARM.com 29310824SAndreas.Sandberg@ARM.com /// Hack for now to send back an strictly ordered access to 29410824SAndreas.Sandberg@ARM.com /// the IEW stage. 29510824SAndreas.Sandberg@ARM.com bool strictlyOrdered; // *I 2962292SN/A 2971060SN/A }; 2981060SN/A 2992292SN/A commitComm commitInfo[Impl::MaxThreads]; 3002292SN/A 3012292SN/A bool decodeBlock[Impl::MaxThreads]; 3022292SN/A bool decodeUnblock[Impl::MaxThreads]; 3032292SN/A bool renameBlock[Impl::MaxThreads]; 3042292SN/A bool renameUnblock[Impl::MaxThreads]; 3052292SN/A bool iewBlock[Impl::MaxThreads]; 3062292SN/A bool iewUnblock[Impl::MaxThreads]; 3071060SN/A}; 3081060SN/A 3092292SN/A#endif //__CPU_O3_COMM_HH__ 310