comm.hh revision 12105
11689SN/A/* 212105Snathanael.premillieu@arm.com * Copyright (c) 2011, 2016 ARM Limited 310239Sbinhpham@cs.rutgers.edu * Copyright (c) 2013 Advanced Micro Devices, Inc. 48137SAli.Saidi@ARM.com * All rights reserved 58137SAli.Saidi@ARM.com * 68137SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 78137SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 88137SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 98137SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 108137SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 118137SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 128137SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 138137SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 148137SAli.Saidi@ARM.com * 152329SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 161689SN/A * All rights reserved. 171689SN/A * 181689SN/A * Redistribution and use in source and binary forms, with or without 191689SN/A * modification, are permitted provided that the following conditions are 201689SN/A * met: redistributions of source code must retain the above copyright 211689SN/A * notice, this list of conditions and the following disclaimer; 221689SN/A * redistributions in binary form must reproduce the above copyright 231689SN/A * notice, this list of conditions and the following disclaimer in the 241689SN/A * documentation and/or other materials provided with the distribution; 251689SN/A * neither the name of the copyright holders nor the names of its 261689SN/A * contributors may be used to endorse or promote products derived from 271689SN/A * this software without specific prior written permission. 281689SN/A * 291689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 301689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 311689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 321689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 331689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 341689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 351689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 361689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 371689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 381689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 391689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665Ssaidi@eecs.umich.edu * 412665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 4212105Snathanael.premillieu@arm.com * Nathanael Premillieu 431689SN/A */ 441689SN/A 452292SN/A#ifndef __CPU_O3_COMM_HH__ 462292SN/A#define __CPU_O3_COMM_HH__ 471060SN/A 481061SN/A#include <vector> 491684SN/A 507720Sgblack@eecs.umich.edu#include "arch/types.hh" 516216Snate@binkert.org#include "base/types.hh" 526216Snate@binkert.org#include "cpu/inst_seq.hh" 532980Sgblack@eecs.umich.edu#include "sim/faults.hh" 541060SN/A 552292SN/A// Typedef for physical register index type. Although the Impl would be the 562292SN/A// most likely location for this, there are a few classes that need this 572292SN/A// typedef yet are not templated on the Impl. For now it will be defined here. 581060SN/Atypedef short int PhysRegIndex; 5912105Snathanael.premillieu@arm.com// Physical register ID 6012105Snathanael.premillieu@arm.com// Associate a physical register index to a register class and 6112105Snathanael.premillieu@arm.com// so it is easy to track which type of register are used. 6212105Snathanael.premillieu@arm.com// A flat index is also provided for when it is useful to have a unified 6312105Snathanael.premillieu@arm.com// indexing (for the dependency graph and the scoreboard for example) 6412105Snathanael.premillieu@arm.comstruct PhysRegId { 6512105Snathanael.premillieu@arm.com RegClass regClass; 6612105Snathanael.premillieu@arm.com PhysRegIndex regIdx; 6712105Snathanael.premillieu@arm.com PhysRegIndex flatIdx; 6812105Snathanael.premillieu@arm.com PhysRegId(RegClass _regClass, PhysRegIndex _regIdx, 6912105Snathanael.premillieu@arm.com PhysRegIndex _flatIdx) 7012105Snathanael.premillieu@arm.com : regClass(_regClass), regIdx(_regIdx), flatIdx(_flatIdx) 7112105Snathanael.premillieu@arm.com {} 7212105Snathanael.premillieu@arm.com 7312105Snathanael.premillieu@arm.com bool operator==(const PhysRegId& that) const { 7412105Snathanael.premillieu@arm.com return regClass == that.regClass && regIdx == that.regIdx; 7512105Snathanael.premillieu@arm.com } 7612105Snathanael.premillieu@arm.com 7712105Snathanael.premillieu@arm.com bool operator!=(const PhysRegId& that) const { 7812105Snathanael.premillieu@arm.com return !(*this==that); 7912105Snathanael.premillieu@arm.com } 8012105Snathanael.premillieu@arm.com 8112105Snathanael.premillieu@arm.com bool isZeroReg() const 8212105Snathanael.premillieu@arm.com { 8312105Snathanael.premillieu@arm.com return (regIdx == TheISA::ZeroReg && 8412105Snathanael.premillieu@arm.com (regClass == IntRegClass || 8512105Snathanael.premillieu@arm.com (THE_ISA == ALPHA_ISA && regClass == FloatRegClass))); 8612105Snathanael.premillieu@arm.com } 8712105Snathanael.premillieu@arm.com 8812105Snathanael.premillieu@arm.com /** @return true if it is an integer physical register. */ 8912105Snathanael.premillieu@arm.com bool isIntPhysReg() const { return regClass == IntRegClass; } 9012105Snathanael.premillieu@arm.com 9112105Snathanael.premillieu@arm.com /** @return true if it is a floating-point physical register. */ 9212105Snathanael.premillieu@arm.com bool isFloatPhysReg() const { return regClass == FloatRegClass; } 9312105Snathanael.premillieu@arm.com 9412105Snathanael.premillieu@arm.com /** @Return true if it is a condition-code physical register. */ 9512105Snathanael.premillieu@arm.com bool isCCPhysReg() const { return regClass == CCRegClass; } 9612105Snathanael.premillieu@arm.com 9712105Snathanael.premillieu@arm.com /** 9812105Snathanael.premillieu@arm.com * Returns true if this register is always associated to the same 9912105Snathanael.premillieu@arm.com * architectural register. 10012105Snathanael.premillieu@arm.com */ 10112105Snathanael.premillieu@arm.com bool isFixedMapping() const 10212105Snathanael.premillieu@arm.com { 10312105Snathanael.premillieu@arm.com return regClass == MiscRegClass; 10412105Snathanael.premillieu@arm.com } 10512105Snathanael.premillieu@arm.com}; 10612105Snathanael.premillieu@arm.com 10712105Snathanael.premillieu@arm.com// PhysRegIds only need to be created once and then we can use the following 10812105Snathanael.premillieu@arm.com// to work with them 10912105Snathanael.premillieu@arm.comtypedef const PhysRegId* PhysRegIdPtr; 1101060SN/A 1112348SN/A/** Struct that defines the information passed from fetch to decode. */ 1121060SN/Atemplate<class Impl> 1132292SN/Astruct DefaultFetchDefaultDecode { 1142292SN/A typedef typename Impl::DynInstPtr DynInstPtr; 1152292SN/A 1162292SN/A int size; 1172292SN/A 1182292SN/A DynInstPtr insts[Impl::MaxWidth]; 1192292SN/A Fault fetchFault; 1202292SN/A InstSeqNum fetchFaultSN; 1212292SN/A bool clearFetchFault; 1222292SN/A}; 1232292SN/A 1242348SN/A/** Struct that defines the information passed from decode to rename. */ 1252292SN/Atemplate<class Impl> 1262292SN/Astruct DefaultDecodeDefaultRename { 1271061SN/A typedef typename Impl::DynInstPtr DynInstPtr; 1281061SN/A 1291061SN/A int size; 1301061SN/A 1311461SN/A DynInstPtr insts[Impl::MaxWidth]; 1321060SN/A}; 1331060SN/A 1342348SN/A/** Struct that defines the information passed from rename to IEW. */ 1351060SN/Atemplate<class Impl> 1362292SN/Astruct DefaultRenameDefaultIEW { 1371061SN/A typedef typename Impl::DynInstPtr DynInstPtr; 1381061SN/A 1391061SN/A int size; 1401061SN/A 1411461SN/A DynInstPtr insts[Impl::MaxWidth]; 1421060SN/A}; 1431060SN/A 1442348SN/A/** Struct that defines the information passed from IEW to commit. */ 1451060SN/Atemplate<class Impl> 1462292SN/Astruct DefaultIEWDefaultCommit { 1471061SN/A typedef typename Impl::DynInstPtr DynInstPtr; 1481061SN/A 1491061SN/A int size; 1501061SN/A 1511461SN/A DynInstPtr insts[Impl::MaxWidth]; 1529046SAli.Saidi@ARM.com DynInstPtr mispredictInst[Impl::MaxThreads]; 1539046SAli.Saidi@ARM.com Addr mispredPC[Impl::MaxThreads]; 1549046SAli.Saidi@ARM.com InstSeqNum squashedSeqNum[Impl::MaxThreads]; 1559046SAli.Saidi@ARM.com TheISA::PCState pc[Impl::MaxThreads]; 1561062SN/A 1572292SN/A bool squash[Impl::MaxThreads]; 1582292SN/A bool branchMispredict[Impl::MaxThreads]; 1592292SN/A bool branchTaken[Impl::MaxThreads]; 1602292SN/A bool includeSquashInst[Impl::MaxThreads]; 1611060SN/A}; 1621060SN/A 1631060SN/Atemplate<class Impl> 1641060SN/Astruct IssueStruct { 1651061SN/A typedef typename Impl::DynInstPtr DynInstPtr; 1661061SN/A 1671061SN/A int size; 1681061SN/A 1691461SN/A DynInstPtr insts[Impl::MaxWidth]; 1701060SN/A}; 1711060SN/A 1722348SN/A/** Struct that defines all backwards communication. */ 1732292SN/Atemplate<class Impl> 1741060SN/Astruct TimeBufStruct { 1757851SMatt.Horsnell@arm.com typedef typename Impl::DynInstPtr DynInstPtr; 1761060SN/A struct decodeComm { 1779260SAli.Saidi@ARM.com TheISA::PCState nextPC; 1789046SAli.Saidi@ARM.com DynInstPtr mispredictInst; 1799046SAli.Saidi@ARM.com DynInstPtr squashInst; 1809260SAli.Saidi@ARM.com InstSeqNum doneSeqNum; 1819046SAli.Saidi@ARM.com Addr mispredPC; 1829260SAli.Saidi@ARM.com uint64_t branchAddr; 1839046SAli.Saidi@ARM.com unsigned branchCount; 1841060SN/A bool squash; 1851060SN/A bool predIncorrect; 1861061SN/A bool branchMispredict; 1871061SN/A bool branchTaken; 1881060SN/A }; 1891060SN/A 1902292SN/A decodeComm decodeInfo[Impl::MaxThreads]; 1911060SN/A 1921060SN/A struct renameComm { 1931060SN/A }; 1941060SN/A 1952292SN/A renameComm renameInfo[Impl::MaxThreads]; 1961060SN/A 1971060SN/A struct iewComm { 1982292SN/A // Also eventually include skid buffer space. 1992292SN/A unsigned freeIQEntries; 20010239Sbinhpham@cs.rutgers.edu unsigned freeLQEntries; 20110239Sbinhpham@cs.rutgers.edu unsigned freeSQEntries; 20210239Sbinhpham@cs.rutgers.edu unsigned dispatchedToLQ; 20310239Sbinhpham@cs.rutgers.edu unsigned dispatchedToSQ; 2041060SN/A 2052292SN/A unsigned iqCount; 2062292SN/A unsigned ldstqCount; 2072292SN/A 2082292SN/A unsigned dispatched; 2099260SAli.Saidi@ARM.com bool usedIQ; 2109260SAli.Saidi@ARM.com bool usedLSQ; 2111060SN/A }; 2121060SN/A 2132292SN/A iewComm iewInfo[Impl::MaxThreads]; 2141060SN/A 2151060SN/A struct commitComm { 2169260SAli.Saidi@ARM.com ///////////////////////////////////////////////////////////////////// 2179260SAli.Saidi@ARM.com // This code has been re-structured for better packing of variables 2189260SAli.Saidi@ARM.com // instead of by stage which is the more logical way to arrange the 2199260SAli.Saidi@ARM.com // data. 2209260SAli.Saidi@ARM.com // F = Fetch 2219260SAli.Saidi@ARM.com // D = Decode 2229260SAli.Saidi@ARM.com // I = IEW 2239260SAli.Saidi@ARM.com // R = Rename 2249260SAli.Saidi@ARM.com // As such each member is annotated with who consumes it 2259260SAli.Saidi@ARM.com // e.g. bool variable name // *F,R for Fetch and Rename 2269260SAli.Saidi@ARM.com ///////////////////////////////////////////////////////////////////// 2272292SN/A 2289260SAli.Saidi@ARM.com /// The pc of the next instruction to execute. This is the next 2299260SAli.Saidi@ARM.com /// instruction for a branch mispredict, but the same instruction for 2309260SAli.Saidi@ARM.com /// order violation and the like 2319260SAli.Saidi@ARM.com TheISA::PCState pc; // *F 2321060SN/A 2339260SAli.Saidi@ARM.com /// Provide fetch the instruction that mispredicted, if this 2349260SAli.Saidi@ARM.com /// pointer is not-null a misprediction occured 2359260SAli.Saidi@ARM.com DynInstPtr mispredictInst; // *F 2361061SN/A 2379260SAli.Saidi@ARM.com /// Instruction that caused the a non-mispredict squash 2389260SAli.Saidi@ARM.com DynInstPtr squashInst; // *F 2391061SN/A 24010824SAndreas.Sandberg@ARM.com /// Hack for now to send back a strictly ordered access to the 24110824SAndreas.Sandberg@ARM.com /// IEW stage. 24210824SAndreas.Sandberg@ARM.com DynInstPtr strictlyOrderedLoad; // *I 2438137SAli.Saidi@ARM.com 2449260SAli.Saidi@ARM.com /// Communication specifically to the IQ to tell the IQ that it can 2459260SAli.Saidi@ARM.com /// schedule a non-speculative instruction. 2469260SAli.Saidi@ARM.com InstSeqNum nonSpecSeqNum; // *I 2478137SAli.Saidi@ARM.com 2489260SAli.Saidi@ARM.com /// Represents the instruction that has either been retired or 2499260SAli.Saidi@ARM.com /// squashed. Similar to having a single bus that broadcasts the 2509260SAli.Saidi@ARM.com /// retired or squashed sequence number. 2519260SAli.Saidi@ARM.com InstSeqNum doneSeqNum; // *F, I 2528137SAli.Saidi@ARM.com 2539260SAli.Saidi@ARM.com /// Tell Rename how many free entries it has in the ROB 2549260SAli.Saidi@ARM.com unsigned freeROBEntries; // *R 2552292SN/A 2569260SAli.Saidi@ARM.com bool squash; // *F, D, R, I 2579260SAli.Saidi@ARM.com bool robSquashing; // *F, D, R, I 2589260SAli.Saidi@ARM.com 2599260SAli.Saidi@ARM.com /// Rename should re-read number of free rob entries 2609260SAli.Saidi@ARM.com bool usedROB; // *R 2619260SAli.Saidi@ARM.com 2629260SAli.Saidi@ARM.com /// Notify Rename that the ROB is empty 2639260SAli.Saidi@ARM.com bool emptyROB; // *R 2649260SAli.Saidi@ARM.com 2659260SAli.Saidi@ARM.com /// Was the branch taken or not 2669260SAli.Saidi@ARM.com bool branchTaken; // *F 2679260SAli.Saidi@ARM.com /// If an interrupt is pending and fetch should stall 2689260SAli.Saidi@ARM.com bool interruptPending; // *F 2699260SAli.Saidi@ARM.com /// If the interrupt ended up being cleared before being handled 2709260SAli.Saidi@ARM.com bool clearInterrupt; // *F 2719260SAli.Saidi@ARM.com 27210824SAndreas.Sandberg@ARM.com /// Hack for now to send back an strictly ordered access to 27310824SAndreas.Sandberg@ARM.com /// the IEW stage. 27410824SAndreas.Sandberg@ARM.com bool strictlyOrdered; // *I 2752292SN/A 2761060SN/A }; 2771060SN/A 2782292SN/A commitComm commitInfo[Impl::MaxThreads]; 2792292SN/A 2802292SN/A bool decodeBlock[Impl::MaxThreads]; 2812292SN/A bool decodeUnblock[Impl::MaxThreads]; 2822292SN/A bool renameBlock[Impl::MaxThreads]; 2832292SN/A bool renameUnblock[Impl::MaxThreads]; 2842292SN/A bool iewBlock[Impl::MaxThreads]; 2852292SN/A bool iewUnblock[Impl::MaxThreads]; 2861060SN/A}; 2871060SN/A 2882292SN/A#endif //__CPU_O3_COMM_HH__ 289