comm.hh revision 1061 
1#ifndef __COMM_HH__
2#define __COMM_HH__
3
4#include <stdint.h>
5#include <vector>
6#include "arch/alpha/isa_traits.hh"
7#include "cpu/inst_seq.hh"
8
9using namespace std;
10
11// Find better place to put this typedef.
12typedef short int PhysRegIndex;
13
14template<class Impl>
15struct SimpleFetchSimpleDecode {
16    typedef typename Impl::DynInstPtr DynInstPtr;
17
18    int size;
19
20    DynInstPtr insts[Impl::MaxWidth + 1];
21};
22
23template<class Impl>
24struct SimpleDecodeSimpleRename {
25    typedef typename Impl::DynInstPtr DynInstPtr;
26
27    int size;
28
29    DynInstPtr insts[Impl::MaxWidth + 1];
30};
31
32template<class Impl>
33struct SimpleRenameSimpleIEW {
34    typedef typename Impl::DynInstPtr DynInstPtr;
35
36    int size;
37
38    DynInstPtr insts[Impl::MaxWidth + 1];
39};
40
41template<class Impl>
42struct SimpleIEWSimpleCommit {
43    typedef typename Impl::DynInstPtr DynInstPtr;
44
45    int size;
46
47    DynInstPtr insts[Impl::MaxWidth + 1];
48};
49
50template<class Impl>
51struct IssueStruct {
52    typedef typename Impl::DynInstPtr DynInstPtr;
53
54    int size;
55
56    DynInstPtr insts[Impl::MaxWidth + 1];
57};
58
59struct TimeBufStruct {
60    struct decodeComm {
61        bool squash;
62        bool stall;
63        bool predIncorrect;
64        uint64_t branchAddr;
65
66        bool branchMispredict;
67        bool branchTaken;
68        uint64_t mispredPC;
69        uint64_t nextPC;
70    };
71
72    decodeComm decodeInfo;
73
74    // Rename can't actually tell anything to squash or send a new PC back
75    // because it doesn't do anything along those lines.  But maybe leave
76    // these fields in here to keep the stages mostly orthagonal.
77    struct renameComm {
78        bool squash;
79        bool stall;
80
81        uint64_t nextPC;
82    };
83
84    renameComm renameInfo;
85
86    struct iewComm {
87        bool squash;
88        bool stall;
89
90        // Also eventually include skid buffer space.
91        unsigned freeIQEntries;
92
93        bool branchMispredict;
94        bool branchTaken;
95        uint64_t mispredPC;
96        uint64_t nextPC;
97        InstSeqNum squashedSeqNum;
98    };
99
100    iewComm iewInfo;
101
102    struct commitComm {
103        bool squash;
104        bool stall;
105        unsigned freeROBEntries;
106
107        bool branchMispredict;
108        bool branchTaken;
109        uint64_t mispredPC;
110        uint64_t nextPC;
111
112        // Think of better names here.
113        // Will need to be a variety of sizes...
114        // Maybe make it a vector, that way only need one object.
115        std::vector<PhysRegIndex> freeRegs;
116
117        bool robSquashing;
118
119        // Represents the instruction that has either been retired or
120        // squashed.  Similar to having a single bus that broadcasts the
121        // retired or squashed sequence number.
122        InstSeqNum doneSeqNum;
123
124        // Extra bits of information so that the LDSTQ only updates when it
125        // needs to.
126        bool commitIsStore;
127        bool commitIsLoad;
128
129        // Communication specifically to the IQ to tell the IQ that it can
130        // schedule a non-speculative instruction.
131        InstSeqNum nonSpecSeqNum;
132    };
133
134    commitComm commitInfo;
135};
136
137#endif //__COMM_HH__
138