comm.hh revision 1060 
1#ifndef __COMM_HH__
2#define __COMM_HH__
3
4#include <stdint.h>
5#include "arch/alpha/isa_traits.hh"
6#include "cpu/inst_seq.hh"
7
8using namespace std;
9
10// Find better place to put this typedef.
11typedef short int PhysRegIndex;
12
13// Might want to put constructors/destructors here.
14template<class Impl>
15struct SimpleFetchSimpleDecode {
16    // Consider having a field of how many ready instructions.
17    typename Impl::DynInst *insts[1];
18};
19
20template<class Impl>
21struct SimpleDecodeSimpleRename {
22    // Consider having a field of how many ready instructions.
23    typename Impl::DynInst *insts[1];
24};
25
26template<class Impl>
27struct SimpleRenameSimpleIEW {
28    // Consider having a field of how many ready instructions.
29    typename Impl::DynInst *insts[1];
30};
31
32template<class Impl>
33struct SimpleIEWSimpleCommit {
34    // Consider having a field of how many ready instructions.
35    typename Impl::DynInst *insts[1];
36};
37
38template<class Impl>
39struct IssueStruct {
40    typename Impl::DynInst *insts[1];
41};
42
43struct TimeBufStruct {
44    struct decodeComm {
45        bool squash;
46        bool stall;
47        bool predIncorrect;
48        uint64_t branchAddr;
49
50        //Question, is it worthwhile to have this Addr passed along
51        //by each stage, or just have Fetch look it up in the proper
52        //amount of cycles in the time buffer?
53        //Both might actually be needed because decode can send a different
54        //nextPC if the bpred was wrong.
55        uint64_t nextPC;
56    };
57
58    decodeComm decodeInfo;
59
60    // Rename can't actually tell anything to squash or send a new PC back
61    // because it doesn't do anything along those lines.  But maybe leave
62    // these fields in here to keep the stages mostly orthagonal.
63    struct renameComm {
64        bool squash;
65        bool stall;
66
67        uint64_t nextPC;
68    };
69
70    renameComm renameInfo;
71
72    struct iewComm {
73        bool squash;
74        bool stall;
75        bool predIncorrect;
76
77        // Also eventually include skid buffer space.
78        unsigned freeIQEntries;
79
80        uint64_t nextPC;
81        // For now hardcode the type.
82        // Change this to sequence number eventually.
83        InstSeqNum squashedSeqNum;
84    };
85
86    iewComm iewInfo;
87
88    struct commitComm {
89        bool squash;
90        bool stall;
91        unsigned freeROBEntries;
92
93        uint64_t nextPC;
94
95        // Think of better names here.
96        // Will need to be a variety of sizes...
97        // Maybe make it a vector, that way only need one object.
98        vector<PhysRegIndex> freeRegs;
99
100        bool robSquashing;
101        // Represents the instruction that has either been retired or
102        // squashed.  Similar to having a single bus that broadcasts the
103        // retired or squashed sequence number.
104        InstSeqNum doneSeqNum;
105    };
106
107    commitComm commitInfo;
108};
109
110#endif //__COMM_HH__
111