comm.hh revision 10239
11689SN/A/* 28137SAli.Saidi@ARM.com * Copyright (c) 2011 ARM Limited 310239Sbinhpham@cs.rutgers.edu * Copyright (c) 2013 Advanced Micro Devices, Inc. 48137SAli.Saidi@ARM.com * All rights reserved 58137SAli.Saidi@ARM.com * 68137SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 78137SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 88137SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 98137SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 108137SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 118137SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 128137SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 138137SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 148137SAli.Saidi@ARM.com * 152329SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 161689SN/A * All rights reserved. 171689SN/A * 181689SN/A * Redistribution and use in source and binary forms, with or without 191689SN/A * modification, are permitted provided that the following conditions are 201689SN/A * met: redistributions of source code must retain the above copyright 211689SN/A * notice, this list of conditions and the following disclaimer; 221689SN/A * redistributions in binary form must reproduce the above copyright 231689SN/A * notice, this list of conditions and the following disclaimer in the 241689SN/A * documentation and/or other materials provided with the distribution; 251689SN/A * neither the name of the copyright holders nor the names of its 261689SN/A * contributors may be used to endorse or promote products derived from 271689SN/A * this software without specific prior written permission. 281689SN/A * 291689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 301689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 311689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 321689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 331689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 341689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 351689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 361689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 371689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 381689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 391689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665Ssaidi@eecs.umich.edu * 412665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 421689SN/A */ 431689SN/A 442292SN/A#ifndef __CPU_O3_COMM_HH__ 452292SN/A#define __CPU_O3_COMM_HH__ 461060SN/A 471061SN/A#include <vector> 481684SN/A 497720Sgblack@eecs.umich.edu#include "arch/types.hh" 506216Snate@binkert.org#include "base/types.hh" 516216Snate@binkert.org#include "cpu/inst_seq.hh" 522980Sgblack@eecs.umich.edu#include "sim/faults.hh" 531060SN/A 542292SN/A// Typedef for physical register index type. Although the Impl would be the 552292SN/A// most likely location for this, there are a few classes that need this 562292SN/A// typedef yet are not templated on the Impl. For now it will be defined here. 571060SN/Atypedef short int PhysRegIndex; 581060SN/A 592348SN/A/** Struct that defines the information passed from fetch to decode. */ 601060SN/Atemplate<class Impl> 612292SN/Astruct DefaultFetchDefaultDecode { 622292SN/A typedef typename Impl::DynInstPtr DynInstPtr; 632292SN/A 642292SN/A int size; 652292SN/A 662292SN/A DynInstPtr insts[Impl::MaxWidth]; 672292SN/A Fault fetchFault; 682292SN/A InstSeqNum fetchFaultSN; 692292SN/A bool clearFetchFault; 702292SN/A}; 712292SN/A 722348SN/A/** Struct that defines the information passed from decode to rename. */ 732292SN/Atemplate<class Impl> 742292SN/Astruct DefaultDecodeDefaultRename { 751061SN/A typedef typename Impl::DynInstPtr DynInstPtr; 761061SN/A 771061SN/A int size; 781061SN/A 791461SN/A DynInstPtr insts[Impl::MaxWidth]; 801060SN/A}; 811060SN/A 822348SN/A/** Struct that defines the information passed from rename to IEW. */ 831060SN/Atemplate<class Impl> 842292SN/Astruct DefaultRenameDefaultIEW { 851061SN/A typedef typename Impl::DynInstPtr DynInstPtr; 861061SN/A 871061SN/A int size; 881061SN/A 891461SN/A DynInstPtr insts[Impl::MaxWidth]; 901060SN/A}; 911060SN/A 922348SN/A/** Struct that defines the information passed from IEW to commit. */ 931060SN/Atemplate<class Impl> 942292SN/Astruct DefaultIEWDefaultCommit { 951061SN/A typedef typename Impl::DynInstPtr DynInstPtr; 961061SN/A 971061SN/A int size; 981061SN/A 991461SN/A DynInstPtr insts[Impl::MaxWidth]; 1009046SAli.Saidi@ARM.com DynInstPtr mispredictInst[Impl::MaxThreads]; 1019046SAli.Saidi@ARM.com Addr mispredPC[Impl::MaxThreads]; 1029046SAli.Saidi@ARM.com InstSeqNum squashedSeqNum[Impl::MaxThreads]; 1039046SAli.Saidi@ARM.com TheISA::PCState pc[Impl::MaxThreads]; 1041062SN/A 1052292SN/A bool squash[Impl::MaxThreads]; 1062292SN/A bool branchMispredict[Impl::MaxThreads]; 1072292SN/A bool branchTaken[Impl::MaxThreads]; 1082292SN/A bool includeSquashInst[Impl::MaxThreads]; 1091060SN/A}; 1101060SN/A 1111060SN/Atemplate<class Impl> 1121060SN/Astruct IssueStruct { 1131061SN/A typedef typename Impl::DynInstPtr DynInstPtr; 1141061SN/A 1151061SN/A int size; 1161061SN/A 1171461SN/A DynInstPtr insts[Impl::MaxWidth]; 1181060SN/A}; 1191060SN/A 1202348SN/A/** Struct that defines all backwards communication. */ 1212292SN/Atemplate<class Impl> 1221060SN/Astruct TimeBufStruct { 1237851SMatt.Horsnell@arm.com typedef typename Impl::DynInstPtr DynInstPtr; 1241060SN/A struct decodeComm { 1259260SAli.Saidi@ARM.com TheISA::PCState nextPC; 1269046SAli.Saidi@ARM.com DynInstPtr mispredictInst; 1279046SAli.Saidi@ARM.com DynInstPtr squashInst; 1289260SAli.Saidi@ARM.com InstSeqNum doneSeqNum; 1299046SAli.Saidi@ARM.com Addr mispredPC; 1309260SAli.Saidi@ARM.com uint64_t branchAddr; 1319046SAli.Saidi@ARM.com unsigned branchCount; 1321060SN/A bool squash; 1331060SN/A bool predIncorrect; 1341061SN/A bool branchMispredict; 1351061SN/A bool branchTaken; 1361060SN/A }; 1371060SN/A 1382292SN/A decodeComm decodeInfo[Impl::MaxThreads]; 1391060SN/A 1401060SN/A struct renameComm { 1411060SN/A }; 1421060SN/A 1432292SN/A renameComm renameInfo[Impl::MaxThreads]; 1441060SN/A 1451060SN/A struct iewComm { 1462292SN/A // Also eventually include skid buffer space. 1472292SN/A unsigned freeIQEntries; 14810239Sbinhpham@cs.rutgers.edu unsigned freeLQEntries; 14910239Sbinhpham@cs.rutgers.edu unsigned freeSQEntries; 15010239Sbinhpham@cs.rutgers.edu unsigned dispatchedToLQ; 15110239Sbinhpham@cs.rutgers.edu unsigned dispatchedToSQ; 1521060SN/A 1532292SN/A unsigned iqCount; 1542292SN/A unsigned ldstqCount; 1552292SN/A 1562292SN/A unsigned dispatched; 1579260SAli.Saidi@ARM.com bool usedIQ; 1589260SAli.Saidi@ARM.com bool usedLSQ; 1591060SN/A }; 1601060SN/A 1612292SN/A iewComm iewInfo[Impl::MaxThreads]; 1621060SN/A 1631060SN/A struct commitComm { 1649260SAli.Saidi@ARM.com ///////////////////////////////////////////////////////////////////// 1659260SAli.Saidi@ARM.com // This code has been re-structured for better packing of variables 1669260SAli.Saidi@ARM.com // instead of by stage which is the more logical way to arrange the 1679260SAli.Saidi@ARM.com // data. 1689260SAli.Saidi@ARM.com // F = Fetch 1699260SAli.Saidi@ARM.com // D = Decode 1709260SAli.Saidi@ARM.com // I = IEW 1719260SAli.Saidi@ARM.com // R = Rename 1729260SAli.Saidi@ARM.com // As such each member is annotated with who consumes it 1739260SAli.Saidi@ARM.com // e.g. bool variable name // *F,R for Fetch and Rename 1749260SAli.Saidi@ARM.com ///////////////////////////////////////////////////////////////////// 1752292SN/A 1769260SAli.Saidi@ARM.com /// The pc of the next instruction to execute. This is the next 1779260SAli.Saidi@ARM.com /// instruction for a branch mispredict, but the same instruction for 1789260SAli.Saidi@ARM.com /// order violation and the like 1799260SAli.Saidi@ARM.com TheISA::PCState pc; // *F 1801060SN/A 1819260SAli.Saidi@ARM.com /// Provide fetch the instruction that mispredicted, if this 1829260SAli.Saidi@ARM.com /// pointer is not-null a misprediction occured 1839260SAli.Saidi@ARM.com DynInstPtr mispredictInst; // *F 1841061SN/A 1859260SAli.Saidi@ARM.com /// Instruction that caused the a non-mispredict squash 1869260SAli.Saidi@ARM.com DynInstPtr squashInst; // *F 1871061SN/A 1889260SAli.Saidi@ARM.com /// Hack for now to send back an uncached access to the IEW stage. 1899260SAli.Saidi@ARM.com DynInstPtr uncachedLoad; // *I 1908137SAli.Saidi@ARM.com 1919260SAli.Saidi@ARM.com /// Communication specifically to the IQ to tell the IQ that it can 1929260SAli.Saidi@ARM.com /// schedule a non-speculative instruction. 1939260SAli.Saidi@ARM.com InstSeqNum nonSpecSeqNum; // *I 1948137SAli.Saidi@ARM.com 1959260SAli.Saidi@ARM.com /// Represents the instruction that has either been retired or 1969260SAli.Saidi@ARM.com /// squashed. Similar to having a single bus that broadcasts the 1979260SAli.Saidi@ARM.com /// retired or squashed sequence number. 1989260SAli.Saidi@ARM.com InstSeqNum doneSeqNum; // *F, I 1998137SAli.Saidi@ARM.com 2009260SAli.Saidi@ARM.com /// Tell Rename how many free entries it has in the ROB 2019260SAli.Saidi@ARM.com unsigned freeROBEntries; // *R 2022292SN/A 2039260SAli.Saidi@ARM.com bool squash; // *F, D, R, I 2049260SAli.Saidi@ARM.com bool robSquashing; // *F, D, R, I 2059260SAli.Saidi@ARM.com 2069260SAli.Saidi@ARM.com /// Rename should re-read number of free rob entries 2079260SAli.Saidi@ARM.com bool usedROB; // *R 2089260SAli.Saidi@ARM.com 2099260SAli.Saidi@ARM.com /// Notify Rename that the ROB is empty 2109260SAli.Saidi@ARM.com bool emptyROB; // *R 2119260SAli.Saidi@ARM.com 2129260SAli.Saidi@ARM.com /// Was the branch taken or not 2139260SAli.Saidi@ARM.com bool branchTaken; // *F 2149260SAli.Saidi@ARM.com /// If an interrupt is pending and fetch should stall 2159260SAli.Saidi@ARM.com bool interruptPending; // *F 2169260SAli.Saidi@ARM.com /// If the interrupt ended up being cleared before being handled 2179260SAli.Saidi@ARM.com bool clearInterrupt; // *F 2189260SAli.Saidi@ARM.com 2199260SAli.Saidi@ARM.com /// Hack for now to send back an uncached access to the IEW stage. 2209260SAli.Saidi@ARM.com bool uncached; // *I 2212292SN/A 2221060SN/A }; 2231060SN/A 2242292SN/A commitComm commitInfo[Impl::MaxThreads]; 2252292SN/A 2262292SN/A bool decodeBlock[Impl::MaxThreads]; 2272292SN/A bool decodeUnblock[Impl::MaxThreads]; 2282292SN/A bool renameBlock[Impl::MaxThreads]; 2292292SN/A bool renameUnblock[Impl::MaxThreads]; 2302292SN/A bool iewBlock[Impl::MaxThreads]; 2312292SN/A bool iewUnblock[Impl::MaxThreads]; 2322292SN/A bool commitBlock[Impl::MaxThreads]; 2332292SN/A bool commitUnblock[Impl::MaxThreads]; 2341060SN/A}; 2351060SN/A 2362292SN/A#endif //__CPU_O3_COMM_HH__ 237