O3CPU.py revision 9132
14486Sbinkertn@umich.edu# Copyright (c) 2005-2007 The Regents of The University of Michigan 24486Sbinkertn@umich.edu# All rights reserved. 34486Sbinkertn@umich.edu# 44486Sbinkertn@umich.edu# Redistribution and use in source and binary forms, with or without 54486Sbinkertn@umich.edu# modification, are permitted provided that the following conditions are 64486Sbinkertn@umich.edu# met: redistributions of source code must retain the above copyright 74486Sbinkertn@umich.edu# notice, this list of conditions and the following disclaimer; 84486Sbinkertn@umich.edu# redistributions in binary form must reproduce the above copyright 94486Sbinkertn@umich.edu# notice, this list of conditions and the following disclaimer in the 104486Sbinkertn@umich.edu# documentation and/or other materials provided with the distribution; 114486Sbinkertn@umich.edu# neither the name of the copyright holders nor the names of its 124486Sbinkertn@umich.edu# contributors may be used to endorse or promote products derived from 134486Sbinkertn@umich.edu# this software without specific prior written permission. 144486Sbinkertn@umich.edu# 154486Sbinkertn@umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 164486Sbinkertn@umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 174486Sbinkertn@umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 184486Sbinkertn@umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 194486Sbinkertn@umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 204486Sbinkertn@umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 214486Sbinkertn@umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 224486Sbinkertn@umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 234486Sbinkertn@umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 244486Sbinkertn@umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 254486Sbinkertn@umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 264486Sbinkertn@umich.edu# 274486Sbinkertn@umich.edu# Authors: Kevin Lim 284486Sbinkertn@umich.edu 296654Snate@binkert.orgfrom m5.defines import buildEnv 303102SN/Afrom m5.params import * 313102SN/Afrom m5.proxy import * 321681SN/Afrom BaseCPU import BaseCPU 333223SN/Afrom FUPool import * 341681SN/Afrom O3Checker import O3Checker 356654Snate@binkert.org 364486Sbinkertn@umich.educlass DerivO3CPU(BaseCPU): 374486Sbinkertn@umich.edu type = 'DerivO3CPU' 382817SN/A activity = Param.Unsigned(0, "Initial count") 392817SN/A 402932SN/A cachePorts = Param.Unsigned(200, "Cache Ports") 411681SN/A 426654Snate@binkert.org decodeToFetchDelay = Param.Unsigned(1, "Decode to fetch delay") 436654Snate@binkert.org renameToFetchDelay = Param.Unsigned(1 ,"Rename to fetch delay") 442932SN/A iewToFetchDelay = Param.Unsigned(1, "Issue/Execute/Writeback to fetch " 453223SN/A "delay") 463223SN/A commitToFetchDelay = Param.Unsigned(1, "Commit to fetch delay") 472932SN/A fetchWidth = Param.Unsigned(8, "Fetch width") 482932SN/A 492932SN/A renameToDecodeDelay = Param.Unsigned(1, "Rename to decode delay") 503223SN/A iewToDecodeDelay = Param.Unsigned(1, "Issue/Execute/Writeback to decode " 513223SN/A "delay") 524997Sgblack@eecs.umich.edu commitToDecodeDelay = Param.Unsigned(1, "Commit to decode delay") 534997Sgblack@eecs.umich.edu fetchToDecodeDelay = Param.Unsigned(1, "Fetch to decode delay") 542318SN/A decodeWidth = Param.Unsigned(8, "Decode width") 554597Sbinkertn@umich.edu 562871SN/A iewToRenameDelay = Param.Unsigned(1, "Issue/Execute/Writeback to rename " 572871SN/A "delay") 587876Sgblack@eecs.umich.edu commitToRenameDelay = Param.Unsigned(1, "Commit to rename delay") 591681SN/A decodeToRenameDelay = Param.Unsigned(1, "Decode to rename delay") 602932SN/A renameWidth = Param.Unsigned(8, "Rename width") 612932SN/A 622932SN/A commitToIEWDelay = Param.Unsigned(1, "Commit to " 632932SN/A "Issue/Execute/Writeback delay") 642932SN/A renameToIEWDelay = Param.Unsigned(2, "Rename to " 652932SN/A "Issue/Execute/Writeback delay") 662932SN/A issueToExecuteDelay = Param.Unsigned(1, "Issue to execute delay (internal " 672932SN/A "to the IEW stage)") 682932SN/A dispatchWidth = Param.Unsigned(8, "Dispatch width") 691681SN/A issueWidth = Param.Unsigned(8, "Issue width") 702932SN/A wbWidth = Param.Unsigned(8, "Writeback width") 712932SN/A wbDepth = Param.Unsigned(1, "Writeback depth") 722932SN/A fuPool = Param.FUPool(DefaultFUPool(), "Functional Unit pool") 731681SN/A 742932SN/A iewToCommitDelay = Param.Unsigned(1, "Issue/Execute/Writeback to commit " 751681SN/A "delay") 762932SN/A renameToROBDelay = Param.Unsigned(1, "Rename to reorder buffer delay") 772932SN/A commitWidth = Param.Unsigned(8, "Commit width") 782932SN/A squashWidth = Param.Unsigned(8, "Squash width") 791681SN/A trapLatency = Param.Tick(13, "Trap latency") 802932SN/A fetchTrapLatency = Param.Tick(1, "Fetch trap latency") 812932SN/A 822932SN/A backComSize = Param.Unsigned(5, "Time buffer size for backwards communication") 832932SN/A forwardComSize = Param.Unsigned(5, "Time buffer size for forward communication") 842932SN/A 852932SN/A predType = Param.String("tournament", "Branch predictor type ('local', 'tournament')") 862932SN/A localPredictorSize = Param.Unsigned(2048, "Size of local predictor") 872932SN/A localCtrBits = Param.Unsigned(2, "Bits per counter") 882932SN/A localHistoryTableSize = Param.Unsigned(2048, "Size of local history table") 892932SN/A localHistoryBits = Param.Unsigned(11, "Bits for the local history") 903223SN/A globalPredictorSize = Param.Unsigned(8192, "Size of global predictor") 912932SN/A globalCtrBits = Param.Unsigned(2, "Bits per counter") 922932SN/A globalHistoryBits = Param.Unsigned(13, "Bits of history") 931681SN/A choicePredictorSize = Param.Unsigned(8192, "Size of choice predictor") 942932SN/A choiceCtrBits = Param.Unsigned(2, "Bits of choice counters") 952932SN/A 962932SN/A BTBEntries = Param.Unsigned(4096, "Number of BTB entries") 972932SN/A BTBTagSize = Param.Unsigned(16, "Size of the BTB tags, in bits") 982932SN/A 991681SN/A RASSize = Param.Unsigned(16, "RAS size") 1002932SN/A 1012932SN/A LQEntries = Param.Unsigned(32, "Number of load queue entries") 1021681SN/A SQEntries = Param.Unsigned(32, "Number of store queue entries") 1032932SN/A LSQDepCheckShift = Param.Unsigned(4, "Number of places to shift addr before check") 1042932SN/A LSQCheckLoads = Param.Bool(True, 1052932SN/A "Should dependency violations be checked for loads & stores or just stores") 1062932SN/A store_set_clear_period = Param.Unsigned(250000, 1072932SN/A "Number of load/store insts before the dep predictor should be invalidated") 1082932SN/A LFSTSize = Param.Unsigned(1024, "Last fetched store table size") 1092932SN/A SSITSize = Param.Unsigned(1024, "Store set ID table size") 1103223SN/A 1112932SN/A numRobs = Param.Unsigned(1, "Number of Reorder Buffers"); 1122932SN/A 1131681SN/A numPhysIntRegs = Param.Unsigned(256, "Number of physical integer registers") 1142932SN/A numPhysFloatRegs = Param.Unsigned(256, "Number of physical floating point " 1152932SN/A "registers") 1162873SN/A numIQEntries = Param.Unsigned(64, "Number of instruction queue entries") 1172932SN/A numROBEntries = Param.Unsigned(192, "Number of reorder buffer entries") 1181681SN/A 1192932SN/A instShiftAmt = Param.Unsigned(2, "Number of bits to shift instructions by") 1202932SN/A 1218199SAli.Saidi@ARM.com smtNumFetchingThreads = Param.Unsigned(1, "SMT Number of Fetching Threads") 1228199SAli.Saidi@ARM.com smtFetchPolicy = Param.String('SingleThread', "SMT Fetch policy") 1238199SAli.Saidi@ARM.com smtLSQPolicy = Param.String('Partitioned', "SMT LSQ Sharing Policy") 1242932SN/A smtLSQThreshold = Param.Int(100, "SMT LSQ Threshold Sharing Parameter") 1252932SN/A smtIQPolicy = Param.String('Partitioned', "SMT IQ Sharing Policy") 1261681SN/A smtIQThreshold = Param.Int(100, "SMT IQ Threshold Sharing Parameter") 1272932SN/A smtROBPolicy = Param.String('Partitioned', "SMT ROB Sharing Policy") 1281681SN/A smtROBThreshold = Param.Int(100, "SMT ROB Threshold Sharing Parameter") 1292932SN/A smtCommitPolicy = Param.String('RoundRobin', "SMT Commit Policy") 1302932SN/A 1312932SN/A needsTSO = Param.Bool(buildEnv['TARGET_ISA'] == 'x86', 1322932SN/A "Enable TSO Memory model") 1332932SN/A 1341681SN/A def addCheckerCpu(self): 1352932SN/A if buildEnv['TARGET_ISA'] in ['arm']: 1361681SN/A from ArmTLB import ArmTLB 1374597Sbinkertn@umich.edu 1384597Sbinkertn@umich.edu self.checker = O3Checker(workload=self.workload, 1394597Sbinkertn@umich.edu exitOnError=False, 1404597Sbinkertn@umich.edu updateOnError=True, 1414597Sbinkertn@umich.edu warnOnlyOnLoadError=True) 1424597Sbinkertn@umich.edu self.checker.itb = ArmTLB(size = self.itb.size) 1434597Sbinkertn@umich.edu self.checker.dtb = ArmTLB(size = self.dtb.size) 1444597Sbinkertn@umich.edu self.checker.cpu_id = self.cpu_id 1454597Sbinkertn@umich.edu 1464303SN/A else: 1477868Sgblack@eecs.umich.edu print "ERROR: Checker only supported under ARM ISA!" 1487868Sgblack@eecs.umich.edu exit(1) 1494303SN/A