O3CPU.py revision 9132
1# Copyright (c) 2005-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright 9# notice, this list of conditions and the following disclaimer in the 10# documentation and/or other materials provided with the distribution; 11# neither the name of the copyright holders nor the names of its 12# contributors may be used to endorse or promote products derived from 13# this software without specific prior written permission. 14# 15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 16# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 17# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 18# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 19# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 20# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 21# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26# 27# Authors: Kevin Lim 28 29from m5.defines import buildEnv 30from m5.params import * 31from m5.proxy import * 32from BaseCPU import BaseCPU 33from FUPool import * 34from O3Checker import O3Checker 35 36class DerivO3CPU(BaseCPU): 37 type = 'DerivO3CPU' 38 activity = Param.Unsigned(0, "Initial count") 39 40 cachePorts = Param.Unsigned(200, "Cache Ports") 41 42 decodeToFetchDelay = Param.Unsigned(1, "Decode to fetch delay") 43 renameToFetchDelay = Param.Unsigned(1 ,"Rename to fetch delay") 44 iewToFetchDelay = Param.Unsigned(1, "Issue/Execute/Writeback to fetch " 45 "delay") 46 commitToFetchDelay = Param.Unsigned(1, "Commit to fetch delay") 47 fetchWidth = Param.Unsigned(8, "Fetch width") 48 49 renameToDecodeDelay = Param.Unsigned(1, "Rename to decode delay") 50 iewToDecodeDelay = Param.Unsigned(1, "Issue/Execute/Writeback to decode " 51 "delay") 52 commitToDecodeDelay = Param.Unsigned(1, "Commit to decode delay") 53 fetchToDecodeDelay = Param.Unsigned(1, "Fetch to decode delay") 54 decodeWidth = Param.Unsigned(8, "Decode width") 55 56 iewToRenameDelay = Param.Unsigned(1, "Issue/Execute/Writeback to rename " 57 "delay") 58 commitToRenameDelay = Param.Unsigned(1, "Commit to rename delay") 59 decodeToRenameDelay = Param.Unsigned(1, "Decode to rename delay") 60 renameWidth = Param.Unsigned(8, "Rename width") 61 62 commitToIEWDelay = Param.Unsigned(1, "Commit to " 63 "Issue/Execute/Writeback delay") 64 renameToIEWDelay = Param.Unsigned(2, "Rename to " 65 "Issue/Execute/Writeback delay") 66 issueToExecuteDelay = Param.Unsigned(1, "Issue to execute delay (internal " 67 "to the IEW stage)") 68 dispatchWidth = Param.Unsigned(8, "Dispatch width") 69 issueWidth = Param.Unsigned(8, "Issue width") 70 wbWidth = Param.Unsigned(8, "Writeback width") 71 wbDepth = Param.Unsigned(1, "Writeback depth") 72 fuPool = Param.FUPool(DefaultFUPool(), "Functional Unit pool") 73 74 iewToCommitDelay = Param.Unsigned(1, "Issue/Execute/Writeback to commit " 75 "delay") 76 renameToROBDelay = Param.Unsigned(1, "Rename to reorder buffer delay") 77 commitWidth = Param.Unsigned(8, "Commit width") 78 squashWidth = Param.Unsigned(8, "Squash width") 79 trapLatency = Param.Tick(13, "Trap latency") 80 fetchTrapLatency = Param.Tick(1, "Fetch trap latency") 81 82 backComSize = Param.Unsigned(5, "Time buffer size for backwards communication") 83 forwardComSize = Param.Unsigned(5, "Time buffer size for forward communication") 84 85 predType = Param.String("tournament", "Branch predictor type ('local', 'tournament')") 86 localPredictorSize = Param.Unsigned(2048, "Size of local predictor") 87 localCtrBits = Param.Unsigned(2, "Bits per counter") 88 localHistoryTableSize = Param.Unsigned(2048, "Size of local history table") 89 localHistoryBits = Param.Unsigned(11, "Bits for the local history") 90 globalPredictorSize = Param.Unsigned(8192, "Size of global predictor") 91 globalCtrBits = Param.Unsigned(2, "Bits per counter") 92 globalHistoryBits = Param.Unsigned(13, "Bits of history") 93 choicePredictorSize = Param.Unsigned(8192, "Size of choice predictor") 94 choiceCtrBits = Param.Unsigned(2, "Bits of choice counters") 95 96 BTBEntries = Param.Unsigned(4096, "Number of BTB entries") 97 BTBTagSize = Param.Unsigned(16, "Size of the BTB tags, in bits") 98 99 RASSize = Param.Unsigned(16, "RAS size") 100 101 LQEntries = Param.Unsigned(32, "Number of load queue entries") 102 SQEntries = Param.Unsigned(32, "Number of store queue entries") 103 LSQDepCheckShift = Param.Unsigned(4, "Number of places to shift addr before check") 104 LSQCheckLoads = Param.Bool(True, 105 "Should dependency violations be checked for loads & stores or just stores") 106 store_set_clear_period = Param.Unsigned(250000, 107 "Number of load/store insts before the dep predictor should be invalidated") 108 LFSTSize = Param.Unsigned(1024, "Last fetched store table size") 109 SSITSize = Param.Unsigned(1024, "Store set ID table size") 110 111 numRobs = Param.Unsigned(1, "Number of Reorder Buffers"); 112 113 numPhysIntRegs = Param.Unsigned(256, "Number of physical integer registers") 114 numPhysFloatRegs = Param.Unsigned(256, "Number of physical floating point " 115 "registers") 116 numIQEntries = Param.Unsigned(64, "Number of instruction queue entries") 117 numROBEntries = Param.Unsigned(192, "Number of reorder buffer entries") 118 119 instShiftAmt = Param.Unsigned(2, "Number of bits to shift instructions by") 120 121 smtNumFetchingThreads = Param.Unsigned(1, "SMT Number of Fetching Threads") 122 smtFetchPolicy = Param.String('SingleThread', "SMT Fetch policy") 123 smtLSQPolicy = Param.String('Partitioned', "SMT LSQ Sharing Policy") 124 smtLSQThreshold = Param.Int(100, "SMT LSQ Threshold Sharing Parameter") 125 smtIQPolicy = Param.String('Partitioned', "SMT IQ Sharing Policy") 126 smtIQThreshold = Param.Int(100, "SMT IQ Threshold Sharing Parameter") 127 smtROBPolicy = Param.String('Partitioned', "SMT ROB Sharing Policy") 128 smtROBThreshold = Param.Int(100, "SMT ROB Threshold Sharing Parameter") 129 smtCommitPolicy = Param.String('RoundRobin', "SMT Commit Policy") 130 131 needsTSO = Param.Bool(buildEnv['TARGET_ISA'] == 'x86', 132 "Enable TSO Memory model") 133 134 def addCheckerCpu(self): 135 if buildEnv['TARGET_ISA'] in ['arm']: 136 from ArmTLB import ArmTLB 137 138 self.checker = O3Checker(workload=self.workload, 139 exitOnError=False, 140 updateOnError=True, 141 warnOnlyOnLoadError=True) 142 self.checker.itb = ArmTLB(size = self.itb.size) 143 self.checker.dtb = ArmTLB(size = self.dtb.size) 144 self.checker.cpu_id = self.cpu_id 145 146 else: 147 print "ERROR: Checker only supported under ARM ISA!" 148 exit(1) 149