1# -*- mode:python -*-
2
3# Copyright (c) 2013-2014 ARM Limited
4# All rights reserved
5#
6# The license below extends only to copyright in the software and shall
7# not be construed as granting a license to any other intellectual
8# property including but not limited to intellectual property relating
9# to a hardware implementation of the functionality of the software
10# licensed hereunder.  You may use the software subject to the license
11# terms below provided that you ensure that this notice is replicated
12# unmodified and in its entirety in all distributions of the software,
13# modified or unmodified, in source code or in binary form.
14#
15# Copyright (c) 2006 The Regents of The University of Michigan
16# All rights reserved.
17#
18# Redistribution and use in source and binary forms, with or without
19# modification, are permitted provided that the following conditions are
20# met: redistributions of source code must retain the above copyright
21# notice, this list of conditions and the following disclaimer;
22# redistributions in binary form must reproduce the above copyright
23# notice, this list of conditions and the following disclaimer in the
24# documentation and/or other materials provided with the distribution;
25# neither the name of the copyright holders nor the names of its
26# contributors may be used to endorse or promote products derived from
27# this software without specific prior written permission.
28#
29# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40#
41# Authors: Nathan Binkert
42#          Andrew Bardsley
43
44Import('*')
45
46if 'MinorCPU' in env['CPU_MODELS']:
47    SimObject('MinorCPU.py')
48
49    Source('activity.cc')
50    Source('cpu.cc')
51    Source('decode.cc')
52    Source('dyn_inst.cc')
53    Source('execute.cc')
54    Source('fetch1.cc')
55    Source('fetch2.cc')
56    Source('func_unit.cc')
57    Source('lsq.cc')
58    Source('pipe_data.cc')
59    Source('pipeline.cc')
60    Source('scoreboard.cc')
61    Source('stats.cc')
62
63    DebugFlag('MinorCPU', 'Minor CPU-level events')
64    DebugFlag('MinorExecute', 'Minor Execute stage')
65    DebugFlag('MinorInterrupt', 'Minor interrupt handling')
66    DebugFlag('MinorMem', 'Minor memory accesses')
67    DebugFlag('MinorScoreboard', 'Minor Execute register scoreboard')
68    DebugFlag('MinorTrace', 'MinorTrace cycle-by-cycle state trace')
69    DebugFlag('MinorTiming', 'Extra timing for instructions')
70
71    CompoundFlag('Minor', [
72        'MinorCPU', 'MinorExecute', 'MinorInterrupt', 'MinorMem',
73        'MinorScoreboard'])
74