MinorCPU.py revision 13759
13101Sstever@eecs.umich.edu# Copyright (c) 2012-2014, 2017-2018 ARM Limited 23101Sstever@eecs.umich.edu# All rights reserved. 33101Sstever@eecs.umich.edu# 43101Sstever@eecs.umich.edu# The license below extends only to copyright in the software and shall 53101Sstever@eecs.umich.edu# not be construed as granting a license to any other intellectual 63101Sstever@eecs.umich.edu# property including but not limited to intellectual property relating 73101Sstever@eecs.umich.edu# to a hardware implementation of the functionality of the software 83101Sstever@eecs.umich.edu# licensed hereunder. You may use the software subject to the license 93101Sstever@eecs.umich.edu# terms below provided that you ensure that this notice is replicated 103101Sstever@eecs.umich.edu# unmodified and in its entirety in all distributions of the software, 113101Sstever@eecs.umich.edu# modified or unmodified, in source code or in binary form. 123101Sstever@eecs.umich.edu# 133101Sstever@eecs.umich.edu# Copyright (c) 2007 The Regents of The University of Michigan 143101Sstever@eecs.umich.edu# All rights reserved. 153101Sstever@eecs.umich.edu# 163101Sstever@eecs.umich.edu# Redistribution and use in source and binary forms, with or without 173101Sstever@eecs.umich.edu# modification, are permitted provided that the following conditions are 183101Sstever@eecs.umich.edu# met: redistributions of source code must retain the above copyright 193101Sstever@eecs.umich.edu# notice, this list of conditions and the following disclaimer; 203101Sstever@eecs.umich.edu# redistributions in binary form must reproduce the above copyright 213101Sstever@eecs.umich.edu# notice, this list of conditions and the following disclaimer in the 223101Sstever@eecs.umich.edu# documentation and/or other materials provided with the distribution; 233101Sstever@eecs.umich.edu# neither the name of the copyright holders nor the names of its 243101Sstever@eecs.umich.edu# contributors may be used to endorse or promote products derived from 253101Sstever@eecs.umich.edu# this software without specific prior written permission. 263101Sstever@eecs.umich.edu# 273101Sstever@eecs.umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 283101Sstever@eecs.umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 293101Sstever@eecs.umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 303101Sstever@eecs.umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 313101Sstever@eecs.umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 323101Sstever@eecs.umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 333101Sstever@eecs.umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 343101Sstever@eecs.umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 353101Sstever@eecs.umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 363101Sstever@eecs.umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 373101Sstever@eecs.umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 383101Sstever@eecs.umich.edu# 393101Sstever@eecs.umich.edu# Authors: Gabe Black 403101Sstever@eecs.umich.edu# Nathan Binkert 413101Sstever@eecs.umich.edu# Andrew Bardsley 423101Sstever@eecs.umich.edu 433101Sstever@eecs.umich.edufrom __future__ import print_function 443101Sstever@eecs.umich.edu 453101Sstever@eecs.umich.edufrom m5.defines import buildEnv 463101Sstever@eecs.umich.edufrom m5.params import * 473885Sbinkertn@umich.edufrom m5.proxy import * 483885Sbinkertn@umich.edufrom m5.SimObject import SimObject 493885Sbinkertn@umich.edufrom m5.objects.BaseCPU import BaseCPU 503885Sbinkertn@umich.edufrom m5.objects.DummyChecker import DummyChecker 513885Sbinkertn@umich.edufrom m5.objects.BranchPredictor import * 523885Sbinkertn@umich.edufrom m5.objects.TimingExpr import TimingExpr 533101Sstever@eecs.umich.edu 544167Sbinkertn@umich.edufrom m5.objects.FuncUnit import OpClass 553102Sstever@eecs.umich.edu 563101Sstever@eecs.umich.educlass MinorOpClass(SimObject): 573101Sstever@eecs.umich.edu """Boxing of OpClass to get around build problems and provide a hook for 583101Sstever@eecs.umich.edu future additions to OpClass checks""" 593101Sstever@eecs.umich.edu 603101Sstever@eecs.umich.edu type = 'MinorOpClass' 613101Sstever@eecs.umich.edu cxx_header = "cpu/minor/func_unit.hh" 623101Sstever@eecs.umich.edu 633101Sstever@eecs.umich.edu opClass = Param.OpClass("op class to match") 643101Sstever@eecs.umich.edu 653101Sstever@eecs.umich.educlass MinorOpClassSet(SimObject): 663101Sstever@eecs.umich.edu """A set of matchable op classes""" 673101Sstever@eecs.umich.edu 683101Sstever@eecs.umich.edu type = 'MinorOpClassSet' 693101Sstever@eecs.umich.edu cxx_header = "cpu/minor/func_unit.hh" 703101Sstever@eecs.umich.edu 713101Sstever@eecs.umich.edu opClasses = VectorParam.MinorOpClass([], "op classes to be matched." 723101Sstever@eecs.umich.edu " An empty list means any class") 733101Sstever@eecs.umich.edu 743101Sstever@eecs.umich.educlass MinorFUTiming(SimObject): 753101Sstever@eecs.umich.edu type = 'MinorFUTiming' 763101Sstever@eecs.umich.edu cxx_header = "cpu/minor/func_unit.hh" 773101Sstever@eecs.umich.edu 783101Sstever@eecs.umich.edu mask = Param.UInt64(0, "mask for testing ExtMachInst") 793101Sstever@eecs.umich.edu match = Param.UInt64(0, "match value for testing ExtMachInst:" 803101Sstever@eecs.umich.edu " (ext_mach_inst & mask) == match") 813101Sstever@eecs.umich.edu suppress = Param.Bool(False, "if true, this inst. is not executed by" 823101Sstever@eecs.umich.edu " this FU") 833101Sstever@eecs.umich.edu extraCommitLat = Param.Cycles(0, "extra cycles to stall commit for" 843101Sstever@eecs.umich.edu " this inst.") 853101Sstever@eecs.umich.edu extraCommitLatExpr = Param.TimingExpr(NULL, "extra cycles as a" 863101Sstever@eecs.umich.edu " run-time evaluated expression") 873101Sstever@eecs.umich.edu extraAssumedLat = Param.Cycles(0, "extra cycles to add to scoreboard" 883101Sstever@eecs.umich.edu " retire time for this insts dest registers once it leaves the" 893101Sstever@eecs.umich.edu " functional unit. For mem refs, if this is 0, the result's time" 903101Sstever@eecs.umich.edu " is marked as unpredictable and no forwarding can take place.") 913101Sstever@eecs.umich.edu srcRegsRelativeLats = VectorParam.Cycles("the maximum number of cycles" 923101Sstever@eecs.umich.edu " after inst. issue that each src reg can be available for this" 933101Sstever@eecs.umich.edu " inst. to issue") 943101Sstever@eecs.umich.edu opClasses = Param.MinorOpClassSet(MinorOpClassSet(), 953101Sstever@eecs.umich.edu "op classes to be considered for this decode. An empty set means any" 963101Sstever@eecs.umich.edu " class") 973101Sstever@eecs.umich.edu description = Param.String('', "description string of the decoding/inst." 983101Sstever@eecs.umich.edu " class") 993101Sstever@eecs.umich.edu 1003101Sstever@eecs.umich.edudef minorMakeOpClassSet(op_classes): 1013101Sstever@eecs.umich.edu """Make a MinorOpClassSet from a list of OpClass enum value strings""" 1023101Sstever@eecs.umich.edu def boxOpClass(op_class): 1033101Sstever@eecs.umich.edu return MinorOpClass(opClass=op_class) 1043101Sstever@eecs.umich.edu 1053101Sstever@eecs.umich.edu return MinorOpClassSet(opClasses=[ boxOpClass(o) for o in op_classes ]) 1063101Sstever@eecs.umich.edu 1073101Sstever@eecs.umich.educlass MinorFU(SimObject): 1083101Sstever@eecs.umich.edu type = 'MinorFU' 1093101Sstever@eecs.umich.edu cxx_header = "cpu/minor/func_unit.hh" 1103102Sstever@eecs.umich.edu 1113101Sstever@eecs.umich.edu opClasses = Param.MinorOpClassSet(MinorOpClassSet(), "type of operations" 1123102Sstever@eecs.umich.edu " allowed on this functional unit") 1133101Sstever@eecs.umich.edu opLat = Param.Cycles(1, "latency in cycles") 1143101Sstever@eecs.umich.edu issueLat = Param.Cycles(1, "cycles until another instruction can be" 1153101Sstever@eecs.umich.edu " issued") 1163102Sstever@eecs.umich.edu timings = VectorParam.MinorFUTiming([], "extra decoding rules") 1173102Sstever@eecs.umich.edu 1183101Sstever@eecs.umich.edu cantForwardFromFUIndices = VectorParam.Unsigned([], 1193101Sstever@eecs.umich.edu "list of FU indices from which this FU can't receive and early" 1203101Sstever@eecs.umich.edu " (forwarded) result") 1213101Sstever@eecs.umich.edu 1223101Sstever@eecs.umich.educlass MinorFUPool(SimObject): 1233101Sstever@eecs.umich.edu type = 'MinorFUPool' 1243101Sstever@eecs.umich.edu cxx_header = "cpu/minor/func_unit.hh" 1253101Sstever@eecs.umich.edu 1263101Sstever@eecs.umich.edu funcUnits = VectorParam.MinorFU("functional units") 1273101Sstever@eecs.umich.edu 1283101Sstever@eecs.umich.educlass MinorDefaultIntFU(MinorFU): 1293101Sstever@eecs.umich.edu opClasses = minorMakeOpClassSet(['IntAlu']) 1303101Sstever@eecs.umich.edu timings = [MinorFUTiming(description="Int", 1313102Sstever@eecs.umich.edu srcRegsRelativeLats=[2])] 1323101Sstever@eecs.umich.edu opLat = 3 1333101Sstever@eecs.umich.edu 1343101Sstever@eecs.umich.educlass MinorDefaultIntMulFU(MinorFU): 1353101Sstever@eecs.umich.edu opClasses = minorMakeOpClassSet(['IntMult']) 1363101Sstever@eecs.umich.edu timings = [MinorFUTiming(description='Mul', 1373101Sstever@eecs.umich.edu srcRegsRelativeLats=[0])] 1383101Sstever@eecs.umich.edu opLat = 3 1393101Sstever@eecs.umich.edu 1403101Sstever@eecs.umich.educlass MinorDefaultIntDivFU(MinorFU): 1413101Sstever@eecs.umich.edu opClasses = minorMakeOpClassSet(['IntDiv']) 1423101Sstever@eecs.umich.edu issueLat = 9 1433101Sstever@eecs.umich.edu opLat = 9 1443101Sstever@eecs.umich.edu 1453101Sstever@eecs.umich.educlass MinorDefaultFloatSimdFU(MinorFU): 1463101Sstever@eecs.umich.edu opClasses = minorMakeOpClassSet([ 1473101Sstever@eecs.umich.edu 'FloatAdd', 'FloatCmp', 'FloatCvt', 'FloatMisc', 'FloatMult', 1483101Sstever@eecs.umich.edu 'FloatMultAcc', 'FloatDiv', 'FloatSqrt', 1493101Sstever@eecs.umich.edu 'SimdAdd', 'SimdAddAcc', 'SimdAlu', 'SimdCmp', 'SimdCvt', 1503101Sstever@eecs.umich.edu 'SimdMisc', 'SimdMult', 'SimdMultAcc', 'SimdShift', 'SimdShiftAcc', 1513101Sstever@eecs.umich.edu 'SimdDiv', 'SimdSqrt', 'SimdFloatAdd', 'SimdFloatAlu', 'SimdFloatCmp', 1523101Sstever@eecs.umich.edu 'SimdFloatCvt', 'SimdFloatDiv', 'SimdFloatMisc', 'SimdFloatMult', 1533101Sstever@eecs.umich.edu 'SimdFloatMultAcc', 'SimdFloatSqrt', 'SimdReduceAdd', 'SimdReduceAlu', 1543101Sstever@eecs.umich.edu 'SimdReduceCmp', 'SimdFloatReduceAdd', 'SimdFloatReduceCmp', 1553101Sstever@eecs.umich.edu 'SimdAes', 'SimdAesMix', 1563101Sstever@eecs.umich.edu 'SimdSha1Hash', 'SimdSha1Hash2', 'SimdSha256Hash', 1573101Sstever@eecs.umich.edu 'SimdSha256Hash2', 'SimdShaSigma2', 'SimdShaSigma3']) 1583101Sstever@eecs.umich.edu 1593101Sstever@eecs.umich.edu timings = [MinorFUTiming(description='FloatSimd', 1603101Sstever@eecs.umich.edu srcRegsRelativeLats=[2])] 1613101Sstever@eecs.umich.edu opLat = 6 1623101Sstever@eecs.umich.edu 1633101Sstever@eecs.umich.educlass MinorDefaultPredFU(MinorFU): 1643101Sstever@eecs.umich.edu opClasses = minorMakeOpClassSet(['SimdPredAlu']) 1653101Sstever@eecs.umich.edu timings = [MinorFUTiming(description="Pred", 1663101Sstever@eecs.umich.edu srcRegsRelativeLats=[2])] 1673101Sstever@eecs.umich.edu opLat = 3 1683101Sstever@eecs.umich.edu 1693101Sstever@eecs.umich.educlass MinorDefaultMemFU(MinorFU): 1703101Sstever@eecs.umich.edu opClasses = minorMakeOpClassSet(['MemRead', 'MemWrite', 'FloatMemRead', 1713101Sstever@eecs.umich.edu 'FloatMemWrite']) 1723101Sstever@eecs.umich.edu timings = [MinorFUTiming(description='Mem', 1733101Sstever@eecs.umich.edu srcRegsRelativeLats=[1], extraAssumedLat=2)] 1743101Sstever@eecs.umich.edu opLat = 1 1753101Sstever@eecs.umich.edu 1763101Sstever@eecs.umich.educlass MinorDefaultMiscFU(MinorFU): 1773101Sstever@eecs.umich.edu opClasses = minorMakeOpClassSet(['IprAccess', 'InstPrefetch']) 1783101Sstever@eecs.umich.edu opLat = 1 1793101Sstever@eecs.umich.edu 1803101Sstever@eecs.umich.educlass MinorDefaultFUPool(MinorFUPool): 1813101Sstever@eecs.umich.edu funcUnits = [MinorDefaultIntFU(), MinorDefaultIntFU(), 1823101Sstever@eecs.umich.edu MinorDefaultIntMulFU(), MinorDefaultIntDivFU(), 1833101Sstever@eecs.umich.edu MinorDefaultFloatSimdFU(), MinorDefaultPredFU(), 1843101Sstever@eecs.umich.edu MinorDefaultMemFU(), MinorDefaultMiscFU()] 1853101Sstever@eecs.umich.edu 1863101Sstever@eecs.umich.educlass ThreadPolicy(Enum): vals = ['SingleThreaded', 'RoundRobin', 'Random'] 1873101Sstever@eecs.umich.edu 1883101Sstever@eecs.umich.educlass MinorCPU(BaseCPU): 1893101Sstever@eecs.umich.edu type = 'MinorCPU' 1903101Sstever@eecs.umich.edu cxx_header = "cpu/minor/cpu.hh" 1913101Sstever@eecs.umich.edu 1923101Sstever@eecs.umich.edu @classmethod 1933101Sstever@eecs.umich.edu def memory_mode(cls): 1943101Sstever@eecs.umich.edu return 'timing' 1953101Sstever@eecs.umich.edu 1963101Sstever@eecs.umich.edu @classmethod 1973101Sstever@eecs.umich.edu def require_caches(cls): 1983101Sstever@eecs.umich.edu return True 1993101Sstever@eecs.umich.edu 2003101Sstever@eecs.umich.edu @classmethod 2013101Sstever@eecs.umich.edu def support_take_over(cls): 2023101Sstever@eecs.umich.edu return True 2033101Sstever@eecs.umich.edu 2043101Sstever@eecs.umich.edu threadPolicy = Param.ThreadPolicy('RoundRobin', 2053101Sstever@eecs.umich.edu "Thread scheduling policy") 2063101Sstever@eecs.umich.edu fetch1FetchLimit = Param.Unsigned(1, 2073101Sstever@eecs.umich.edu "Number of line fetches allowable in flight at once") 2083101Sstever@eecs.umich.edu fetch1LineSnapWidth = Param.Unsigned(0, 2093101Sstever@eecs.umich.edu "Fetch1 'line' fetch snap size in bytes" 2103101Sstever@eecs.umich.edu " (0 means use system cache line size)") 2113101Sstever@eecs.umich.edu fetch1LineWidth = Param.Unsigned(0, 2123101Sstever@eecs.umich.edu "Fetch1 maximum fetch size in bytes (0 means use system cache" 2133101Sstever@eecs.umich.edu " line size)") 2143101Sstever@eecs.umich.edu fetch1ToFetch2ForwardDelay = Param.Cycles(1, 2153101Sstever@eecs.umich.edu "Forward cycle delay from Fetch1 to Fetch2 (1 means next cycle)") 2163101Sstever@eecs.umich.edu fetch1ToFetch2BackwardDelay = Param.Cycles(1, 2173101Sstever@eecs.umich.edu "Backward cycle delay from Fetch2 to Fetch1 for branch prediction" 2183101Sstever@eecs.umich.edu " signalling (0 means in the same cycle, 1 mean the next cycle)") 2193101Sstever@eecs.umich.edu 2203101Sstever@eecs.umich.edu fetch2InputBufferSize = Param.Unsigned(2, 2213101Sstever@eecs.umich.edu "Size of input buffer to Fetch2 in cycles-worth of insts.") 2223101Sstever@eecs.umich.edu fetch2ToDecodeForwardDelay = Param.Cycles(1, 2233101Sstever@eecs.umich.edu "Forward cycle delay from Fetch2 to Decode (1 means next cycle)") 2243101Sstever@eecs.umich.edu fetch2CycleInput = Param.Bool(True, 2253101Sstever@eecs.umich.edu "Allow Fetch2 to cross input lines to generate full output each" 2263101Sstever@eecs.umich.edu " cycle") 2273101Sstever@eecs.umich.edu 2283101Sstever@eecs.umich.edu decodeInputBufferSize = Param.Unsigned(3, 2293101Sstever@eecs.umich.edu "Size of input buffer to Decode in cycles-worth of insts.") 2303101Sstever@eecs.umich.edu decodeToExecuteForwardDelay = Param.Cycles(1, 2313101Sstever@eecs.umich.edu "Forward cycle delay from Decode to Execute (1 means next cycle)") 2323101Sstever@eecs.umich.edu decodeInputWidth = Param.Unsigned(2, 2333101Sstever@eecs.umich.edu "Width (in instructions) of input to Decode (and implicitly" 2343101Sstever@eecs.umich.edu " Decode's own width)") 2353101Sstever@eecs.umich.edu decodeCycleInput = Param.Bool(True, 2363101Sstever@eecs.umich.edu "Allow Decode to pack instructions from more than one input cycle" 2373101Sstever@eecs.umich.edu " to fill its output each cycle") 2383101Sstever@eecs.umich.edu 2393101Sstever@eecs.umich.edu executeInputWidth = Param.Unsigned(2, 2403101Sstever@eecs.umich.edu "Width (in instructions) of input to Execute") 2413101Sstever@eecs.umich.edu executeCycleInput = Param.Bool(True, 2423101Sstever@eecs.umich.edu "Allow Execute to use instructions from more than one input cycle" 2433101Sstever@eecs.umich.edu " each cycle") 2443101Sstever@eecs.umich.edu executeIssueLimit = Param.Unsigned(2, 2453101Sstever@eecs.umich.edu "Number of issuable instructions in Execute each cycle") 2463714Sstever@eecs.umich.edu executeMemoryIssueLimit = Param.Unsigned(1, 2473714Sstever@eecs.umich.edu "Number of issuable memory instructions in Execute each cycle") 2483714Sstever@eecs.umich.edu executeCommitLimit = Param.Unsigned(2, 2493714Sstever@eecs.umich.edu "Number of committable instructions in Execute each cycle") 2503714Sstever@eecs.umich.edu executeMemoryCommitLimit = Param.Unsigned(1, 2513714Sstever@eecs.umich.edu "Number of committable memory references in Execute each cycle") 2523101Sstever@eecs.umich.edu executeInputBufferSize = Param.Unsigned(7, 2533101Sstever@eecs.umich.edu "Size of input buffer to Execute in cycles-worth of insts.") 2543101Sstever@eecs.umich.edu executeMemoryWidth = Param.Unsigned(0, 2553101Sstever@eecs.umich.edu "Width (and snap) in bytes of the data memory interface. (0 mean use" 2563101Sstever@eecs.umich.edu " the system cacheLineSize)") 2573101Sstever@eecs.umich.edu executeMaxAccessesInMemory = Param.Unsigned(2, 2583101Sstever@eecs.umich.edu "Maximum number of concurrent accesses allowed to the memory system" 2593101Sstever@eecs.umich.edu " from the dcache port") 2603101Sstever@eecs.umich.edu executeLSQMaxStoreBufferStoresPerCycle = Param.Unsigned(2, 2613101Sstever@eecs.umich.edu "Maximum number of stores that the store buffer can issue per cycle") 2623101Sstever@eecs.umich.edu executeLSQRequestsQueueSize = Param.Unsigned(1, 2633101Sstever@eecs.umich.edu "Size of LSQ requests queue (address translation queue)") 2643101Sstever@eecs.umich.edu executeLSQTransfersQueueSize = Param.Unsigned(2, 2653101Sstever@eecs.umich.edu "Size of LSQ transfers queue (memory transaction queue)") 2663101Sstever@eecs.umich.edu executeLSQStoreBufferSize = Param.Unsigned(5, 2673101Sstever@eecs.umich.edu "Size of LSQ store buffer") 2683101Sstever@eecs.umich.edu executeBranchDelay = Param.Cycles(1, 2693101Sstever@eecs.umich.edu "Delay from Execute deciding to branch and Fetch1 reacting" 2703101Sstever@eecs.umich.edu " (1 means next cycle)") 2713101Sstever@eecs.umich.edu 2723101Sstever@eecs.umich.edu executeFuncUnits = Param.MinorFUPool(MinorDefaultFUPool(), 2733101Sstever@eecs.umich.edu "FUlines for this processor") 2743101Sstever@eecs.umich.edu 2753101Sstever@eecs.umich.edu executeSetTraceTimeOnCommit = Param.Bool(True, 2763101Sstever@eecs.umich.edu "Set inst. trace times to be commit times") 2773101Sstever@eecs.umich.edu executeSetTraceTimeOnIssue = Param.Bool(False, 2783101Sstever@eecs.umich.edu "Set inst. trace times to be issue times") 2793101Sstever@eecs.umich.edu 2803101Sstever@eecs.umich.edu executeAllowEarlyMemoryIssue = Param.Bool(True, 2813101Sstever@eecs.umich.edu "Allow mem refs to be issued to the LSQ before reaching the head of" 2823101Sstever@eecs.umich.edu " the in flight insts queue") 2833101Sstever@eecs.umich.edu 2843101Sstever@eecs.umich.edu enableIdling = Param.Bool(True, 2853101Sstever@eecs.umich.edu "Enable cycle skipping when the processor is idle\n"); 2863101Sstever@eecs.umich.edu 2873101Sstever@eecs.umich.edu branchPred = Param.BranchPredictor(TournamentBP( 2883101Sstever@eecs.umich.edu numThreads = Parent.numThreads), "Branch Predictor") 2893101Sstever@eecs.umich.edu 2903101Sstever@eecs.umich.edu def addCheckerCpu(self): 2913101Sstever@eecs.umich.edu print("Checker not yet supported by MinorCPU") 2923101Sstever@eecs.umich.edu exit(1) 2933101Sstever@eecs.umich.edu