MinorCPU.py revision 13759 
1# Copyright (c) 2012-2014, 2017-2018 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder.  You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2007 The Regents of The University of Michigan
14# All rights reserved.
15#
16# Redistribution and use in source and binary forms, with or without
17# modification, are permitted provided that the following conditions are
18# met: redistributions of source code must retain the above copyright
19# notice, this list of conditions and the following disclaimer;
20# redistributions in binary form must reproduce the above copyright
21# notice, this list of conditions and the following disclaimer in the
22# documentation and/or other materials provided with the distribution;
23# neither the name of the copyright holders nor the names of its
24# contributors may be used to endorse or promote products derived from
25# this software without specific prior written permission.
26#
27# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
30# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
32# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38#
39# Authors: Gabe Black
40#          Nathan Binkert
41#          Andrew Bardsley
42
43from __future__ import print_function
44
45from m5.defines import buildEnv
46from m5.params import *
47from m5.proxy import *
48from m5.SimObject import SimObject
49from m5.objects.BaseCPU import BaseCPU
50from m5.objects.DummyChecker import DummyChecker
51from m5.objects.BranchPredictor import *
52from m5.objects.TimingExpr import TimingExpr
53
54from m5.objects.FuncUnit import OpClass
55
56class MinorOpClass(SimObject):
57    """Boxing of OpClass to get around build problems and provide a hook for
58    future additions to OpClass checks"""
59
60    type = 'MinorOpClass'
61    cxx_header = "cpu/minor/func_unit.hh"
62
63    opClass = Param.OpClass("op class to match")
64
65class MinorOpClassSet(SimObject):
66    """A set of matchable op classes"""
67
68    type = 'MinorOpClassSet'
69    cxx_header = "cpu/minor/func_unit.hh"
70
71    opClasses = VectorParam.MinorOpClass([], "op classes to be matched."
72        "  An empty list means any class")
73
74class MinorFUTiming(SimObject):
75    type = 'MinorFUTiming'
76    cxx_header = "cpu/minor/func_unit.hh"
77
78    mask = Param.UInt64(0, "mask for testing ExtMachInst")
79    match = Param.UInt64(0, "match value for testing ExtMachInst:"
80        " (ext_mach_inst & mask) == match")
81    suppress = Param.Bool(False, "if true, this inst. is not executed by"
82        " this FU")
83    extraCommitLat = Param.Cycles(0, "extra cycles to stall commit for"
84        " this inst.")
85    extraCommitLatExpr = Param.TimingExpr(NULL, "extra cycles as a"
86        " run-time evaluated expression")
87    extraAssumedLat = Param.Cycles(0, "extra cycles to add to scoreboard"
88        " retire time for this insts dest registers once it leaves the"
89        " functional unit.  For mem refs, if this is 0, the result's time"
90        " is marked as unpredictable and no forwarding can take place.")
91    srcRegsRelativeLats = VectorParam.Cycles("the maximum number of cycles"
92        " after inst. issue that each src reg can be available for this"
93        " inst. to issue")
94    opClasses = Param.MinorOpClassSet(MinorOpClassSet(),
95        "op classes to be considered for this decode.  An empty set means any"
96        " class")
97    description = Param.String('', "description string of the decoding/inst."
98        " class")
99
100def minorMakeOpClassSet(op_classes):
101    """Make a MinorOpClassSet from a list of OpClass enum value strings"""
102    def boxOpClass(op_class):
103        return MinorOpClass(opClass=op_class)
104
105    return MinorOpClassSet(opClasses=[ boxOpClass(o) for o in op_classes ])
106
107class MinorFU(SimObject):
108    type = 'MinorFU'
109    cxx_header = "cpu/minor/func_unit.hh"
110
111    opClasses = Param.MinorOpClassSet(MinorOpClassSet(), "type of operations"
112        " allowed on this functional unit")
113    opLat = Param.Cycles(1, "latency in cycles")
114    issueLat = Param.Cycles(1, "cycles until another instruction can be"
115        " issued")
116    timings = VectorParam.MinorFUTiming([], "extra decoding rules")
117
118    cantForwardFromFUIndices = VectorParam.Unsigned([],
119        "list of FU indices from which this FU can't receive and early"
120        " (forwarded) result")
121
122class MinorFUPool(SimObject):
123    type = 'MinorFUPool'
124    cxx_header = "cpu/minor/func_unit.hh"
125
126    funcUnits = VectorParam.MinorFU("functional units")
127
128class MinorDefaultIntFU(MinorFU):
129    opClasses = minorMakeOpClassSet(['IntAlu'])
130    timings = [MinorFUTiming(description="Int",
131        srcRegsRelativeLats=[2])]
132    opLat = 3
133
134class MinorDefaultIntMulFU(MinorFU):
135    opClasses = minorMakeOpClassSet(['IntMult'])
136    timings = [MinorFUTiming(description='Mul',
137        srcRegsRelativeLats=[0])]
138    opLat = 3
139
140class MinorDefaultIntDivFU(MinorFU):
141    opClasses = minorMakeOpClassSet(['IntDiv'])
142    issueLat = 9
143    opLat = 9
144
145class MinorDefaultFloatSimdFU(MinorFU):
146    opClasses = minorMakeOpClassSet([
147        'FloatAdd', 'FloatCmp', 'FloatCvt', 'FloatMisc', 'FloatMult',
148        'FloatMultAcc', 'FloatDiv', 'FloatSqrt',
149        'SimdAdd', 'SimdAddAcc', 'SimdAlu', 'SimdCmp', 'SimdCvt',
150        'SimdMisc', 'SimdMult', 'SimdMultAcc', 'SimdShift', 'SimdShiftAcc',
151        'SimdDiv', 'SimdSqrt', 'SimdFloatAdd', 'SimdFloatAlu', 'SimdFloatCmp',
152        'SimdFloatCvt', 'SimdFloatDiv', 'SimdFloatMisc', 'SimdFloatMult',
153        'SimdFloatMultAcc', 'SimdFloatSqrt', 'SimdReduceAdd', 'SimdReduceAlu',
154        'SimdReduceCmp', 'SimdFloatReduceAdd', 'SimdFloatReduceCmp',
155        'SimdAes', 'SimdAesMix',
156        'SimdSha1Hash', 'SimdSha1Hash2', 'SimdSha256Hash',
157        'SimdSha256Hash2', 'SimdShaSigma2', 'SimdShaSigma3'])
158
159    timings = [MinorFUTiming(description='FloatSimd',
160        srcRegsRelativeLats=[2])]
161    opLat = 6
162
163class MinorDefaultPredFU(MinorFU):
164    opClasses = minorMakeOpClassSet(['SimdPredAlu'])
165    timings = [MinorFUTiming(description="Pred",
166        srcRegsRelativeLats=[2])]
167    opLat = 3
168
169class MinorDefaultMemFU(MinorFU):
170    opClasses = minorMakeOpClassSet(['MemRead', 'MemWrite', 'FloatMemRead',
171                                     'FloatMemWrite'])
172    timings = [MinorFUTiming(description='Mem',
173        srcRegsRelativeLats=[1], extraAssumedLat=2)]
174    opLat = 1
175
176class MinorDefaultMiscFU(MinorFU):
177    opClasses = minorMakeOpClassSet(['IprAccess', 'InstPrefetch'])
178    opLat = 1
179
180class MinorDefaultFUPool(MinorFUPool):
181    funcUnits = [MinorDefaultIntFU(), MinorDefaultIntFU(),
182        MinorDefaultIntMulFU(), MinorDefaultIntDivFU(),
183        MinorDefaultFloatSimdFU(), MinorDefaultPredFU(),
184        MinorDefaultMemFU(), MinorDefaultMiscFU()]
185
186class ThreadPolicy(Enum): vals = ['SingleThreaded', 'RoundRobin', 'Random']
187
188class MinorCPU(BaseCPU):
189    type = 'MinorCPU'
190    cxx_header = "cpu/minor/cpu.hh"
191
192    @classmethod
193    def memory_mode(cls):
194        return 'timing'
195
196    @classmethod
197    def require_caches(cls):
198        return True
199
200    @classmethod
201    def support_take_over(cls):
202        return True
203
204    threadPolicy = Param.ThreadPolicy('RoundRobin',
205            "Thread scheduling policy")
206    fetch1FetchLimit = Param.Unsigned(1,
207        "Number of line fetches allowable in flight at once")
208    fetch1LineSnapWidth = Param.Unsigned(0,
209        "Fetch1 'line' fetch snap size in bytes"
210        " (0 means use system cache line size)")
211    fetch1LineWidth = Param.Unsigned(0,
212        "Fetch1 maximum fetch size in bytes (0 means use system cache"
213        " line size)")
214    fetch1ToFetch2ForwardDelay = Param.Cycles(1,
215        "Forward cycle delay from Fetch1 to Fetch2 (1 means next cycle)")
216    fetch1ToFetch2BackwardDelay = Param.Cycles(1,
217        "Backward cycle delay from Fetch2 to Fetch1 for branch prediction"
218        " signalling (0 means in the same cycle, 1 mean the next cycle)")
219
220    fetch2InputBufferSize = Param.Unsigned(2,
221        "Size of input buffer to Fetch2 in cycles-worth of insts.")
222    fetch2ToDecodeForwardDelay = Param.Cycles(1,
223        "Forward cycle delay from Fetch2 to Decode (1 means next cycle)")
224    fetch2CycleInput = Param.Bool(True,
225        "Allow Fetch2 to cross input lines to generate full output each"
226        " cycle")
227
228    decodeInputBufferSize = Param.Unsigned(3,
229        "Size of input buffer to Decode in cycles-worth of insts.")
230    decodeToExecuteForwardDelay = Param.Cycles(1,
231        "Forward cycle delay from Decode to Execute (1 means next cycle)")
232    decodeInputWidth = Param.Unsigned(2,
233        "Width (in instructions) of input to Decode (and implicitly"
234        " Decode's own width)")
235    decodeCycleInput = Param.Bool(True,
236        "Allow Decode to pack instructions from more than one input cycle"
237        " to fill its output each cycle")
238
239    executeInputWidth = Param.Unsigned(2,
240        "Width (in instructions) of input to Execute")
241    executeCycleInput = Param.Bool(True,
242        "Allow Execute to use instructions from more than one input cycle"
243        " each cycle")
244    executeIssueLimit = Param.Unsigned(2,
245        "Number of issuable instructions in Execute each cycle")
246    executeMemoryIssueLimit = Param.Unsigned(1,
247        "Number of issuable memory instructions in Execute each cycle")
248    executeCommitLimit = Param.Unsigned(2,
249        "Number of committable instructions in Execute each cycle")
250    executeMemoryCommitLimit = Param.Unsigned(1,
251        "Number of committable memory references in Execute each cycle")
252    executeInputBufferSize = Param.Unsigned(7,
253        "Size of input buffer to Execute in cycles-worth of insts.")
254    executeMemoryWidth = Param.Unsigned(0,
255        "Width (and snap) in bytes of the data memory interface. (0 mean use"
256        " the system cacheLineSize)")
257    executeMaxAccessesInMemory = Param.Unsigned(2,
258        "Maximum number of concurrent accesses allowed to the memory system"
259        " from the dcache port")
260    executeLSQMaxStoreBufferStoresPerCycle = Param.Unsigned(2,
261        "Maximum number of stores that the store buffer can issue per cycle")
262    executeLSQRequestsQueueSize = Param.Unsigned(1,
263        "Size of LSQ requests queue (address translation queue)")
264    executeLSQTransfersQueueSize = Param.Unsigned(2,
265        "Size of LSQ transfers queue (memory transaction queue)")
266    executeLSQStoreBufferSize = Param.Unsigned(5,
267        "Size of LSQ store buffer")
268    executeBranchDelay = Param.Cycles(1,
269        "Delay from Execute deciding to branch and Fetch1 reacting"
270        " (1 means next cycle)")
271
272    executeFuncUnits = Param.MinorFUPool(MinorDefaultFUPool(),
273        "FUlines for this processor")
274
275    executeSetTraceTimeOnCommit = Param.Bool(True,
276        "Set inst. trace times to be commit times")
277    executeSetTraceTimeOnIssue = Param.Bool(False,
278        "Set inst. trace times to be issue times")
279
280    executeAllowEarlyMemoryIssue = Param.Bool(True,
281        "Allow mem refs to be issued to the LSQ before reaching the head of"
282        " the in flight insts queue")
283
284    enableIdling = Param.Bool(True,
285        "Enable cycle skipping when the processor is idle\n");
286
287    branchPred = Param.BranchPredictor(TournamentBP(
288        numThreads = Parent.numThreads), "Branch Predictor")
289
290    def addCheckerCpu(self):
291        print("Checker not yet supported by MinorCPU")
292        exit(1)
293