MinorCPU.py revision 10785
113559Snikos.nikoleris@arm.com# Copyright (c) 2012-2014 ARM Limited 212109SRekai.GonzalezAlberquilla@arm.com# All rights reserved. 312109SRekai.GonzalezAlberquilla@arm.com# 412109SRekai.GonzalezAlberquilla@arm.com# The license below extends only to copyright in the software and shall 512109SRekai.GonzalezAlberquilla@arm.com# not be construed as granting a license to any other intellectual 612109SRekai.GonzalezAlberquilla@arm.com# property including but not limited to intellectual property relating 712109SRekai.GonzalezAlberquilla@arm.com# to a hardware implementation of the functionality of the software 812109SRekai.GonzalezAlberquilla@arm.com# licensed hereunder. You may use the software subject to the license 912109SRekai.GonzalezAlberquilla@arm.com# terms below provided that you ensure that this notice is replicated 1012109SRekai.GonzalezAlberquilla@arm.com# unmodified and in its entirety in all distributions of the software, 1112109SRekai.GonzalezAlberquilla@arm.com# modified or unmodified, in source code or in binary form. 1212109SRekai.GonzalezAlberquilla@arm.com# 134486Sbinkertn@umich.edu# Copyright (c) 2007 The Regents of The University of Michigan 144486Sbinkertn@umich.edu# All rights reserved. 154486Sbinkertn@umich.edu# 164486Sbinkertn@umich.edu# Redistribution and use in source and binary forms, with or without 174486Sbinkertn@umich.edu# modification, are permitted provided that the following conditions are 184486Sbinkertn@umich.edu# met: redistributions of source code must retain the above copyright 194486Sbinkertn@umich.edu# notice, this list of conditions and the following disclaimer; 204486Sbinkertn@umich.edu# redistributions in binary form must reproduce the above copyright 214486Sbinkertn@umich.edu# notice, this list of conditions and the following disclaimer in the 224486Sbinkertn@umich.edu# documentation and/or other materials provided with the distribution; 234486Sbinkertn@umich.edu# neither the name of the copyright holders nor the names of its 244486Sbinkertn@umich.edu# contributors may be used to endorse or promote products derived from 254486Sbinkertn@umich.edu# this software without specific prior written permission. 264486Sbinkertn@umich.edu# 274486Sbinkertn@umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 284486Sbinkertn@umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 294486Sbinkertn@umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 304486Sbinkertn@umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 314486Sbinkertn@umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 324486Sbinkertn@umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 334486Sbinkertn@umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 344486Sbinkertn@umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 354486Sbinkertn@umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 364486Sbinkertn@umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 374486Sbinkertn@umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 384486Sbinkertn@umich.edu# 394486Sbinkertn@umich.edu# Authors: Gabe Black 404486Sbinkertn@umich.edu# Nathan Binkert 4112563Sgabeblack@google.com# Andrew Bardsley 4212563Sgabeblack@google.com 436654Snate@binkert.orgfrom m5.defines import buildEnv 443102SN/Afrom m5.params import * 453102SN/Afrom m5.proxy import * 461681SN/Afrom m5.SimObject import SimObject 473223SN/Afrom BaseCPU import BaseCPU 488887Sgeoffrey.blake@arm.comfrom DummyChecker import DummyChecker 4910785Sgope@wisc.edufrom BranchPredictor import * 504486Sbinkertn@umich.edufrom TimingExpr import TimingExpr 5113559Snikos.nikoleris@arm.com 5213559Snikos.nikoleris@arm.comfrom FuncUnit import OpClass 5313559Snikos.nikoleris@arm.com 5413560Snikos.nikoleris@arm.comclass MinorOpClass(SimObject): 5513560Snikos.nikoleris@arm.com """Boxing of OpClass to get around build problems and provide a hook for 5613560Snikos.nikoleris@arm.com future additions to OpClass checks""" 5713563Snikos.nikoleris@arm.com 5813563Snikos.nikoleris@arm.com type = 'MinorOpClass' 5913563Snikos.nikoleris@arm.com cxx_header = "cpu/minor/func_unit.hh" 602817SN/A 612817SN/A opClass = Param.OpClass("op class to match") 629341SAndreas.Sandberg@arm.com 639341SAndreas.Sandberg@arm.comclass MinorOpClassSet(SimObject): 649518SAndreas.Sandberg@ARM.com """A set of matchable op classes""" 659518SAndreas.Sandberg@ARM.com 669518SAndreas.Sandberg@ARM.com type = 'MinorOpClassSet' 679518SAndreas.Sandberg@ARM.com cxx_header = "cpu/minor/func_unit.hh" 689518SAndreas.Sandberg@ARM.com 699518SAndreas.Sandberg@ARM.com opClasses = VectorParam.MinorOpClass([], "op classes to be matched." 709518SAndreas.Sandberg@ARM.com " An empty list means any class") 719518SAndreas.Sandberg@ARM.com 729518SAndreas.Sandberg@ARM.comclass MinorFUTiming(SimObject): 739518SAndreas.Sandberg@ARM.com type = 'MinorFUTiming' 749518SAndreas.Sandberg@ARM.com cxx_header = "cpu/minor/func_unit.hh" 759518SAndreas.Sandberg@ARM.com 762932SN/A mask = Param.UInt64(0, "mask for testing ExtMachInst") 771681SN/A match = Param.UInt64(0, "match value for testing ExtMachInst:" 7811780Sarthur.perais@inria.fr " (ext_mach_inst & mask) == match") 7911780Sarthur.perais@inria.fr suppress = Param.Bool(False, "if true, this inst. is not executed by" 801681SN/A " this FU") 819184Sandreas.hansson@arm.com extraCommitLat = Param.Cycles(0, "extra cycles to stall commit for" 829184Sandreas.hansson@arm.com " this inst.") 839184Sandreas.hansson@arm.com extraCommitLatExpr = Param.TimingExpr(NULL, "extra cycles as a" 849184Sandreas.hansson@arm.com " run-time evaluated expression") 859184Sandreas.hansson@arm.com extraAssumedLat = Param.Cycles(0, "extra cycles to add to scoreboard" 862932SN/A " retire time for this insts dest registers once it leaves the" 879982Satgutier@umich.edu " functional unit. For mem refs, if this is 0, the result's time" 8810331Smitch.hayenga@arm.com " is marked as unpredictable and no forwarding can take place.") 8910331Smitch.hayenga@arm.com srcRegsRelativeLats = VectorParam.Cycles("the maximum number of cycles" 902932SN/A " after inst. issue that each src reg can be available for this" 919184Sandreas.hansson@arm.com " inst. to issue") 929184Sandreas.hansson@arm.com opClasses = Param.MinorOpClassSet(MinorOpClassSet(), 939184Sandreas.hansson@arm.com "op classes to be considered for this decode. An empty set means any" 949184Sandreas.hansson@arm.com " class") 959184Sandreas.hansson@arm.com description = Param.String('', "description string of the decoding/inst." 962932SN/A " class") 971681SN/A 989184Sandreas.hansson@arm.comdef minorMakeOpClassSet(op_classes): 999184Sandreas.hansson@arm.com """Make a MinorOpClassSet from a list of OpClass enum value strings""" 1009184Sandreas.hansson@arm.com def boxOpClass(op_class): 1019184Sandreas.hansson@arm.com return MinorOpClass(opClass=op_class) 1022932SN/A 1031681SN/A return MinorOpClassSet(opClasses=map(boxOpClass, op_classes)) 1049184Sandreas.hansson@arm.com 1052932SN/Aclass MinorFU(SimObject): 1069184Sandreas.hansson@arm.com type = 'MinorFU' 1072932SN/A cxx_header = "cpu/minor/func_unit.hh" 1089184Sandreas.hansson@arm.com 1092932SN/A opClasses = Param.MinorOpClassSet(MinorOpClassSet(), "type of operations" 1102932SN/A " allowed on this functional unit") 1112932SN/A opLat = Param.Cycles(1, "latency in cycles") 1122932SN/A issueLat = Param.Cycles(1, "cycles until another instruction can be" 1133223SN/A " issued") 1142932SN/A timings = VectorParam.MinorFUTiming([], "extra decoding rules") 1159184Sandreas.hansson@arm.com 1161681SN/A cantForwardFromFUIndices = VectorParam.Unsigned([], 1179184Sandreas.hansson@arm.com "list of FU indices from which this FU can't receive and early" 1182932SN/A " (forwarded) result") 1192932SN/A 1209184Sandreas.hansson@arm.comclass MinorFUPool(SimObject): 1219184Sandreas.hansson@arm.com type = 'MinorFUPool' 1221681SN/A cxx_header = "cpu/minor/func_unit.hh" 1232932SN/A 1242932SN/A funcUnits = VectorParam.MinorFU("functional units") 1251681SN/A 1262932SN/Aclass MinorDefaultIntFU(MinorFU): 1272932SN/A opClasses = minorMakeOpClassSet(['IntAlu']) 1288199SAli.Saidi@ARM.com timings = [MinorFUTiming(description="Int", 1298199SAli.Saidi@ARM.com srcRegsRelativeLats=[2])] 1308199SAli.Saidi@ARM.com opLat = 3 1318519SAli.Saidi@ARM.com 1328519SAli.Saidi@ARM.comclass MinorDefaultIntMulFU(MinorFU): 1332932SN/A opClasses = minorMakeOpClassSet(['IntMult']) 1342932SN/A timings = [MinorFUTiming(description='Mul', 1351681SN/A srcRegsRelativeLats=[0])] 1362932SN/A opLat = 3 1371681SN/A 1382932SN/Aclass MinorDefaultIntDivFU(MinorFU): 1392932SN/A opClasses = minorMakeOpClassSet(['IntDiv']) 1402932SN/A issueLat = 9 1419921Syasuko.eckert@amd.com opLat = 9 1429921Syasuko.eckert@amd.com 14310338SCurtis.Dunham@arm.comclass MinorDefaultFloatSimdFU(MinorFU): 1449921Syasuko.eckert@amd.com opClasses = minorMakeOpClassSet([ 1459921Syasuko.eckert@amd.com 'FloatAdd', 'FloatCmp', 'FloatCvt', 'FloatMult', 'FloatDiv', 1469921Syasuko.eckert@amd.com 'FloatSqrt', 1479921Syasuko.eckert@amd.com 'SimdAdd', 'SimdAddAcc', 'SimdAlu', 'SimdCmp', 'SimdCvt', 1489921Syasuko.eckert@amd.com 'SimdMisc', 'SimdMult', 'SimdMultAcc', 'SimdShift', 'SimdShiftAcc', 1499921Syasuko.eckert@amd.com 'SimdSqrt', 'SimdFloatAdd', 'SimdFloatAlu', 'SimdFloatCmp', 1509921Syasuko.eckert@amd.com 'SimdFloatCvt', 'SimdFloatDiv', 'SimdFloatMisc', 'SimdFloatMult', 15112109SRekai.GonzalezAlberquilla@arm.com 'SimdFloatMultAcc', 'SimdFloatSqrt']) 15212109SRekai.GonzalezAlberquilla@arm.com timings = [MinorFUTiming(description='FloatSimd', 15313610Sgiacomo.gabrielli@arm.com srcRegsRelativeLats=[2])] 15413610Sgiacomo.gabrielli@arm.com opLat = 6 1559921Syasuko.eckert@amd.com 1569921Syasuko.eckert@amd.comclass MinorDefaultMemFU(MinorFU): 1572932SN/A opClasses = minorMakeOpClassSet(['MemRead', 'MemWrite']) 1582932SN/A timings = [MinorFUTiming(description='Mem', 1591681SN/A srcRegsRelativeLats=[1], extraAssumedLat=2)] 1604597Sbinkertn@umich.edu opLat = 1 16113559Snikos.nikoleris@arm.com 16213560Snikos.nikoleris@arm.comclass MinorDefaultMiscFU(MinorFU): 16313560Snikos.nikoleris@arm.com opClasses = minorMakeOpClassSet(['IprAccess', 'InstPrefetch']) 1644597Sbinkertn@umich.edu opLat = 1 16513561Snikos.nikoleris@arm.com 16613561Snikos.nikoleris@arm.comclass MinorDefaultFUPool(MinorFUPool): 1674597Sbinkertn@umich.edu funcUnits = [MinorDefaultIntFU(), MinorDefaultIntFU(), 16813562Snikos.nikoleris@arm.com MinorDefaultIntMulFU(), MinorDefaultIntDivFU(), 16913562Snikos.nikoleris@arm.com MinorDefaultFloatSimdFU(), MinorDefaultMemFU(), 1704597Sbinkertn@umich.edu MinorDefaultMiscFU()] 17113563Snikos.nikoleris@arm.com 1724303SN/Aclass MinorCPU(BaseCPU): 17310785Sgope@wisc.edu type = 'MinorCPU' 1749849Sandreas.hansson@arm.com cxx_header = "cpu/minor/cpu.hh" 1759849Sandreas.hansson@arm.com 1768727Snilay@cs.wisc.edu @classmethod 1778727Snilay@cs.wisc.edu def memory_mode(cls): 1788887Sgeoffrey.blake@arm.com return 'timing' 1798887Sgeoffrey.blake@arm.com 1808887Sgeoffrey.blake@arm.com @classmethod 1818887Sgeoffrey.blake@arm.com def require_caches(cls): 1828887Sgeoffrey.blake@arm.com return True 1838887Sgeoffrey.blake@arm.com 1848887Sgeoffrey.blake@arm.com @classmethod 1858887Sgeoffrey.blake@arm.com def support_take_over(cls): 1868887Sgeoffrey.blake@arm.com return True 1878887Sgeoffrey.blake@arm.com 1888887Sgeoffrey.blake@arm.com fetch1FetchLimit = Param.Unsigned(1, 1899132Satgutier@umich.edu "Number of line fetches allowable in flight at once") 1908887Sgeoffrey.blake@arm.com fetch1LineSnapWidth = Param.Unsigned(0, 1918887Sgeoffrey.blake@arm.com "Fetch1 'line' fetch snap size in bytes" 19212563Sgabeblack@google.com " (0 means use system cache line size)") 1938887Sgeoffrey.blake@arm.com fetch1LineWidth = Param.Unsigned(0, 194 "Fetch1 maximum fetch size in bytes (0 means use system cache" 195 " line size)") 196 fetch1ToFetch2ForwardDelay = Param.Cycles(1, 197 "Forward cycle delay from Fetch1 to Fetch2 (1 means next cycle)") 198 fetch1ToFetch2BackwardDelay = Param.Cycles(1, 199 "Backward cycle delay from Fetch2 to Fetch1 for branch prediction" 200 " signalling (0 means in the same cycle, 1 mean the next cycle)") 201 202 fetch2InputBufferSize = Param.Unsigned(2, 203 "Size of input buffer to Fetch2 in cycles-worth of insts.") 204 fetch2ToDecodeForwardDelay = Param.Cycles(1, 205 "Forward cycle delay from Fetch2 to Decode (1 means next cycle)") 206 fetch2CycleInput = Param.Bool(True, 207 "Allow Fetch2 to cross input lines to generate full output each" 208 " cycle") 209 210 decodeInputBufferSize = Param.Unsigned(3, 211 "Size of input buffer to Decode in cycles-worth of insts.") 212 decodeToExecuteForwardDelay = Param.Cycles(1, 213 "Forward cycle delay from Decode to Execute (1 means next cycle)") 214 decodeInputWidth = Param.Unsigned(2, 215 "Width (in instructions) of input to Decode (and implicitly" 216 " Decode's own width)") 217 decodeCycleInput = Param.Bool(True, 218 "Allow Decode to pack instructions from more than one input cycle" 219 " to fill its output each cycle") 220 221 executeInputWidth = Param.Unsigned(2, 222 "Width (in instructions) of input to Execute") 223 executeCycleInput = Param.Bool(True, 224 "Allow Execute to use instructions from more than one input cycle" 225 " each cycle") 226 executeIssueLimit = Param.Unsigned(2, 227 "Number of issuable instructions in Execute each cycle") 228 executeMemoryIssueLimit = Param.Unsigned(1, 229 "Number of issuable memory instructions in Execute each cycle") 230 executeCommitLimit = Param.Unsigned(2, 231 "Number of committable instructions in Execute each cycle") 232 executeMemoryCommitLimit = Param.Unsigned(1, 233 "Number of committable memory references in Execute each cycle") 234 executeInputBufferSize = Param.Unsigned(7, 235 "Size of input buffer to Execute in cycles-worth of insts.") 236 executeMemoryWidth = Param.Unsigned(0, 237 "Width (and snap) in bytes of the data memory interface. (0 mean use" 238 " the system cacheLineSize)") 239 executeMaxAccessesInMemory = Param.Unsigned(2, 240 "Maximum number of concurrent accesses allowed to the memory system" 241 " from the dcache port") 242 executeLSQMaxStoreBufferStoresPerCycle = Param.Unsigned(2, 243 "Maximum number of stores that the store buffer can issue per cycle") 244 executeLSQRequestsQueueSize = Param.Unsigned(1, 245 "Size of LSQ requests queue (address translation queue)") 246 executeLSQTransfersQueueSize = Param.Unsigned(2, 247 "Size of LSQ transfers queue (memory transaction queue)") 248 executeLSQStoreBufferSize = Param.Unsigned(5, 249 "Size of LSQ store buffer") 250 executeBranchDelay = Param.Cycles(1, 251 "Delay from Execute deciding to branch and Fetch1 reacting" 252 " (1 means next cycle)") 253 254 executeFuncUnits = Param.MinorFUPool(MinorDefaultFUPool(), 255 "FUlines for this processor") 256 257 executeSetTraceTimeOnCommit = Param.Bool(True, 258 "Set inst. trace times to be commit times") 259 executeSetTraceTimeOnIssue = Param.Bool(False, 260 "Set inst. trace times to be issue times") 261 262 executeAllowEarlyMemoryIssue = Param.Bool(True, 263 "Allow mem refs to be issued to the LSQ before reaching the head of" 264 " the in flight insts queue") 265 266 enableIdling = Param.Bool(True, 267 "Enable cycle skipping when the processor is idle\n"); 268 269 branchPred = Param.BranchPredictor(TournamentBP( 270 numThreads = Parent.numThreads), "Branch Predictor") 271 272 def addCheckerCpu(self): 273 print "Checker not yet supported by MinorCPU" 274 exit(1) 275