MinorCPU.py revision 10785 
1# Copyright (c) 2012-2014 ARM Limited
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13# Copyright (c) 2007 The Regents of The University of Michigan
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38#
39# Authors: Gabe Black
40#          Nathan Binkert
41#          Andrew Bardsley
42
43from m5.defines import buildEnv
44from m5.params import *
45from m5.proxy import *
46from m5.SimObject import SimObject
47from BaseCPU import BaseCPU
48from DummyChecker import DummyChecker
49from BranchPredictor import *
50from TimingExpr import TimingExpr
51
52from FuncUnit import OpClass
53
54class MinorOpClass(SimObject):
55    """Boxing of OpClass to get around build problems and provide a hook for
56    future additions to OpClass checks"""
57
58    type = 'MinorOpClass'
59    cxx_header = "cpu/minor/func_unit.hh"
60
61    opClass = Param.OpClass("op class to match")
62
63class MinorOpClassSet(SimObject):
64    """A set of matchable op classes"""
65
66    type = 'MinorOpClassSet'
67    cxx_header = "cpu/minor/func_unit.hh"
68
69    opClasses = VectorParam.MinorOpClass([], "op classes to be matched."
70        "  An empty list means any class")
71
72class MinorFUTiming(SimObject):
73    type = 'MinorFUTiming'
74    cxx_header = "cpu/minor/func_unit.hh"
75
76    mask = Param.UInt64(0, "mask for testing ExtMachInst")
77    match = Param.UInt64(0, "match value for testing ExtMachInst:"
78        " (ext_mach_inst & mask) == match")
79    suppress = Param.Bool(False, "if true, this inst. is not executed by"
80        " this FU")
81    extraCommitLat = Param.Cycles(0, "extra cycles to stall commit for"
82        " this inst.")
83    extraCommitLatExpr = Param.TimingExpr(NULL, "extra cycles as a"
84        " run-time evaluated expression")
85    extraAssumedLat = Param.Cycles(0, "extra cycles to add to scoreboard"
86        " retire time for this insts dest registers once it leaves the"
87        " functional unit.  For mem refs, if this is 0, the result's time"
88        " is marked as unpredictable and no forwarding can take place.")
89    srcRegsRelativeLats = VectorParam.Cycles("the maximum number of cycles"
90        " after inst. issue that each src reg can be available for this"
91        " inst. to issue")
92    opClasses = Param.MinorOpClassSet(MinorOpClassSet(),
93        "op classes to be considered for this decode.  An empty set means any"
94        " class")
95    description = Param.String('', "description string of the decoding/inst."
96        " class")
97
98def minorMakeOpClassSet(op_classes):
99    """Make a MinorOpClassSet from a list of OpClass enum value strings"""
100    def boxOpClass(op_class):
101        return MinorOpClass(opClass=op_class)
102
103    return MinorOpClassSet(opClasses=map(boxOpClass, op_classes))
104
105class MinorFU(SimObject):
106    type = 'MinorFU'
107    cxx_header = "cpu/minor/func_unit.hh"
108
109    opClasses = Param.MinorOpClassSet(MinorOpClassSet(), "type of operations"
110        " allowed on this functional unit")
111    opLat = Param.Cycles(1, "latency in cycles")
112    issueLat = Param.Cycles(1, "cycles until another instruction can be"
113        " issued")
114    timings = VectorParam.MinorFUTiming([], "extra decoding rules")
115
116    cantForwardFromFUIndices = VectorParam.Unsigned([],
117        "list of FU indices from which this FU can't receive and early"
118        " (forwarded) result")
119
120class MinorFUPool(SimObject):
121    type = 'MinorFUPool'
122    cxx_header = "cpu/minor/func_unit.hh"
123
124    funcUnits = VectorParam.MinorFU("functional units")
125
126class MinorDefaultIntFU(MinorFU):
127    opClasses = minorMakeOpClassSet(['IntAlu'])
128    timings = [MinorFUTiming(description="Int",
129        srcRegsRelativeLats=[2])]
130    opLat = 3
131
132class MinorDefaultIntMulFU(MinorFU):
133    opClasses = minorMakeOpClassSet(['IntMult'])
134    timings = [MinorFUTiming(description='Mul',
135        srcRegsRelativeLats=[0])]
136    opLat = 3
137
138class MinorDefaultIntDivFU(MinorFU):
139    opClasses = minorMakeOpClassSet(['IntDiv'])
140    issueLat = 9
141    opLat = 9
142
143class MinorDefaultFloatSimdFU(MinorFU):
144    opClasses = minorMakeOpClassSet([
145        'FloatAdd', 'FloatCmp', 'FloatCvt', 'FloatMult', 'FloatDiv',
146        'FloatSqrt',
147        'SimdAdd', 'SimdAddAcc', 'SimdAlu', 'SimdCmp', 'SimdCvt',
148        'SimdMisc', 'SimdMult', 'SimdMultAcc', 'SimdShift', 'SimdShiftAcc',
149        'SimdSqrt', 'SimdFloatAdd', 'SimdFloatAlu', 'SimdFloatCmp',
150        'SimdFloatCvt', 'SimdFloatDiv', 'SimdFloatMisc', 'SimdFloatMult',
151        'SimdFloatMultAcc', 'SimdFloatSqrt'])
152    timings = [MinorFUTiming(description='FloatSimd',
153        srcRegsRelativeLats=[2])]
154    opLat = 6
155
156class MinorDefaultMemFU(MinorFU):
157    opClasses = minorMakeOpClassSet(['MemRead', 'MemWrite'])
158    timings = [MinorFUTiming(description='Mem',
159        srcRegsRelativeLats=[1], extraAssumedLat=2)]
160    opLat = 1
161
162class MinorDefaultMiscFU(MinorFU):
163    opClasses = minorMakeOpClassSet(['IprAccess', 'InstPrefetch'])
164    opLat = 1
165
166class MinorDefaultFUPool(MinorFUPool):
167    funcUnits = [MinorDefaultIntFU(), MinorDefaultIntFU(),
168        MinorDefaultIntMulFU(), MinorDefaultIntDivFU(),
169        MinorDefaultFloatSimdFU(), MinorDefaultMemFU(),
170        MinorDefaultMiscFU()]
171
172class MinorCPU(BaseCPU):
173    type = 'MinorCPU'
174    cxx_header = "cpu/minor/cpu.hh"
175
176    @classmethod
177    def memory_mode(cls):
178        return 'timing'
179
180    @classmethod
181    def require_caches(cls):
182        return True
183
184    @classmethod
185    def support_take_over(cls):
186        return True
187
188    fetch1FetchLimit = Param.Unsigned(1,
189        "Number of line fetches allowable in flight at once")
190    fetch1LineSnapWidth = Param.Unsigned(0,
191        "Fetch1 'line' fetch snap size in bytes"
192        " (0 means use system cache line size)")
193    fetch1LineWidth = Param.Unsigned(0,
194        "Fetch1 maximum fetch size in bytes (0 means use system cache"
195        " line size)")
196    fetch1ToFetch2ForwardDelay = Param.Cycles(1,
197        "Forward cycle delay from Fetch1 to Fetch2 (1 means next cycle)")
198    fetch1ToFetch2BackwardDelay = Param.Cycles(1,
199        "Backward cycle delay from Fetch2 to Fetch1 for branch prediction"
200        " signalling (0 means in the same cycle, 1 mean the next cycle)")
201
202    fetch2InputBufferSize = Param.Unsigned(2,
203        "Size of input buffer to Fetch2 in cycles-worth of insts.")
204    fetch2ToDecodeForwardDelay = Param.Cycles(1,
205        "Forward cycle delay from Fetch2 to Decode (1 means next cycle)")
206    fetch2CycleInput = Param.Bool(True,
207        "Allow Fetch2 to cross input lines to generate full output each"
208        " cycle")
209
210    decodeInputBufferSize = Param.Unsigned(3,
211        "Size of input buffer to Decode in cycles-worth of insts.")
212    decodeToExecuteForwardDelay = Param.Cycles(1,
213        "Forward cycle delay from Decode to Execute (1 means next cycle)")
214    decodeInputWidth = Param.Unsigned(2,
215        "Width (in instructions) of input to Decode (and implicitly"
216        " Decode's own width)")
217    decodeCycleInput = Param.Bool(True,
218        "Allow Decode to pack instructions from more than one input cycle"
219        " to fill its output each cycle")
220
221    executeInputWidth = Param.Unsigned(2,
222        "Width (in instructions) of input to Execute")
223    executeCycleInput = Param.Bool(True,
224        "Allow Execute to use instructions from more than one input cycle"
225        " each cycle")
226    executeIssueLimit = Param.Unsigned(2,
227        "Number of issuable instructions in Execute each cycle")
228    executeMemoryIssueLimit = Param.Unsigned(1,
229        "Number of issuable memory instructions in Execute each cycle")
230    executeCommitLimit = Param.Unsigned(2,
231        "Number of committable instructions in Execute each cycle")
232    executeMemoryCommitLimit = Param.Unsigned(1,
233        "Number of committable memory references in Execute each cycle")
234    executeInputBufferSize = Param.Unsigned(7,
235        "Size of input buffer to Execute in cycles-worth of insts.")
236    executeMemoryWidth = Param.Unsigned(0,
237        "Width (and snap) in bytes of the data memory interface. (0 mean use"
238        " the system cacheLineSize)")
239    executeMaxAccessesInMemory = Param.Unsigned(2,
240        "Maximum number of concurrent accesses allowed to the memory system"
241        " from the dcache port")
242    executeLSQMaxStoreBufferStoresPerCycle = Param.Unsigned(2,
243        "Maximum number of stores that the store buffer can issue per cycle")
244    executeLSQRequestsQueueSize = Param.Unsigned(1,
245        "Size of LSQ requests queue (address translation queue)")
246    executeLSQTransfersQueueSize = Param.Unsigned(2,
247        "Size of LSQ transfers queue (memory transaction queue)")
248    executeLSQStoreBufferSize = Param.Unsigned(5,
249        "Size of LSQ store buffer")
250    executeBranchDelay = Param.Cycles(1,
251        "Delay from Execute deciding to branch and Fetch1 reacting"
252        " (1 means next cycle)")
253
254    executeFuncUnits = Param.MinorFUPool(MinorDefaultFUPool(),
255        "FUlines for this processor")
256
257    executeSetTraceTimeOnCommit = Param.Bool(True,
258        "Set inst. trace times to be commit times")
259    executeSetTraceTimeOnIssue = Param.Bool(False,
260        "Set inst. trace times to be issue times")
261
262    executeAllowEarlyMemoryIssue = Param.Bool(True,
263        "Allow mem refs to be issued to the LSQ before reaching the head of"
264        " the in flight insts queue")
265
266    enableIdling = Param.Bool(True,
267        "Enable cycle skipping when the processor is idle\n");
268
269    branchPred = Param.BranchPredictor(TournamentBP(
270        numThreads = Parent.numThreads), "Branch Predictor")
271
272    def addCheckerCpu(self):
273        print "Checker not yet supported by MinorCPU"
274        exit(1)
275