exec_context.hh revision 3468
12SN/A/* 21762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 292665Ssaidi@eecs.umich.edu */ 302SN/A 312SN/A#error "Cannot include this file" 3211793Sbrandon.potter@amd.com 3311793Sbrandon.potter@amd.com/** 344183Sgblack@eecs.umich.edu * The ExecContext is not a usable class. It is simply here for 3512334Sgabeblack@google.com * documentation purposes. It shows the interface that is used by the 368229Snate@binkert.org * ISA to access and change CPU state. 372680Sktlim@umich.edu */ 388232Snate@binkert.orgclass ExecContext { 398229Snate@binkert.org // The register accessor methods provide the index of the 408784Sgblack@eecs.umich.edu // instruction's operand (e.g., 0 or 1), not the architectural 414183Sgblack@eecs.umich.edu // register index, to simplify the implementation of register 422SN/A // renaming. We find the architectural register index by indexing 4310417Sandreas.hansson@arm.com // into the instruction's own operand index table. Note that a 442201SN/A // raw pointer to the StaticInst is provided instead of a 458784Sgblack@eecs.umich.edu // ref-counted StaticInstPtr to reduce overhead. This is fine as 468589Sgblack@eecs.umich.edu // long as these methods don't copy the pointer into any long-term 478589Sgblack@eecs.umich.edu // storage (which is pretty hard to imagine they would have reason 488589Sgblack@eecs.umich.edu // to do). 498589Sgblack@eecs.umich.edu 502201SN/A /** Reads an integer register. */ 512612SN/A uint64_t readIntReg(const StaticInst *si, int idx); 5210417Sandreas.hansson@arm.com 532612SN/A /** Reads a floating point register of a specific width. */ 546815SLisa.Hsu@amd.com FloatReg readFloatReg(const StaticInst *si, int idx, int width); 552612SN/A 565004Sgblack@eecs.umich.edu /** Reads a floating point register of single register width. */ 5710417Sandreas.hansson@arm.com FloatReg readFloatReg(const StaticInst *si, int idx); 588545Ssaidi@eecs.umich.edu 598545Ssaidi@eecs.umich.edu /** Reads a floating point register of a specific width in its 608545Ssaidi@eecs.umich.edu * binary format, instead of by value. */ 618545Ssaidi@eecs.umich.edu FloatRegBits readFloatRegBits(const StaticInst *si, int idx, int width); 6211877Sbrandon.potter@amd.com 6311877Sbrandon.potter@amd.com /** Reads a floating point register in its binary format, instead 6411877Sbrandon.potter@amd.com * of by value. */ 6511877Sbrandon.potter@amd.com FloatRegBits readFloatRegBits(const StaticInst *si, int idx); 6611877Sbrandon.potter@amd.com 6710417Sandreas.hansson@arm.com /** Sets an integer register to a value. */ 684183Sgblack@eecs.umich.edu void setIntReg(const StaticInst *si, int idx, uint64_t val); 698589Sgblack@eecs.umich.edu 708784Sgblack@eecs.umich.edu /** Sets a floating point register of a specific width to a value. */ 718784Sgblack@eecs.umich.edu void setFloatReg(const StaticInst *si, int idx, FloatReg val, int width); 728784Sgblack@eecs.umich.edu 738784Sgblack@eecs.umich.edu /** Sets a floating point register of single width to a value. */ 748589Sgblack@eecs.umich.edu void setFloatReg(const StaticInst *si, int idx, FloatReg val); 754183Sgblack@eecs.umich.edu 764434Ssaidi@eecs.umich.edu /** Sets the bits of a floating point register of a specific width 774183Sgblack@eecs.umich.edu * to a binary value. */ 785004Sgblack@eecs.umich.edu void setFloatRegBits(const StaticInst *si, int idx, 7910417Sandreas.hansson@arm.com FloatRegBits val, int width); 805004Sgblack@eecs.umich.edu 815004Sgblack@eecs.umich.edu /** Sets the bits of a floating point register of single width 825004Sgblack@eecs.umich.edu * to a binary value. */ 83 void setFloatRegBits(const StaticInst *si, int idx, FloatRegBits val); 84 85 /** Reads the PC. */ 86 uint64_t readPC(); 87 /** Reads the NextPC. */ 88 uint64_t readNextPC(); 89 /** Reads the Next-NextPC. Only for architectures like SPARC or MIPS. */ 90 uint64_t readNextNPC(); 91 92 /** Sets the PC. */ 93 void setPC(uint64_t val); 94 /** Sets the NextPC. */ 95 void setNextPC(uint64_t val); 96 /** Sets the Next-NextPC. Only for architectures like SPARC or MIPS. */ 97 void setNextNPC(uint64_t val); 98 99 /** Reads a miscellaneous register. */ 100 MiscReg readMiscReg(int misc_reg); 101 102 /** Reads a miscellaneous register, handling any architectural 103 * side effects due to reading that register. */ 104 MiscReg readMiscRegWithEffect(int misc_reg); 105 106 /** Sets a miscellaneous register. */ 107 void setMiscReg(int misc_reg, const MiscReg &val); 108 109 /** Sets a miscellaneous register, handling any architectural 110 * side effects due to writing that register. */ 111 void setMiscRegWithEffect(int misc_reg, const MiscReg &val); 112 113 /** Records the effective address of the instruction. Only valid 114 * for memory ops. */ 115 void setEA(Addr EA); 116 /** Returns the effective address of the instruction. Only valid 117 * for memory ops. */ 118 Addr getEA(); 119 120 /** Returns a pointer to the ThreadContext. */ 121 ThreadContext *tcBase(); 122 123 /** Reads an address, creating a memory request with the given 124 * flags. Stores result of read in data. */ 125 template <class T> 126 Fault read(Addr addr, T &data, unsigned flags); 127 128 /** Writes to an address, creating a memory request with the given 129 * flags. Writes data to memory. For store conditionals, returns 130 * the result of the store in res. */ 131 template <class T> 132 Fault write(T data, Addr addr, unsigned flags, uint64_t *res); 133 134 /** Prefetches an address, creating a memory request with the 135 * given flags. */ 136 void prefetch(Addr addr, unsigned flags); 137 138 /** Hints to the memory system that an address will be written to 139 * soon, with the given size. Creates a memory request with the 140 * given flags. */ 141 void writeHint(Addr addr, int size, unsigned flags); 142 143#if FULL_SYSTEM 144 /** Somewhat Alpha-specific function that handles returning from 145 * an error or interrupt. */ 146 Fault hwrei(); 147 148 /** 149 * Check for special simulator handling of specific PAL calls. If 150 * return value is false, actual PAL call will be suppressed. 151 */ 152 bool simPalCheck(int palFunc); 153#else 154 /** Executes a syscall specified by the callnum. */ 155 void syscall(int64_t callnum); 156#endif 157}; 158