exec_context.hh revision 3468 
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31#error "Cannot include this file"
32
33/**
34 * The ExecContext is not a usable class.  It is simply here for
35 * documentation purposes.  It shows the interface that is used by the
36 * ISA to access and change CPU state.
37 */
38class ExecContext {
39    // The register accessor methods provide the index of the
40    // instruction's operand (e.g., 0 or 1), not the architectural
41    // register index, to simplify the implementation of register
42    // renaming.  We find the architectural register index by indexing
43    // into the instruction's own operand index table.  Note that a
44    // raw pointer to the StaticInst is provided instead of a
45    // ref-counted StaticInstPtr to reduce overhead.  This is fine as
46    // long as these methods don't copy the pointer into any long-term
47    // storage (which is pretty hard to imagine they would have reason
48    // to do).
49
50    /** Reads an integer register. */
51    uint64_t readIntReg(const StaticInst *si, int idx);
52
53    /** Reads a floating point register of a specific width. */
54    FloatReg readFloatReg(const StaticInst *si, int idx, int width);
55
56    /** Reads a floating point register of single register width. */
57    FloatReg readFloatReg(const StaticInst *si, int idx);
58
59    /** Reads a floating point register of a specific width in its
60     * binary format, instead of by value. */
61    FloatRegBits readFloatRegBits(const StaticInst *si, int idx, int width);
62
63    /** Reads a floating point register in its binary format, instead
64     * of by value. */
65    FloatRegBits readFloatRegBits(const StaticInst *si, int idx);
66
67    /** Sets an integer register to a value. */
68    void setIntReg(const StaticInst *si, int idx, uint64_t val);
69
70    /** Sets a floating point register of a specific width to a value. */
71    void setFloatReg(const StaticInst *si, int idx, FloatReg val, int width);
72
73    /** Sets a floating point register of single width to a value. */
74    void setFloatReg(const StaticInst *si, int idx, FloatReg val);
75
76    /** Sets the bits of a floating point register of a specific width
77     * to a binary value. */
78    void setFloatRegBits(const StaticInst *si, int idx,
79                         FloatRegBits val, int width);
80
81    /** Sets the bits of a floating point register of single width
82     * to a binary value. */
83    void setFloatRegBits(const StaticInst *si, int idx, FloatRegBits val);
84
85    /** Reads the PC. */
86    uint64_t readPC();
87    /** Reads the NextPC. */
88    uint64_t readNextPC();
89    /** Reads the Next-NextPC. Only for architectures like SPARC or MIPS. */
90    uint64_t readNextNPC();
91
92    /** Sets the PC. */
93    void setPC(uint64_t val);
94    /** Sets the NextPC. */
95    void setNextPC(uint64_t val);
96    /** Sets the Next-NextPC.  Only for architectures like SPARC or MIPS. */
97    void setNextNPC(uint64_t val);
98
99    /** Reads a miscellaneous register. */
100    MiscReg readMiscReg(int misc_reg);
101
102    /** Reads a miscellaneous register, handling any architectural
103     * side effects due to reading that register. */
104    MiscReg readMiscRegWithEffect(int misc_reg);
105
106    /** Sets a miscellaneous register. */
107    void setMiscReg(int misc_reg, const MiscReg &val);
108
109    /** Sets a miscellaneous register, handling any architectural
110     * side effects due to writing that register. */
111    void setMiscRegWithEffect(int misc_reg, const MiscReg &val);
112
113    /** Records the effective address of the instruction.  Only valid
114     * for memory ops. */
115    void setEA(Addr EA);
116    /** Returns the effective address of the instruction.  Only valid
117     * for memory ops. */
118    Addr getEA();
119
120    /** Returns a pointer to the ThreadContext. */
121    ThreadContext *tcBase();
122
123    /** Reads an address, creating a memory request with the given
124     * flags.  Stores result of read in data. */
125    template <class T>
126    Fault read(Addr addr, T &data, unsigned flags);
127
128    /** Writes to an address, creating a memory request with the given
129     * flags.  Writes data to memory.  For store conditionals, returns
130     * the result of the store in res. */
131    template <class T>
132    Fault write(T data, Addr addr, unsigned flags, uint64_t *res);
133
134    /** Prefetches an address, creating a memory request with the
135     * given flags. */
136    void prefetch(Addr addr, unsigned flags);
137
138    /** Hints to the memory system that an address will be written to
139     * soon, with the given size.  Creates a memory request with the
140     * given flags. */
141    void writeHint(Addr addr, int size, unsigned flags);
142
143#if FULL_SYSTEM
144    /** Somewhat Alpha-specific function that handles returning from
145     * an error or interrupt. */
146    Fault hwrei();
147
148    /**
149     * Check for special simulator handling of specific PAL calls.  If
150     * return value is false, actual PAL call will be suppressed.
151     */
152    bool simPalCheck(int palFunc);
153#else
154    /** Executes a syscall specified by the callnum. */
155    void syscall(int64_t callnum);
156#endif
157};
158