cpu_impl.hh revision 6658
1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim 29 */ 30 31#include <list> 32#include <string> 33 34#include "base/refcnt.hh" 35#include "config/the_isa.hh" 36#include "cpu/base_dyn_inst.hh" 37#include "cpu/checker/cpu.hh" 38#include "cpu/simple_thread.hh" 39#include "cpu/thread_context.hh" 40#include "cpu/static_inst.hh" 41#include "sim/sim_object.hh" 42#include "sim/stats.hh" 43 44#if FULL_SYSTEM 45#include "arch/vtophys.hh" 46#endif // FULL_SYSTEM 47 48using namespace std; 49//The CheckerCPU does alpha only 50using namespace AlphaISA; 51 52template <class DynInstPtr> 53void 54Checker<DynInstPtr>::verify(DynInstPtr &completed_inst) 55{ 56 DynInstPtr inst; 57 58 // Either check this instruction, or add it to a list of 59 // instructions waiting to be checked. Instructions must be 60 // checked in program order, so if a store has committed yet not 61 // completed, there may be some instructions that are waiting 62 // behind it that have completed and must be checked. 63 if (!instList.empty()) { 64 if (youngestSN < completed_inst->seqNum) { 65 DPRINTF(Checker, "Adding instruction [sn:%lli] PC:%#x to list.\n", 66 completed_inst->seqNum, completed_inst->readPC()); 67 instList.push_back(completed_inst); 68 youngestSN = completed_inst->seqNum; 69 } 70 71 if (!instList.front()->isCompleted()) { 72 return; 73 } else { 74 inst = instList.front(); 75 instList.pop_front(); 76 } 77 } else { 78 if (!completed_inst->isCompleted()) { 79 if (youngestSN < completed_inst->seqNum) { 80 DPRINTF(Checker, "Adding instruction [sn:%lli] PC:%#x to list.\n", 81 completed_inst->seqNum, completed_inst->readPC()); 82 instList.push_back(completed_inst); 83 youngestSN = completed_inst->seqNum; 84 } 85 return; 86 } else { 87 if (youngestSN < completed_inst->seqNum) { 88 inst = completed_inst; 89 youngestSN = completed_inst->seqNum; 90 } else { 91 return; 92 } 93 } 94 } 95 96 unverifiedInst = inst; 97 98 // Try to check all instructions that are completed, ending if we 99 // run out of instructions to check or if an instruction is not 100 // yet completed. 101 while (1) { 102 DPRINTF(Checker, "Processing instruction [sn:%lli] PC:%#x.\n", 103 inst->seqNum, inst->readPC()); 104 unverifiedResult.integer = inst->readIntResult(); 105 unverifiedReq = inst->req; 106 unverifiedMemData = inst->memData; 107 numCycles++; 108 109 Fault fault = NoFault; 110 111 // maintain $r0 semantics 112 thread->setIntReg(ZeroReg, 0); 113#ifdef TARGET_ALPHA 114 thread->setFloatRegDouble(ZeroReg, 0.0); 115#endif // TARGET_ALPHA 116 117 // Check if any recent PC changes match up with anything we 118 // expect to happen. This is mostly to check if traps or 119 // PC-based events have occurred in both the checker and CPU. 120 if (changedPC) { 121 DPRINTF(Checker, "Changed PC recently to %#x\n", 122 thread->readPC()); 123 if (willChangePC) { 124 if (newPC == thread->readPC()) { 125 DPRINTF(Checker, "Changed PC matches expected PC\n"); 126 } else { 127 warn("%lli: Changed PC does not match expected PC, " 128 "changed: %#x, expected: %#x", 129 curTick, thread->readPC(), newPC); 130 CheckerCPU::handleError(); 131 } 132 willChangePC = false; 133 } 134 changedPC = false; 135 } 136 if (changedNextPC) { 137 DPRINTF(Checker, "Changed NextPC recently to %#x\n", 138 thread->readNextPC()); 139 changedNextPC = false; 140 } 141 142 // Try to fetch the instruction 143 144#if FULL_SYSTEM 145#define IFETCH_FLAGS(pc) ((pc) & 1) ? PHYSICAL : 0 146#else 147#define IFETCH_FLAGS(pc) 0 148#endif 149 150 uint64_t fetch_PC = thread->readPC() & ~3; 151 152 // set up memory request for instruction fetch 153 memReq = new Request(inst->threadNumber, fetch_PC, 154 sizeof(uint32_t), 155 IFETCH_FLAGS(thread->readPC()), 156 fetch_PC, thread->contextId(), 157 inst->threadNumber); 158 159 bool succeeded = itb->translateAtomic(memReq, thread); 160 161 if (!succeeded) { 162 if (inst->getFault() == NoFault) { 163 // In this case the instruction was not a dummy 164 // instruction carrying an ITB fault. In the single 165 // threaded case the ITB should still be able to 166 // translate this instruction; in the SMT case it's 167 // possible that its ITB entry was kicked out. 168 warn("%lli: Instruction PC %#x was not found in the ITB!", 169 curTick, thread->readPC()); 170 handleError(inst); 171 172 // go to the next instruction 173 thread->setPC(thread->readNextPC()); 174 thread->setNextPC(thread->readNextPC() + sizeof(MachInst)); 175 176 break; 177 } else { 178 // The instruction is carrying an ITB fault. Handle 179 // the fault and see if our results match the CPU on 180 // the next tick(). 181 fault = inst->getFault(); 182 } 183 } 184 185 if (fault == NoFault) { 186 PacketPtr pkt = new Packet(memReq, Packet::ReadReq, 187 Packet::Broadcast); 188 189 pkt->dataStatic(&machInst); 190 191 icachePort->sendFunctional(pkt); 192 193 delete pkt; 194 195 // keep an instruction count 196 numInst++; 197 198 // decode the instruction 199 machInst = gtoh(machInst); 200 // Checks that the instruction matches what we expected it to be. 201 // Checks both the machine instruction and the PC. 202 validateInst(inst); 203 204#if THE_ISA == ALPHA_ISA 205 curStaticInst = StaticInst::decode(makeExtMI(machInst, 206 thread->readPC())); 207#elif THE_ISA == SPARC_ISA 208 curStaticInst = StaticInst::decode(makeExtMI(machInst, 209 thread->getTC())); 210#endif 211 212#if FULL_SYSTEM 213 thread->setInst(machInst); 214#endif // FULL_SYSTEM 215 216 fault = inst->getFault(); 217 } 218 219 // Discard fetch's memReq. 220 delete memReq; 221 memReq = NULL; 222 223 // Either the instruction was a fault and we should process the fault, 224 // or we should just go ahead execute the instruction. This assumes 225 // that the instruction is properly marked as a fault. 226 if (fault == NoFault) { 227 228 thread->funcExeInst++; 229 230 if (!inst->isUnverifiable()) 231 fault = curStaticInst->execute(this, NULL); 232 233 // Checks to make sure instrution results are correct. 234 validateExecution(inst); 235 236 if (curStaticInst->isLoad()) { 237 ++numLoad; 238 } 239 } 240 241 if (fault != NoFault) { 242#if FULL_SYSTEM 243 fault->invoke(tc); 244 willChangePC = true; 245 newPC = thread->readPC(); 246 DPRINTF(Checker, "Fault, PC is now %#x\n", newPC); 247#endif 248 } else { 249#if THE_ISA != MIPS_ISA 250 // go to the next instruction 251 thread->setPC(thread->readNextPC()); 252 thread->setNextPC(thread->readNextPC() + sizeof(MachInst)); 253#else 254 // go to the next instruction 255 thread->setPC(thread->readNextPC()); 256 thread->setNextPC(thread->readNextNPC()); 257 thread->setNextNPC(thread->readNextNPC() + sizeof(MachInst)); 258#endif 259 260 } 261 262#if FULL_SYSTEM 263 // @todo: Determine if these should happen only if the 264 // instruction hasn't faulted. In the SimpleCPU case this may 265 // not be true, but in the O3 or Ozone case this may be true. 266 Addr oldpc; 267 int count = 0; 268 do { 269 oldpc = thread->readPC(); 270 system->pcEventQueue.service(tc); 271 count++; 272 } while (oldpc != thread->readPC()); 273 if (count > 1) { 274 willChangePC = true; 275 newPC = thread->readPC(); 276 DPRINTF(Checker, "PC Event, PC is now %#x\n", newPC); 277 } 278#endif 279 280 // @todo: Optionally can check all registers. (Or just those 281 // that have been modified). 282 validateState(); 283 284 if (memReq) { 285 delete memReq; 286 memReq = NULL; 287 } 288 289 // Continue verifying instructions if there's another completed 290 // instruction waiting to be verified. 291 if (instList.empty()) { 292 break; 293 } else if (instList.front()->isCompleted()) { 294 inst = instList.front(); 295 instList.pop_front(); 296 } else { 297 break; 298 } 299 } 300 unverifiedInst = NULL; 301} 302 303template <class DynInstPtr> 304void 305Checker<DynInstPtr>::switchOut() 306{ 307 instList.clear(); 308} 309 310template <class DynInstPtr> 311void 312Checker<DynInstPtr>::takeOverFrom(BaseCPU *oldCPU) 313{ 314} 315 316template <class DynInstPtr> 317void 318Checker<DynInstPtr>::validateInst(DynInstPtr &inst) 319{ 320 if (inst->readPC() != thread->readPC()) { 321 warn("%lli: PCs do not match! Inst: %#x, checker: %#x", 322 curTick, inst->readPC(), thread->readPC()); 323 if (changedPC) { 324 warn("%lli: Changed PCs recently, may not be an error", 325 curTick); 326 } else { 327 handleError(inst); 328 } 329 } 330 331 MachInst mi = static_cast<MachInst>(inst->staticInst->machInst); 332 333 if (mi != machInst) { 334 warn("%lli: Binary instructions do not match! Inst: %#x, " 335 "checker: %#x", 336 curTick, mi, machInst); 337 handleError(inst); 338 } 339} 340 341template <class DynInstPtr> 342void 343Checker<DynInstPtr>::validateExecution(DynInstPtr &inst) 344{ 345 bool result_mismatch = false; 346 if (inst->numDestRegs()) { 347 // @todo: Support more destination registers. 348 if (inst->isUnverifiable()) { 349 // Unverifiable instructions assume they were executed 350 // properly by the CPU. Grab the result from the 351 // instruction and write it to the register. 352 copyResult(inst); 353 } else if (result.integer != inst->readIntResult()) { 354 result_mismatch = true; 355 } 356 } 357 358 if (result_mismatch) { 359 warn("%lli: Instruction results do not match! (Values may not " 360 "actually be integers) Inst: %#x, checker: %#x", 361 curTick, inst->readIntResult(), result.integer); 362 363 // It's useful to verify load values from memory, but in MP 364 // systems the value obtained at execute may be different than 365 // the value obtained at completion. Similarly DMA can 366 // present the same problem on even UP systems. Thus there is 367 // the option to only warn on loads having a result error. 368 if (inst->isLoad() && warnOnlyOnLoadError) { 369 copyResult(inst); 370 } else { 371 handleError(inst); 372 } 373 } 374 375 if (inst->readNextPC() != thread->readNextPC()) { 376 warn("%lli: Instruction next PCs do not match! Inst: %#x, " 377 "checker: %#x", 378 curTick, inst->readNextPC(), thread->readNextPC()); 379 handleError(inst); 380 } 381 382 // Checking side effect registers can be difficult if they are not 383 // checked simultaneously with the execution of the instruction. 384 // This is because other valid instructions may have modified 385 // these registers in the meantime, and their values are not 386 // stored within the DynInst. 387 while (!miscRegIdxs.empty()) { 388 int misc_reg_idx = miscRegIdxs.front(); 389 miscRegIdxs.pop(); 390 391 if (inst->tcBase()->readMiscRegNoEffect(misc_reg_idx) != 392 thread->readMiscRegNoEffect(misc_reg_idx)) { 393 warn("%lli: Misc reg idx %i (side effect) does not match! " 394 "Inst: %#x, checker: %#x", 395 curTick, misc_reg_idx, 396 inst->tcBase()->readMiscRegNoEffect(misc_reg_idx), 397 thread->readMiscRegNoEffect(misc_reg_idx)); 398 handleError(inst); 399 } 400 } 401} 402 403template <class DynInstPtr> 404void 405Checker<DynInstPtr>::validateState() 406{ 407 if (updateThisCycle) { 408 warn("%lli: Instruction PC %#x results didn't match up, copying all " 409 "registers from main CPU", curTick, unverifiedInst->readPC()); 410 // Heavy-weight copying of all registers 411 thread->copyArchRegs(unverifiedInst->tcBase()); 412 // Also advance the PC. Hopefully no PC-based events happened. 413#if THE_ISA != MIPS_ISA 414 // go to the next instruction 415 thread->setPC(thread->readNextPC()); 416 thread->setNextPC(thread->readNextPC() + sizeof(MachInst)); 417#else 418 // go to the next instruction 419 thread->setPC(thread->readNextPC()); 420 thread->setNextPC(thread->readNextNPC()); 421 thread->setNextNPC(thread->readNextNPC() + sizeof(MachInst)); 422#endif 423 updateThisCycle = false; 424 } 425} 426 427template <class DynInstPtr> 428void 429Checker<DynInstPtr>::copyResult(DynInstPtr &inst) 430{ 431 RegIndex idx = inst->destRegIdx(0); 432 if (idx < TheISA::FP_Base_DepTag) { 433 thread->setIntReg(idx, inst->readIntResult()); 434 } else if (idx < TheISA::Fpcr_DepTag) { 435 thread->setFloatRegBits(idx, inst->readIntResult()); 436 } else { 437 thread->setMiscRegNoEffect(idx, inst->readIntResult()); 438 } 439} 440 441template <class DynInstPtr> 442void 443Checker<DynInstPtr>::dumpAndExit(DynInstPtr &inst) 444{ 445 cprintf("Error detected, instruction information:\n"); 446 cprintf("PC:%#x, nextPC:%#x\n[sn:%lli]\n[tid:%i]\n" 447 "Completed:%i\n", 448 inst->readPC(), 449 inst->readNextPC(), 450 inst->seqNum, 451 inst->threadNumber, 452 inst->isCompleted()); 453 inst->dump(); 454 CheckerCPU::dumpAndExit(); 455} 456 457template <class DynInstPtr> 458void 459Checker<DynInstPtr>::dumpInsts() 460{ 461 int num = 0; 462 463 InstListIt inst_list_it = --(instList.end()); 464 465 cprintf("Inst list size: %i\n", instList.size()); 466 467 while (inst_list_it != instList.end()) 468 { 469 cprintf("Instruction:%i\n", 470 num); 471 472 cprintf("PC:%#x\n[sn:%lli]\n[tid:%i]\n" 473 "Completed:%i\n", 474 (*inst_list_it)->readPC(), 475 (*inst_list_it)->seqNum, 476 (*inst_list_it)->threadNumber, 477 (*inst_list_it)->isCompleted()); 478 479 cprintf("\n"); 480 481 inst_list_it--; 482 ++num; 483 } 484 485} 486