cpu_impl.hh revision 12109
1/* 2 * Copyright (c) 2011, 2016 ARM Limited 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating 9 * to a hardware implementation of the functionality of the software 10 * licensed hereunder. You may use the software subject to the license 11 * terms below provided that you ensure that this notice is replicated 12 * unmodified and in its entirety in all distributions of the software, 13 * modified or unmodified, in source code or in binary form. 14 * 15 * Copyright (c) 2006 The Regents of The University of Michigan 16 * All rights reserved. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions are 20 * met: redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer; 22 * redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution; 25 * neither the name of the copyright holders nor the names of its 26 * contributors may be used to endorse or promote products derived from 27 * this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 * 41 * Authors: Kevin Lim 42 * Geoffrey Blake 43 */ 44 45#ifndef __CPU_CHECKER_CPU_IMPL_HH__ 46#define __CPU_CHECKER_CPU_IMPL_HH__ 47 48#include <list> 49#include <string> 50 51#include "arch/isa_traits.hh" 52#include "arch/vtophys.hh" 53#include "base/refcnt.hh" 54#include "config/the_isa.hh" 55#include "cpu/base_dyn_inst.hh" 56#include "cpu/exetrace.hh" 57#include "cpu/reg_class.hh" 58#include "cpu/simple_thread.hh" 59#include "cpu/static_inst.hh" 60#include "cpu/thread_context.hh" 61#include "cpu/checker/cpu.hh" 62#include "debug/Checker.hh" 63#include "sim/full_system.hh" 64#include "sim/sim_object.hh" 65#include "sim/stats.hh" 66 67using namespace std; 68using namespace TheISA; 69 70template <class Impl> 71void 72Checker<Impl>::advancePC(const Fault &fault) 73{ 74 if (fault != NoFault) { 75 curMacroStaticInst = StaticInst::nullStaticInstPtr; 76 fault->invoke(tc, curStaticInst); 77 thread->decoder.reset(); 78 } else { 79 if (curStaticInst) { 80 if (curStaticInst->isLastMicroop()) 81 curMacroStaticInst = StaticInst::nullStaticInstPtr; 82 TheISA::PCState pcState = thread->pcState(); 83 TheISA::advancePC(pcState, curStaticInst); 84 thread->pcState(pcState); 85 DPRINTF(Checker, "Advancing PC to %s.\n", thread->pcState()); 86 } 87 } 88} 89////////////////////////////////////////////////// 90 91template <class Impl> 92void 93Checker<Impl>::handlePendingInt() 94{ 95 DPRINTF(Checker, "IRQ detected at PC: %s with %d insts in buffer\n", 96 thread->pcState(), instList.size()); 97 DynInstPtr boundaryInst = NULL; 98 if (!instList.empty()) { 99 // Set the instructions as completed and verify as much as possible. 100 DynInstPtr inst; 101 typename std::list<DynInstPtr>::iterator itr; 102 103 for (itr = instList.begin(); itr != instList.end(); itr++) { 104 (*itr)->setCompleted(); 105 } 106 107 inst = instList.front(); 108 boundaryInst = instList.back(); 109 verify(inst); // verify the instructions 110 inst = NULL; 111 } 112 if ((!boundaryInst && curMacroStaticInst && 113 curStaticInst->isDelayedCommit() && 114 !curStaticInst->isLastMicroop()) || 115 (boundaryInst && boundaryInst->isDelayedCommit() && 116 !boundaryInst->isLastMicroop())) { 117 panic("%lli: Trying to take an interrupt in middle of " 118 "a non-interuptable instruction!", curTick()); 119 } 120 boundaryInst = NULL; 121 thread->decoder.reset(); 122 curMacroStaticInst = StaticInst::nullStaticInstPtr; 123} 124 125template <class Impl> 126void 127Checker<Impl>::verify(DynInstPtr &completed_inst) 128{ 129 DynInstPtr inst; 130 131 // Make sure serializing instructions are actually 132 // seen as serializing to commit. instList should be 133 // empty in these cases. 134 if ((completed_inst->isSerializing() || 135 completed_inst->isSerializeBefore()) && 136 (!instList.empty() ? 137 (instList.front()->seqNum != completed_inst->seqNum) : 0)) { 138 panic("%lli: Instruction sn:%lli at PC %s is serializing before but is" 139 " entering instList with other instructions\n", curTick(), 140 completed_inst->seqNum, completed_inst->pcState()); 141 } 142 143 // Either check this instruction, or add it to a list of 144 // instructions waiting to be checked. Instructions must be 145 // checked in program order, so if a store has committed yet not 146 // completed, there may be some instructions that are waiting 147 // behind it that have completed and must be checked. 148 if (!instList.empty()) { 149 if (youngestSN < completed_inst->seqNum) { 150 DPRINTF(Checker, "Adding instruction [sn:%lli] PC:%s to list\n", 151 completed_inst->seqNum, completed_inst->pcState()); 152 instList.push_back(completed_inst); 153 youngestSN = completed_inst->seqNum; 154 } 155 156 if (!instList.front()->isCompleted()) { 157 return; 158 } else { 159 inst = instList.front(); 160 instList.pop_front(); 161 } 162 } else { 163 if (!completed_inst->isCompleted()) { 164 if (youngestSN < completed_inst->seqNum) { 165 DPRINTF(Checker, "Adding instruction [sn:%lli] PC:%s to list\n", 166 completed_inst->seqNum, completed_inst->pcState()); 167 instList.push_back(completed_inst); 168 youngestSN = completed_inst->seqNum; 169 } 170 return; 171 } else { 172 if (youngestSN < completed_inst->seqNum) { 173 inst = completed_inst; 174 youngestSN = completed_inst->seqNum; 175 } else { 176 return; 177 } 178 } 179 } 180 181 // Make sure a serializing instruction is actually seen as 182 // serializing. instList should be empty here 183 if (inst->isSerializeAfter() && !instList.empty()) { 184 panic("%lli: Instruction sn:%lli at PC %s is serializing after but is" 185 " exiting instList with other instructions\n", curTick(), 186 completed_inst->seqNum, completed_inst->pcState()); 187 } 188 unverifiedInst = inst; 189 inst = NULL; 190 191 // Try to check all instructions that are completed, ending if we 192 // run out of instructions to check or if an instruction is not 193 // yet completed. 194 while (1) { 195 DPRINTF(Checker, "Processing instruction [sn:%lli] PC:%s.\n", 196 unverifiedInst->seqNum, unverifiedInst->pcState()); 197 unverifiedReq = NULL; 198 unverifiedReq = unverifiedInst->reqToVerify; 199 unverifiedMemData = unverifiedInst->memData; 200 // Make sure results queue is empty 201 while (!result.empty()) { 202 result.pop(); 203 } 204 numCycles++; 205 206 Fault fault = NoFault; 207 208 // maintain $r0 semantics 209 thread->setIntReg(ZeroReg, 0); 210#if THE_ISA == ALPHA_ISA 211 thread->setFloatReg(ZeroReg, 0.0); 212#endif 213 214 // Check if any recent PC changes match up with anything we 215 // expect to happen. This is mostly to check if traps or 216 // PC-based events have occurred in both the checker and CPU. 217 if (changedPC) { 218 DPRINTF(Checker, "Changed PC recently to %s\n", 219 thread->pcState()); 220 if (willChangePC) { 221 if (newPCState == thread->pcState()) { 222 DPRINTF(Checker, "Changed PC matches expected PC\n"); 223 } else { 224 warn("%lli: Changed PC does not match expected PC, " 225 "changed: %s, expected: %s", 226 curTick(), thread->pcState(), newPCState); 227 CheckerCPU::handleError(); 228 } 229 willChangePC = false; 230 } 231 changedPC = false; 232 } 233 234 // Try to fetch the instruction 235 uint64_t fetchOffset = 0; 236 bool fetchDone = false; 237 238 while (!fetchDone) { 239 Addr fetch_PC = thread->instAddr(); 240 fetch_PC = (fetch_PC & PCMask) + fetchOffset; 241 242 MachInst machInst; 243 244 // If not in the middle of a macro instruction 245 if (!curMacroStaticInst) { 246 // set up memory request for instruction fetch 247 memReq = new Request(unverifiedInst->threadNumber, fetch_PC, 248 sizeof(MachInst), 249 0, 250 masterId, 251 fetch_PC, thread->contextId()); 252 memReq->setVirt(0, fetch_PC, sizeof(MachInst), 253 Request::INST_FETCH, masterId, thread->instAddr()); 254 255 256 fault = itb->translateFunctional(memReq, tc, BaseTLB::Execute); 257 258 if (fault != NoFault) { 259 if (unverifiedInst->getFault() == NoFault) { 260 // In this case the instruction was not a dummy 261 // instruction carrying an ITB fault. In the single 262 // threaded case the ITB should still be able to 263 // translate this instruction; in the SMT case it's 264 // possible that its ITB entry was kicked out. 265 warn("%lli: Instruction PC %s was not found in the " 266 "ITB!", curTick(), thread->pcState()); 267 handleError(unverifiedInst); 268 269 // go to the next instruction 270 advancePC(NoFault); 271 272 // Give up on an ITB fault.. 273 delete memReq; 274 unverifiedInst = NULL; 275 return; 276 } else { 277 // The instruction is carrying an ITB fault. Handle 278 // the fault and see if our results match the CPU on 279 // the next tick(). 280 fault = unverifiedInst->getFault(); 281 delete memReq; 282 break; 283 } 284 } else { 285 PacketPtr pkt = new Packet(memReq, MemCmd::ReadReq); 286 287 pkt->dataStatic(&machInst); 288 icachePort->sendFunctional(pkt); 289 machInst = gtoh(machInst); 290 291 delete memReq; 292 delete pkt; 293 } 294 } 295 296 if (fault == NoFault) { 297 TheISA::PCState pcState = thread->pcState(); 298 299 if (isRomMicroPC(pcState.microPC())) { 300 fetchDone = true; 301 curStaticInst = 302 microcodeRom.fetchMicroop(pcState.microPC(), NULL); 303 } else if (!curMacroStaticInst) { 304 //We're not in the middle of a macro instruction 305 StaticInstPtr instPtr = nullptr; 306 307 //Predecode, ie bundle up an ExtMachInst 308 //If more fetch data is needed, pass it in. 309 Addr fetchPC = (pcState.instAddr() & PCMask) + fetchOffset; 310 thread->decoder.moreBytes(pcState, fetchPC, machInst); 311 312 //If an instruction is ready, decode it. 313 //Otherwise, we'll have to fetch beyond the 314 //MachInst at the current pc. 315 if (thread->decoder.instReady()) { 316 fetchDone = true; 317 instPtr = thread->decoder.decode(pcState); 318 thread->pcState(pcState); 319 } else { 320 fetchDone = false; 321 fetchOffset += sizeof(TheISA::MachInst); 322 } 323 324 //If we decoded an instruction and it's microcoded, 325 //start pulling out micro ops 326 if (instPtr && instPtr->isMacroop()) { 327 curMacroStaticInst = instPtr; 328 curStaticInst = 329 instPtr->fetchMicroop(pcState.microPC()); 330 } else { 331 curStaticInst = instPtr; 332 } 333 } else { 334 // Read the next micro op from the macro-op 335 curStaticInst = 336 curMacroStaticInst->fetchMicroop(pcState.microPC()); 337 fetchDone = true; 338 } 339 } 340 } 341 // reset decoder on Checker 342 thread->decoder.reset(); 343 344 // Check Checker and CPU get same instruction, and record 345 // any faults the CPU may have had. 346 Fault unverifiedFault; 347 if (fault == NoFault) { 348 unverifiedFault = unverifiedInst->getFault(); 349 350 // Checks that the instruction matches what we expected it to be. 351 // Checks both the machine instruction and the PC. 352 validateInst(unverifiedInst); 353 } 354 355 // keep an instruction count 356 numInst++; 357 358 359 // Either the instruction was a fault and we should process the fault, 360 // or we should just go ahead execute the instruction. This assumes 361 // that the instruction is properly marked as a fault. 362 if (fault == NoFault) { 363 // Execute Checker instruction and trace 364 if (!unverifiedInst->isUnverifiable()) { 365 Trace::InstRecord *traceData = tracer->getInstRecord(curTick(), 366 tc, 367 curStaticInst, 368 pcState(), 369 curMacroStaticInst); 370 fault = curStaticInst->execute(this, traceData); 371 if (traceData) { 372 traceData->dump(); 373 delete traceData; 374 } 375 } 376 377 if (fault == NoFault && unverifiedFault == NoFault) { 378 thread->funcExeInst++; 379 // Checks to make sure instrution results are correct. 380 validateExecution(unverifiedInst); 381 382 if (curStaticInst->isLoad()) { 383 ++numLoad; 384 } 385 } else if (fault != NoFault && unverifiedFault == NoFault) { 386 panic("%lli: sn: %lli at PC: %s took a fault in checker " 387 "but not in driver CPU\n", curTick(), 388 unverifiedInst->seqNum, unverifiedInst->pcState()); 389 } else if (fault == NoFault && unverifiedFault != NoFault) { 390 panic("%lli: sn: %lli at PC: %s took a fault in driver " 391 "CPU but not in checker\n", curTick(), 392 unverifiedInst->seqNum, unverifiedInst->pcState()); 393 } 394 } 395 396 // Take any faults here 397 if (fault != NoFault) { 398 if (FullSystem) { 399 fault->invoke(tc, curStaticInst); 400 willChangePC = true; 401 newPCState = thread->pcState(); 402 DPRINTF(Checker, "Fault, PC is now %s\n", newPCState); 403 curMacroStaticInst = StaticInst::nullStaticInstPtr; 404 } 405 } else { 406 advancePC(fault); 407 } 408 409 if (FullSystem) { 410 // @todo: Determine if these should happen only if the 411 // instruction hasn't faulted. In the SimpleCPU case this may 412 // not be true, but in the O3 case this may be true. 413 Addr oldpc; 414 int count = 0; 415 do { 416 oldpc = thread->instAddr(); 417 system->pcEventQueue.service(tc); 418 count++; 419 } while (oldpc != thread->instAddr()); 420 if (count > 1) { 421 willChangePC = true; 422 newPCState = thread->pcState(); 423 DPRINTF(Checker, "PC Event, PC is now %s\n", newPCState); 424 } 425 } 426 427 // @todo: Optionally can check all registers. (Or just those 428 // that have been modified). 429 validateState(); 430 431 // Continue verifying instructions if there's another completed 432 // instruction waiting to be verified. 433 if (instList.empty()) { 434 break; 435 } else if (instList.front()->isCompleted()) { 436 unverifiedInst = NULL; 437 unverifiedInst = instList.front(); 438 instList.pop_front(); 439 } else { 440 break; 441 } 442 } 443 unverifiedInst = NULL; 444} 445 446template <class Impl> 447void 448Checker<Impl>::switchOut() 449{ 450 instList.clear(); 451} 452 453template <class Impl> 454void 455Checker<Impl>::takeOverFrom(BaseCPU *oldCPU) 456{ 457} 458 459template <class Impl> 460void 461Checker<Impl>::validateInst(DynInstPtr &inst) 462{ 463 if (inst->instAddr() != thread->instAddr()) { 464 warn("%lli: PCs do not match! Inst: %s, checker: %s", 465 curTick(), inst->pcState(), thread->pcState()); 466 if (changedPC) { 467 warn("%lli: Changed PCs recently, may not be an error", 468 curTick()); 469 } else { 470 handleError(inst); 471 } 472 } 473 474 if (curStaticInst != inst->staticInst) { 475 warn("%lli: StaticInstPtrs don't match. (%s, %s).\n", curTick(), 476 curStaticInst->getName(), inst->staticInst->getName()); 477 } 478} 479 480template <class Impl> 481void 482Checker<Impl>::validateExecution(DynInstPtr &inst) 483{ 484 InstResult checker_val; 485 InstResult inst_val; 486 int idx = -1; 487 bool result_mismatch = false; 488 bool scalar_mismatch = false; 489 bool vector_mismatch = false; 490 491 if (inst->isUnverifiable()) { 492 // Unverifiable instructions assume they were executed 493 // properly by the CPU. Grab the result from the 494 // instruction and write it to the register. 495 copyResult(inst, InstResult(0ul, InstResult::ResultType::Scalar), idx); 496 } else if (inst->numDestRegs() > 0 && !result.empty()) { 497 DPRINTF(Checker, "Dest regs %d, number of checker dest regs %d\n", 498 inst->numDestRegs(), result.size()); 499 for (int i = 0; i < inst->numDestRegs() && !result.empty(); i++) { 500 checker_val = result.front(); 501 result.pop(); 502 inst_val = inst->popResult( 503 InstResult(0ul, InstResult::ResultType::Scalar)); 504 if (checker_val != inst_val) { 505 result_mismatch = true; 506 idx = i; 507 scalar_mismatch = checker_val.isScalar(); 508 vector_mismatch = checker_val.isVector(); 509 panic_if(!(scalar_mismatch || vector_mismatch), 510 "Unknown type of result\n"); 511 } 512 } 513 } // Checker CPU checks all the saved results in the dyninst passed by 514 // the cpu model being checked against the saved results present in 515 // the static inst executed in the Checker. Sometimes the number 516 // of saved results differs between the dyninst and static inst, but 517 // this is ok and not a bug. May be worthwhile to try and correct this. 518 519 if (result_mismatch) { 520 if (scalar_mismatch) { 521 warn("%lli: Instruction results (%i) do not match! (Values may" 522 " not actually be integers) Inst: %#x, checker: %#x", 523 curTick(), idx, inst_val.asIntegerNoAssert(), 524 checker_val.asInteger()); 525 } 526 527 // It's useful to verify load values from memory, but in MP 528 // systems the value obtained at execute may be different than 529 // the value obtained at completion. Similarly DMA can 530 // present the same problem on even UP systems. Thus there is 531 // the option to only warn on loads having a result error. 532 // The load/store queue in Detailed CPU can also cause problems 533 // if load/store forwarding is allowed. 534 if (inst->isLoad() && warnOnlyOnLoadError) { 535 copyResult(inst, inst_val, idx); 536 } else { 537 handleError(inst); 538 } 539 } 540 541 if (inst->nextInstAddr() != thread->nextInstAddr()) { 542 warn("%lli: Instruction next PCs do not match! Inst: %#x, " 543 "checker: %#x", 544 curTick(), inst->nextInstAddr(), thread->nextInstAddr()); 545 handleError(inst); 546 } 547 548 // Checking side effect registers can be difficult if they are not 549 // checked simultaneously with the execution of the instruction. 550 // This is because other valid instructions may have modified 551 // these registers in the meantime, and their values are not 552 // stored within the DynInst. 553 while (!miscRegIdxs.empty()) { 554 int misc_reg_idx = miscRegIdxs.front(); 555 miscRegIdxs.pop(); 556 557 if (inst->tcBase()->readMiscRegNoEffect(misc_reg_idx) != 558 thread->readMiscRegNoEffect(misc_reg_idx)) { 559 warn("%lli: Misc reg idx %i (side effect) does not match! " 560 "Inst: %#x, checker: %#x", 561 curTick(), misc_reg_idx, 562 inst->tcBase()->readMiscRegNoEffect(misc_reg_idx), 563 thread->readMiscRegNoEffect(misc_reg_idx)); 564 handleError(inst); 565 } 566 } 567} 568 569 570// This function is weird, if it is called it means the Checker and 571// O3 have diverged, so panic is called for now. It may be useful 572// to resynch states and continue if the divergence is a false positive 573template <class Impl> 574void 575Checker<Impl>::validateState() 576{ 577 if (updateThisCycle) { 578 // Change this back to warn if divergences end up being false positives 579 panic("%lli: Instruction PC %#x results didn't match up, copying all " 580 "registers from main CPU", curTick(), unverifiedInst->instAddr()); 581 582 // Terribly convoluted way to make sure O3 model does not implode 583 bool no_squash_from_TC = unverifiedInst->thread->noSquashFromTC; 584 unverifiedInst->thread->noSquashFromTC = true; 585 586 // Heavy-weight copying of all registers 587 thread->copyArchRegs(unverifiedInst->tcBase()); 588 unverifiedInst->thread->noSquashFromTC = no_squash_from_TC; 589 590 // Set curStaticInst to unverifiedInst->staticInst 591 curStaticInst = unverifiedInst->staticInst; 592 // Also advance the PC. Hopefully no PC-based events happened. 593 advancePC(NoFault); 594 updateThisCycle = false; 595 } 596} 597 598template <class Impl> 599void 600Checker<Impl>::copyResult(DynInstPtr &inst, const InstResult& mismatch_val, 601 int start_idx) 602{ 603 // We've already popped one dest off the queue, 604 // so do the fix-up then start with the next dest reg; 605 if (start_idx >= 0) { 606 const RegId& idx = inst->destRegIdx(start_idx); 607 switch (idx.classValue()) { 608 case IntRegClass: 609 panic_if(!mismatch_val.isScalar(), "Unexpected type of result"); 610 thread->setIntReg(idx.index(), mismatch_val.asInteger()); 611 break; 612 case FloatRegClass: 613 panic_if(!mismatch_val.isScalar(), "Unexpected type of result"); 614 thread->setFloatRegBits(idx.index(), mismatch_val.asInteger()); 615 break; 616 case VecRegClass: 617 panic_if(!mismatch_val.isVector(), "Unexpected type of result"); 618 thread->setVecReg(idx, mismatch_val.asVector()); 619 break; 620 case VecElemClass: 621 panic_if(!mismatch_val.isVecElem(), 622 "Unexpected type of result"); 623 thread->setVecElem(idx, mismatch_val.asVectorElem()); 624 break; 625 case CCRegClass: 626 panic_if(!mismatch_val.isScalar(), "Unexpected type of result"); 627 thread->setCCReg(idx.index(), mismatch_val.asInteger()); 628 break; 629 case MiscRegClass: 630 panic_if(!mismatch_val.isScalar(), "Unexpected type of result"); 631 thread->setMiscReg(idx.index(), mismatch_val.asInteger()); 632 break; 633 default: 634 panic("Unknown register class: %d", (int)idx.classValue()); 635 } 636 } 637 start_idx++; 638 InstResult res; 639 for (int i = start_idx; i < inst->numDestRegs(); i++) { 640 const RegId& idx = inst->destRegIdx(i); 641 res = inst->popResult(); 642 switch (idx.classValue()) { 643 case IntRegClass: 644 panic_if(!res.isScalar(), "Unexpected type of result"); 645 thread->setIntReg(idx.index(), res.asInteger()); 646 break; 647 case FloatRegClass: 648 panic_if(!res.isScalar(), "Unexpected type of result"); 649 thread->setFloatRegBits(idx.index(), res.asInteger()); 650 break; 651 case VecRegClass: 652 panic_if(!res.isVector(), "Unexpected type of result"); 653 thread->setVecReg(idx, res.asVector()); 654 break; 655 case VecElemClass: 656 panic_if(!res.isVecElem(), "Unexpected type of result"); 657 thread->setVecElem(idx, res.asVectorElem()); 658 break; 659 case CCRegClass: 660 panic_if(!res.isScalar(), "Unexpected type of result"); 661 thread->setCCReg(idx.index(), res.asInteger()); 662 break; 663 case MiscRegClass: 664 panic_if(res.isValid(), "MiscReg expecting invalid result"); 665 // Try to get the proper misc register index for ARM here... 666 thread->setMiscReg(idx.index(), 0); 667 break; 668 // else Register is out of range... 669 default: 670 panic("Unknown register class: %d", (int)idx.classValue()); 671 } 672 } 673} 674 675template <class Impl> 676void 677Checker<Impl>::dumpAndExit(DynInstPtr &inst) 678{ 679 cprintf("Error detected, instruction information:\n"); 680 cprintf("PC:%s, nextPC:%#x\n[sn:%lli]\n[tid:%i]\n" 681 "Completed:%i\n", 682 inst->pcState(), 683 inst->nextInstAddr(), 684 inst->seqNum, 685 inst->threadNumber, 686 inst->isCompleted()); 687 inst->dump(); 688 CheckerCPU::dumpAndExit(); 689} 690 691template <class Impl> 692void 693Checker<Impl>::dumpInsts() 694{ 695 int num = 0; 696 697 InstListIt inst_list_it = --(instList.end()); 698 699 cprintf("Inst list size: %i\n", instList.size()); 700 701 while (inst_list_it != instList.end()) 702 { 703 cprintf("Instruction:%i\n", 704 num); 705 706 cprintf("PC:%s\n[sn:%lli]\n[tid:%i]\n" 707 "Completed:%i\n", 708 (*inst_list_it)->pcState(), 709 (*inst_list_it)->seqNum, 710 (*inst_list_it)->threadNumber, 711 (*inst_list_it)->isCompleted()); 712 713 cprintf("\n"); 714 715 inst_list_it--; 716 ++num; 717 } 718 719} 720 721#endif//__CPU_CHECKER_CPU_IMPL_HH__ 722