cpu.hh revision 9023
12315SN/A/* 28733Sgeoffrey.blake@arm.com * Copyright (c) 2011 ARM Limited 38733Sgeoffrey.blake@arm.com * All rights reserved 48733Sgeoffrey.blake@arm.com * 58733Sgeoffrey.blake@arm.com * The license below extends only to copyright in the software and shall 68733Sgeoffrey.blake@arm.com * not be construed as granting a license to any other intellectual 78733Sgeoffrey.blake@arm.com * property including but not limited to intellectual property relating 88733Sgeoffrey.blake@arm.com * to a hardware implementation of the functionality of the software 98733Sgeoffrey.blake@arm.com * licensed hereunder. You may use the software subject to the license 108733Sgeoffrey.blake@arm.com * terms below provided that you ensure that this notice is replicated 118733Sgeoffrey.blake@arm.com * unmodified and in its entirety in all distributions of the software, 128733Sgeoffrey.blake@arm.com * modified or unmodified, in source code or in binary form. 138733Sgeoffrey.blake@arm.com * 142332SN/A * Copyright (c) 2006 The Regents of The University of Michigan 152315SN/A * All rights reserved. 162315SN/A * 172315SN/A * Redistribution and use in source and binary forms, with or without 182315SN/A * modification, are permitted provided that the following conditions are 192315SN/A * met: redistributions of source code must retain the above copyright 202315SN/A * notice, this list of conditions and the following disclaimer; 212315SN/A * redistributions in binary form must reproduce the above copyright 222315SN/A * notice, this list of conditions and the following disclaimer in the 232315SN/A * documentation and/or other materials provided with the distribution; 242315SN/A * neither the name of the copyright holders nor the names of its 252315SN/A * contributors may be used to endorse or promote products derived from 262315SN/A * this software without specific prior written permission. 272315SN/A * 282315SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292315SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302315SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312315SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322315SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332315SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342315SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352315SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362315SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372315SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382315SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392689Sktlim@umich.edu * 402689Sktlim@umich.edu * Authors: Kevin Lim 412315SN/A */ 422315SN/A 432315SN/A#ifndef __CPU_CHECKER_CPU_HH__ 442315SN/A#define __CPU_CHECKER_CPU_HH__ 452315SN/A 462315SN/A#include <list> 478229Snate@binkert.org#include <map> 482315SN/A#include <queue> 492315SN/A 502669Sktlim@umich.edu#include "arch/types.hh" 512315SN/A#include "base/statistics.hh" 522315SN/A#include "cpu/base.hh" 532315SN/A#include "cpu/base_dyn_inst.hh" 548229Snate@binkert.org#include "cpu/pc_event.hh" 552683Sktlim@umich.edu#include "cpu/simple_thread.hh" 562315SN/A#include "cpu/static_inst.hh" 578733Sgeoffrey.blake@arm.com#include "debug/Checker.hh" 588733Sgeoffrey.blake@arm.com#include "params/CheckerCPU.hh" 592315SN/A#include "sim/eventq.hh" 602315SN/A 612315SN/A// forward declarations 623468Sgblack@eecs.umich.edunamespace TheISA 633468Sgblack@eecs.umich.edu{ 646022Sgblack@eecs.umich.edu class TLB; 653468Sgblack@eecs.umich.edu} 662315SN/A 672315SN/Atemplate <class> 682315SN/Aclass BaseDynInst; 692680Sktlim@umich.educlass ThreadContext; 702669Sktlim@umich.educlass Request; 712315SN/A 722350SN/A/** 732350SN/A * CheckerCPU class. Dynamically verifies instructions as they are 742350SN/A * completed by making sure that the instruction and its results match 752350SN/A * the independent execution of the benchmark inside the checker. The 762350SN/A * checker verifies instructions in order, regardless of the order in 772350SN/A * which instructions complete. There are certain results that can 782350SN/A * not be verified, specifically the result of a store conditional or 792350SN/A * the values of uncached accesses. In these cases, and with 802350SN/A * instructions marked as "IsUnverifiable", the checker assumes that 812350SN/A * the value from the main CPU's execution is correct and simply 822680Sktlim@umich.edu * copies that value. It provides a CheckerThreadContext (see 832683Sktlim@umich.edu * checker/thread_context.hh) that provides hooks for updating the 842680Sktlim@umich.edu * Checker's state through any ThreadContext accesses. This allows the 852350SN/A * checker to be able to correctly verify instructions, even with 862680Sktlim@umich.edu * external accesses to the ThreadContext that change state. 872350SN/A */ 882315SN/Aclass CheckerCPU : public BaseCPU 892315SN/A{ 902315SN/A protected: 912315SN/A typedef TheISA::MachInst MachInst; 922669Sktlim@umich.edu typedef TheISA::FloatReg FloatReg; 932669Sktlim@umich.edu typedef TheISA::FloatRegBits FloatRegBits; 942315SN/A typedef TheISA::MiscReg MiscReg; 958832SAli.Saidi@ARM.com 968832SAli.Saidi@ARM.com /** id attached to all issued requests */ 978832SAli.Saidi@ARM.com MasterID masterId; 982315SN/A public: 992315SN/A virtual void init(); 1002315SN/A 1012315SN/A public: 1025529Snate@binkert.org typedef CheckerCPUParams Params; 1035529Snate@binkert.org const Params *params() const 1048733Sgeoffrey.blake@arm.com { return reinterpret_cast<const Params *>(_params); } 1052315SN/A CheckerCPU(Params *p); 1062315SN/A virtual ~CheckerCPU(); 1072315SN/A 1088733Sgeoffrey.blake@arm.com std::vector<Process*> workload; 1092679Sktlim@umich.edu 1102315SN/A void setSystem(System *system); 1112315SN/A 1122315SN/A System *systemPtr; 1132679Sktlim@umich.edu 1148887Sgeoffrey.blake@arm.com void setIcachePort(CpuPort *icache_port); 1152679Sktlim@umich.edu 1168887Sgeoffrey.blake@arm.com CpuPort *icachePort; 1172679Sktlim@umich.edu 1188887Sgeoffrey.blake@arm.com void setDcachePort(CpuPort *dcache_port); 1192679Sktlim@umich.edu 1208887Sgeoffrey.blake@arm.com CpuPort *dcachePort; 1218887Sgeoffrey.blake@arm.com 1228887Sgeoffrey.blake@arm.com CpuPort &getDataPort() 1238887Sgeoffrey.blake@arm.com { 1248887Sgeoffrey.blake@arm.com panic("Not supported on checker!"); 1258887Sgeoffrey.blake@arm.com return *dcachePort; 1268887Sgeoffrey.blake@arm.com } 1278887Sgeoffrey.blake@arm.com 1288887Sgeoffrey.blake@arm.com CpuPort &getInstPort() 1298887Sgeoffrey.blake@arm.com { 1308887Sgeoffrey.blake@arm.com panic("Not supported on checker!"); 1318887Sgeoffrey.blake@arm.com return *icachePort; 1328887Sgeoffrey.blake@arm.com } 1332679Sktlim@umich.edu 1342315SN/A public: 1352683Sktlim@umich.edu // Primary thread being run. 1362683Sktlim@umich.edu SimpleThread *thread; 1372315SN/A 1382680Sktlim@umich.edu ThreadContext *tc; 1392315SN/A 1406022Sgblack@eecs.umich.edu TheISA::TLB *itb; 1416022Sgblack@eecs.umich.edu TheISA::TLB *dtb; 1422315SN/A 1432315SN/A Addr dbg_vtophys(Addr addr); 1442315SN/A 1452315SN/A union Result { 1462315SN/A uint64_t integer; 1472315SN/A double dbl; 1488733Sgeoffrey.blake@arm.com void set(uint64_t i) { integer = i; } 1498733Sgeoffrey.blake@arm.com void set(double d) { dbl = d; } 1508733Sgeoffrey.blake@arm.com void get(uint64_t& i) { i = integer; } 1518733Sgeoffrey.blake@arm.com void get(double& d) { d = dbl; } 1522315SN/A }; 1532315SN/A 1548733Sgeoffrey.blake@arm.com // ISAs like ARM can have multiple destination registers to check, 1558733Sgeoffrey.blake@arm.com // keep them all in a std::queue 1568733Sgeoffrey.blake@arm.com std::queue<Result> result; 1572315SN/A 1582679Sktlim@umich.edu // Pointer to the one memory request. 1592679Sktlim@umich.edu RequestPtr memReq; 1602315SN/A 1612315SN/A StaticInstPtr curStaticInst; 1628733Sgeoffrey.blake@arm.com StaticInstPtr curMacroStaticInst; 1632315SN/A 1642315SN/A // number of simulated instructions 1652315SN/A Counter numInst; 1662315SN/A Counter startNumInst; 1672315SN/A 1682315SN/A std::queue<int> miscRegIdxs; 1692315SN/A 1708733Sgeoffrey.blake@arm.com TheISA::TLB* getITBPtr() { return itb; } 1718733Sgeoffrey.blake@arm.com TheISA::TLB* getDTBPtr() { return dtb; } 1728733Sgeoffrey.blake@arm.com 1738887Sgeoffrey.blake@arm.com virtual Counter totalInsts() const 1748887Sgeoffrey.blake@arm.com { 1758887Sgeoffrey.blake@arm.com return 0; 1768887Sgeoffrey.blake@arm.com } 1778887Sgeoffrey.blake@arm.com 1788887Sgeoffrey.blake@arm.com virtual Counter totalOps() const 1792315SN/A { 1802930Sktlim@umich.edu return 0; 1812315SN/A } 1822315SN/A 1832315SN/A // number of simulated loads 1842315SN/A Counter numLoad; 1852315SN/A Counter startNumLoad; 1862315SN/A 1872315SN/A virtual void serialize(std::ostream &os); 1882315SN/A virtual void unserialize(Checkpoint *cp, const std::string §ion); 1892315SN/A 1902315SN/A // These functions are only used in CPU models that split 1912315SN/A // effective address computation from the actual memory access. 1922315SN/A void setEA(Addr EA) { panic("SimpleCPU::setEA() not implemented\n"); } 1935543Ssaidi@eecs.umich.edu Addr getEA() { panic("SimpleCPU::getEA() not implemented\n"); } 1942315SN/A 1952315SN/A // The register accessor methods provide the index of the 1962315SN/A // instruction's operand (e.g., 0 or 1), not the architectural 1972315SN/A // register index, to simplify the implementation of register 1982315SN/A // renaming. We find the architectural register index by indexing 1992315SN/A // into the instruction's own operand index table. Note that a 2002315SN/A // raw pointer to the StaticInst is provided instead of a 2012315SN/A // ref-counted StaticInstPtr to redice overhead. This is fine as 2022315SN/A // long as these methods don't copy the pointer into any long-term 2032315SN/A // storage (which is pretty hard to imagine they would have reason 2042315SN/A // to do). 2052315SN/A 2063735Sstever@eecs.umich.edu uint64_t readIntRegOperand(const StaticInst *si, int idx) 2072315SN/A { 2082683Sktlim@umich.edu return thread->readIntReg(si->srcRegIdx(idx)); 2092315SN/A } 2102315SN/A 2113735Sstever@eecs.umich.edu FloatReg readFloatRegOperand(const StaticInst *si, int idx) 2122315SN/A { 2132315SN/A int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; 2142683Sktlim@umich.edu return thread->readFloatReg(reg_idx); 2152315SN/A } 2162315SN/A 2173735Sstever@eecs.umich.edu FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx) 2182669Sktlim@umich.edu { 2192669Sktlim@umich.edu int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; 2202683Sktlim@umich.edu return thread->readFloatRegBits(reg_idx); 2212315SN/A } 2222315SN/A 2238733Sgeoffrey.blake@arm.com template <class T> 2248733Sgeoffrey.blake@arm.com void setResult(T t) 2258733Sgeoffrey.blake@arm.com { 2268733Sgeoffrey.blake@arm.com Result instRes; 2278733Sgeoffrey.blake@arm.com instRes.set(t); 2288733Sgeoffrey.blake@arm.com result.push(instRes); 2298733Sgeoffrey.blake@arm.com } 2308733Sgeoffrey.blake@arm.com 2313735Sstever@eecs.umich.edu void setIntRegOperand(const StaticInst *si, int idx, uint64_t val) 2322315SN/A { 2332683Sktlim@umich.edu thread->setIntReg(si->destRegIdx(idx), val); 2348733Sgeoffrey.blake@arm.com setResult<uint64_t>(val); 2352315SN/A } 2362315SN/A 2373735Sstever@eecs.umich.edu void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val) 2382669Sktlim@umich.edu { 2392669Sktlim@umich.edu int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; 2402683Sktlim@umich.edu thread->setFloatReg(reg_idx, val); 2418733Sgeoffrey.blake@arm.com setResult<double>(val); 2422315SN/A } 2432315SN/A 2443735Sstever@eecs.umich.edu void setFloatRegOperandBits(const StaticInst *si, int idx, 2453735Sstever@eecs.umich.edu FloatRegBits val) 2462315SN/A { 2472315SN/A int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; 2482683Sktlim@umich.edu thread->setFloatRegBits(reg_idx, val); 2498733Sgeoffrey.blake@arm.com setResult<uint64_t>(val); 2502315SN/A } 2512315SN/A 2528733Sgeoffrey.blake@arm.com bool readPredicate() { return thread->readPredicate(); } 2538733Sgeoffrey.blake@arm.com void setPredicate(bool val) 2548733Sgeoffrey.blake@arm.com { 2558733Sgeoffrey.blake@arm.com thread->setPredicate(val); 2568733Sgeoffrey.blake@arm.com } 2572669Sktlim@umich.edu 2588733Sgeoffrey.blake@arm.com TheISA::PCState pcState() { return thread->pcState(); } 2598733Sgeoffrey.blake@arm.com void pcState(const TheISA::PCState &val) 2608733Sgeoffrey.blake@arm.com { 2618733Sgeoffrey.blake@arm.com DPRINTF(Checker, "Changing PC to %s, old PC %s.\n", 2628733Sgeoffrey.blake@arm.com val, thread->pcState()); 2638733Sgeoffrey.blake@arm.com thread->pcState(val); 2648733Sgeoffrey.blake@arm.com } 2658733Sgeoffrey.blake@arm.com Addr instAddr() { return thread->instAddr(); } 2668733Sgeoffrey.blake@arm.com Addr nextInstAddr() { return thread->nextInstAddr(); } 2678733Sgeoffrey.blake@arm.com MicroPC microPC() { return thread->microPC(); } 2688733Sgeoffrey.blake@arm.com ////////////////////////////////////////// 2692315SN/A 2704172Ssaidi@eecs.umich.edu MiscReg readMiscRegNoEffect(int misc_reg) 2714172Ssaidi@eecs.umich.edu { 2724172Ssaidi@eecs.umich.edu return thread->readMiscRegNoEffect(misc_reg); 2734172Ssaidi@eecs.umich.edu } 2744172Ssaidi@eecs.umich.edu 2752315SN/A MiscReg readMiscReg(int misc_reg) 2762315SN/A { 2772683Sktlim@umich.edu return thread->readMiscReg(misc_reg); 2782315SN/A } 2792315SN/A 2804172Ssaidi@eecs.umich.edu void setMiscRegNoEffect(int misc_reg, const MiscReg &val) 2812315SN/A { 2824172Ssaidi@eecs.umich.edu miscRegIdxs.push(misc_reg); 2834172Ssaidi@eecs.umich.edu return thread->setMiscRegNoEffect(misc_reg, val); 2842315SN/A } 2852315SN/A 2863468Sgblack@eecs.umich.edu void setMiscReg(int misc_reg, const MiscReg &val) 2872315SN/A { 2882315SN/A miscRegIdxs.push(misc_reg); 2892683Sktlim@umich.edu return thread->setMiscReg(misc_reg, val); 2902315SN/A } 2912315SN/A 2928733Sgeoffrey.blake@arm.com MiscReg readMiscRegOperand(const StaticInst *si, int idx) 2938733Sgeoffrey.blake@arm.com { 2948733Sgeoffrey.blake@arm.com int reg_idx = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag; 2958733Sgeoffrey.blake@arm.com return thread->readMiscReg(reg_idx); 2968733Sgeoffrey.blake@arm.com } 2978733Sgeoffrey.blake@arm.com 2988733Sgeoffrey.blake@arm.com void setMiscRegOperand( 2998733Sgeoffrey.blake@arm.com const StaticInst *si, int idx, const MiscReg &val) 3008733Sgeoffrey.blake@arm.com { 3018733Sgeoffrey.blake@arm.com int reg_idx = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag; 3028733Sgeoffrey.blake@arm.com return thread->setMiscReg(reg_idx, val); 3038733Sgeoffrey.blake@arm.com } 3048888Sgeoffrey.blake@arm.com 3058888Sgeoffrey.blake@arm.com#if THE_ISA == MIPS_ISA 3068888Sgeoffrey.blake@arm.com uint64_t readRegOtherThread(int misc_reg) 3078888Sgeoffrey.blake@arm.com { 3088888Sgeoffrey.blake@arm.com panic("MIPS MT not defined for CheckerCPU.\n"); 3098888Sgeoffrey.blake@arm.com return 0; 3108888Sgeoffrey.blake@arm.com } 3118888Sgeoffrey.blake@arm.com 3128888Sgeoffrey.blake@arm.com void setRegOtherThread(int misc_reg, const TheISA::MiscReg &val) 3138888Sgeoffrey.blake@arm.com { 3148888Sgeoffrey.blake@arm.com panic("MIPS MT not defined for CheckerCPU.\n"); 3158888Sgeoffrey.blake@arm.com } 3168888Sgeoffrey.blake@arm.com#endif 3178888Sgeoffrey.blake@arm.com 3188733Sgeoffrey.blake@arm.com ///////////////////////////////////////// 3198733Sgeoffrey.blake@arm.com 3208733Sgeoffrey.blake@arm.com void recordPCChange(const TheISA::PCState &val) 3218733Sgeoffrey.blake@arm.com { 3228733Sgeoffrey.blake@arm.com changedPC = true; 3238733Sgeoffrey.blake@arm.com newPCState = val; 3248733Sgeoffrey.blake@arm.com } 3252315SN/A 3265358Sgblack@eecs.umich.edu void demapPage(Addr vaddr, uint64_t asn) 3275358Sgblack@eecs.umich.edu { 3285358Sgblack@eecs.umich.edu this->itb->demapPage(vaddr, asn); 3295358Sgblack@eecs.umich.edu this->dtb->demapPage(vaddr, asn); 3305358Sgblack@eecs.umich.edu } 3315358Sgblack@eecs.umich.edu 3325358Sgblack@eecs.umich.edu void demapInstPage(Addr vaddr, uint64_t asn) 3335358Sgblack@eecs.umich.edu { 3345358Sgblack@eecs.umich.edu this->itb->demapPage(vaddr, asn); 3355358Sgblack@eecs.umich.edu } 3365358Sgblack@eecs.umich.edu 3375358Sgblack@eecs.umich.edu void demapDataPage(Addr vaddr, uint64_t asn) 3385358Sgblack@eecs.umich.edu { 3395358Sgblack@eecs.umich.edu this->dtb->demapPage(vaddr, asn); 3405358Sgblack@eecs.umich.edu } 3415358Sgblack@eecs.umich.edu 3428733Sgeoffrey.blake@arm.com Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags); 3438733Sgeoffrey.blake@arm.com Fault writeMem(uint8_t *data, unsigned size, 3448733Sgeoffrey.blake@arm.com Addr addr, unsigned flags, uint64_t *res); 3458733Sgeoffrey.blake@arm.com 3468733Sgeoffrey.blake@arm.com void setStCondFailures(unsigned sc_failures) 3478733Sgeoffrey.blake@arm.com {} 3488733Sgeoffrey.blake@arm.com ///////////////////////////////////////////////////// 3498733Sgeoffrey.blake@arm.com 3505702Ssaidi@eecs.umich.edu Fault hwrei() { return thread->hwrei(); } 3515702Ssaidi@eecs.umich.edu bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); } 3528733Sgeoffrey.blake@arm.com void wakeup() { } 3532315SN/A // Assume that the normal CPU's call to syscall was successful. 3542332SN/A // The checker's state would have already been updated by the syscall. 3552669Sktlim@umich.edu void syscall(uint64_t callnum) { } 3562315SN/A 3572315SN/A void handleError() 3582315SN/A { 3592315SN/A if (exitOnError) 3602732Sktlim@umich.edu dumpAndExit(); 3612315SN/A } 3622732Sktlim@umich.edu 3638733Sgeoffrey.blake@arm.com bool checkFlags(Request *unverified_req, Addr vAddr, 3648733Sgeoffrey.blake@arm.com Addr pAddr, int flags); 3652315SN/A 3662732Sktlim@umich.edu void dumpAndExit(); 3672732Sktlim@umich.edu 3682680Sktlim@umich.edu ThreadContext *tcBase() { return tc; } 3692683Sktlim@umich.edu SimpleThread *threadBase() { return thread; } 3702315SN/A 3712315SN/A Result unverifiedResult; 3722669Sktlim@umich.edu Request *unverifiedReq; 3732679Sktlim@umich.edu uint8_t *unverifiedMemData; 3742315SN/A 3752315SN/A bool changedPC; 3762315SN/A bool willChangePC; 3778733Sgeoffrey.blake@arm.com TheISA::PCState newPCState; 3782315SN/A bool changedNextPC; 3792315SN/A bool exitOnError; 3802354SN/A bool updateOnError; 3812732Sktlim@umich.edu bool warnOnlyOnLoadError; 3822315SN/A 3832315SN/A InstSeqNum youngestSN; 3842315SN/A}; 3852315SN/A 3862350SN/A/** 3872350SN/A * Templated Checker class. This Checker class is templated on the 3882350SN/A * DynInstPtr of the instruction type that will be verified. Proper 3892350SN/A * template instantiations of the Checker must be placed at the bottom 3902350SN/A * of checker/cpu.cc. 3912350SN/A */ 3928733Sgeoffrey.blake@arm.comtemplate <class Impl> 3932315SN/Aclass Checker : public CheckerCPU 3942315SN/A{ 3958733Sgeoffrey.blake@arm.com private: 3968733Sgeoffrey.blake@arm.com typedef typename Impl::DynInstPtr DynInstPtr; 3978733Sgeoffrey.blake@arm.com 3982315SN/A public: 3992315SN/A Checker(Params *p) 4009023Sgblack@eecs.umich.edu : CheckerCPU(p), updateThisCycle(false), unverifiedInst(NULL) 4012315SN/A { } 4022315SN/A 4032840Sktlim@umich.edu void switchOut(); 4042315SN/A void takeOverFrom(BaseCPU *oldCPU); 4052315SN/A 4068733Sgeoffrey.blake@arm.com void advancePC(Fault fault); 4078733Sgeoffrey.blake@arm.com 4082732Sktlim@umich.edu void verify(DynInstPtr &inst); 4092315SN/A 4102315SN/A void validateInst(DynInstPtr &inst); 4112315SN/A void validateExecution(DynInstPtr &inst); 4122315SN/A void validateState(); 4132315SN/A 4148733Sgeoffrey.blake@arm.com void copyResult(DynInstPtr &inst, uint64_t mismatch_val, int start_idx); 4158733Sgeoffrey.blake@arm.com void handlePendingInt(); 4162732Sktlim@umich.edu 4172732Sktlim@umich.edu private: 4182732Sktlim@umich.edu void handleError(DynInstPtr &inst) 4192732Sktlim@umich.edu { 4202360SN/A if (exitOnError) { 4212732Sktlim@umich.edu dumpAndExit(inst); 4222360SN/A } else if (updateOnError) { 4232354SN/A updateThisCycle = true; 4242360SN/A } 4252732Sktlim@umich.edu } 4262732Sktlim@umich.edu 4272732Sktlim@umich.edu void dumpAndExit(DynInstPtr &inst); 4282732Sktlim@umich.edu 4292354SN/A bool updateThisCycle; 4302354SN/A 4312354SN/A DynInstPtr unverifiedInst; 4322354SN/A 4332315SN/A std::list<DynInstPtr> instList; 4342315SN/A typedef typename std::list<DynInstPtr>::iterator InstListIt; 4352315SN/A void dumpInsts(); 4362315SN/A}; 4372315SN/A 4382315SN/A#endif // __CPU_CHECKER_CPU_HH__ 439