cpu.hh revision 9023
1/* 2 * Copyright (c) 2011 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2006 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Kevin Lim 41 */ 42 43#ifndef __CPU_CHECKER_CPU_HH__ 44#define __CPU_CHECKER_CPU_HH__ 45 46#include <list> 47#include <map> 48#include <queue> 49 50#include "arch/types.hh" 51#include "base/statistics.hh" 52#include "cpu/base.hh" 53#include "cpu/base_dyn_inst.hh" 54#include "cpu/pc_event.hh" 55#include "cpu/simple_thread.hh" 56#include "cpu/static_inst.hh" 57#include "debug/Checker.hh" 58#include "params/CheckerCPU.hh" 59#include "sim/eventq.hh" 60 61// forward declarations 62namespace TheISA 63{ 64 class TLB; 65} 66 67template <class> 68class BaseDynInst; 69class ThreadContext; 70class Request; 71 72/** 73 * CheckerCPU class. Dynamically verifies instructions as they are 74 * completed by making sure that the instruction and its results match 75 * the independent execution of the benchmark inside the checker. The 76 * checker verifies instructions in order, regardless of the order in 77 * which instructions complete. There are certain results that can 78 * not be verified, specifically the result of a store conditional or 79 * the values of uncached accesses. In these cases, and with 80 * instructions marked as "IsUnverifiable", the checker assumes that 81 * the value from the main CPU's execution is correct and simply 82 * copies that value. It provides a CheckerThreadContext (see 83 * checker/thread_context.hh) that provides hooks for updating the 84 * Checker's state through any ThreadContext accesses. This allows the 85 * checker to be able to correctly verify instructions, even with 86 * external accesses to the ThreadContext that change state. 87 */ 88class CheckerCPU : public BaseCPU 89{ 90 protected: 91 typedef TheISA::MachInst MachInst; 92 typedef TheISA::FloatReg FloatReg; 93 typedef TheISA::FloatRegBits FloatRegBits; 94 typedef TheISA::MiscReg MiscReg; 95 96 /** id attached to all issued requests */ 97 MasterID masterId; 98 public: 99 virtual void init(); 100 101 public: 102 typedef CheckerCPUParams Params; 103 const Params *params() const 104 { return reinterpret_cast<const Params *>(_params); } 105 CheckerCPU(Params *p); 106 virtual ~CheckerCPU(); 107 108 std::vector<Process*> workload; 109 110 void setSystem(System *system); 111 112 System *systemPtr; 113 114 void setIcachePort(CpuPort *icache_port); 115 116 CpuPort *icachePort; 117 118 void setDcachePort(CpuPort *dcache_port); 119 120 CpuPort *dcachePort; 121 122 CpuPort &getDataPort() 123 { 124 panic("Not supported on checker!"); 125 return *dcachePort; 126 } 127 128 CpuPort &getInstPort() 129 { 130 panic("Not supported on checker!"); 131 return *icachePort; 132 } 133 134 public: 135 // Primary thread being run. 136 SimpleThread *thread; 137 138 ThreadContext *tc; 139 140 TheISA::TLB *itb; 141 TheISA::TLB *dtb; 142 143 Addr dbg_vtophys(Addr addr); 144 145 union Result { 146 uint64_t integer; 147 double dbl; 148 void set(uint64_t i) { integer = i; } 149 void set(double d) { dbl = d; } 150 void get(uint64_t& i) { i = integer; } 151 void get(double& d) { d = dbl; } 152 }; 153 154 // ISAs like ARM can have multiple destination registers to check, 155 // keep them all in a std::queue 156 std::queue<Result> result; 157 158 // Pointer to the one memory request. 159 RequestPtr memReq; 160 161 StaticInstPtr curStaticInst; 162 StaticInstPtr curMacroStaticInst; 163 164 // number of simulated instructions 165 Counter numInst; 166 Counter startNumInst; 167 168 std::queue<int> miscRegIdxs; 169 170 TheISA::TLB* getITBPtr() { return itb; } 171 TheISA::TLB* getDTBPtr() { return dtb; } 172 173 virtual Counter totalInsts() const 174 { 175 return 0; 176 } 177 178 virtual Counter totalOps() const 179 { 180 return 0; 181 } 182 183 // number of simulated loads 184 Counter numLoad; 185 Counter startNumLoad; 186 187 virtual void serialize(std::ostream &os); 188 virtual void unserialize(Checkpoint *cp, const std::string §ion); 189 190 // These functions are only used in CPU models that split 191 // effective address computation from the actual memory access. 192 void setEA(Addr EA) { panic("SimpleCPU::setEA() not implemented\n"); } 193 Addr getEA() { panic("SimpleCPU::getEA() not implemented\n"); } 194 195 // The register accessor methods provide the index of the 196 // instruction's operand (e.g., 0 or 1), not the architectural 197 // register index, to simplify the implementation of register 198 // renaming. We find the architectural register index by indexing 199 // into the instruction's own operand index table. Note that a 200 // raw pointer to the StaticInst is provided instead of a 201 // ref-counted StaticInstPtr to redice overhead. This is fine as 202 // long as these methods don't copy the pointer into any long-term 203 // storage (which is pretty hard to imagine they would have reason 204 // to do). 205 206 uint64_t readIntRegOperand(const StaticInst *si, int idx) 207 { 208 return thread->readIntReg(si->srcRegIdx(idx)); 209 } 210 211 FloatReg readFloatRegOperand(const StaticInst *si, int idx) 212 { 213 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; 214 return thread->readFloatReg(reg_idx); 215 } 216 217 FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx) 218 { 219 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; 220 return thread->readFloatRegBits(reg_idx); 221 } 222 223 template <class T> 224 void setResult(T t) 225 { 226 Result instRes; 227 instRes.set(t); 228 result.push(instRes); 229 } 230 231 void setIntRegOperand(const StaticInst *si, int idx, uint64_t val) 232 { 233 thread->setIntReg(si->destRegIdx(idx), val); 234 setResult<uint64_t>(val); 235 } 236 237 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val) 238 { 239 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; 240 thread->setFloatReg(reg_idx, val); 241 setResult<double>(val); 242 } 243 244 void setFloatRegOperandBits(const StaticInst *si, int idx, 245 FloatRegBits val) 246 { 247 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; 248 thread->setFloatRegBits(reg_idx, val); 249 setResult<uint64_t>(val); 250 } 251 252 bool readPredicate() { return thread->readPredicate(); } 253 void setPredicate(bool val) 254 { 255 thread->setPredicate(val); 256 } 257 258 TheISA::PCState pcState() { return thread->pcState(); } 259 void pcState(const TheISA::PCState &val) 260 { 261 DPRINTF(Checker, "Changing PC to %s, old PC %s.\n", 262 val, thread->pcState()); 263 thread->pcState(val); 264 } 265 Addr instAddr() { return thread->instAddr(); } 266 Addr nextInstAddr() { return thread->nextInstAddr(); } 267 MicroPC microPC() { return thread->microPC(); } 268 ////////////////////////////////////////// 269 270 MiscReg readMiscRegNoEffect(int misc_reg) 271 { 272 return thread->readMiscRegNoEffect(misc_reg); 273 } 274 275 MiscReg readMiscReg(int misc_reg) 276 { 277 return thread->readMiscReg(misc_reg); 278 } 279 280 void setMiscRegNoEffect(int misc_reg, const MiscReg &val) 281 { 282 miscRegIdxs.push(misc_reg); 283 return thread->setMiscRegNoEffect(misc_reg, val); 284 } 285 286 void setMiscReg(int misc_reg, const MiscReg &val) 287 { 288 miscRegIdxs.push(misc_reg); 289 return thread->setMiscReg(misc_reg, val); 290 } 291 292 MiscReg readMiscRegOperand(const StaticInst *si, int idx) 293 { 294 int reg_idx = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag; 295 return thread->readMiscReg(reg_idx); 296 } 297 298 void setMiscRegOperand( 299 const StaticInst *si, int idx, const MiscReg &val) 300 { 301 int reg_idx = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag; 302 return thread->setMiscReg(reg_idx, val); 303 } 304 305#if THE_ISA == MIPS_ISA 306 uint64_t readRegOtherThread(int misc_reg) 307 { 308 panic("MIPS MT not defined for CheckerCPU.\n"); 309 return 0; 310 } 311 312 void setRegOtherThread(int misc_reg, const TheISA::MiscReg &val) 313 { 314 panic("MIPS MT not defined for CheckerCPU.\n"); 315 } 316#endif 317 318 ///////////////////////////////////////// 319 320 void recordPCChange(const TheISA::PCState &val) 321 { 322 changedPC = true; 323 newPCState = val; 324 } 325 326 void demapPage(Addr vaddr, uint64_t asn) 327 { 328 this->itb->demapPage(vaddr, asn); 329 this->dtb->demapPage(vaddr, asn); 330 } 331 332 void demapInstPage(Addr vaddr, uint64_t asn) 333 { 334 this->itb->demapPage(vaddr, asn); 335 } 336 337 void demapDataPage(Addr vaddr, uint64_t asn) 338 { 339 this->dtb->demapPage(vaddr, asn); 340 } 341 342 Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags); 343 Fault writeMem(uint8_t *data, unsigned size, 344 Addr addr, unsigned flags, uint64_t *res); 345 346 void setStCondFailures(unsigned sc_failures) 347 {} 348 ///////////////////////////////////////////////////// 349 350 Fault hwrei() { return thread->hwrei(); } 351 bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); } 352 void wakeup() { } 353 // Assume that the normal CPU's call to syscall was successful. 354 // The checker's state would have already been updated by the syscall. 355 void syscall(uint64_t callnum) { } 356 357 void handleError() 358 { 359 if (exitOnError) 360 dumpAndExit(); 361 } 362 363 bool checkFlags(Request *unverified_req, Addr vAddr, 364 Addr pAddr, int flags); 365 366 void dumpAndExit(); 367 368 ThreadContext *tcBase() { return tc; } 369 SimpleThread *threadBase() { return thread; } 370 371 Result unverifiedResult; 372 Request *unverifiedReq; 373 uint8_t *unverifiedMemData; 374 375 bool changedPC; 376 bool willChangePC; 377 TheISA::PCState newPCState; 378 bool changedNextPC; 379 bool exitOnError; 380 bool updateOnError; 381 bool warnOnlyOnLoadError; 382 383 InstSeqNum youngestSN; 384}; 385 386/** 387 * Templated Checker class. This Checker class is templated on the 388 * DynInstPtr of the instruction type that will be verified. Proper 389 * template instantiations of the Checker must be placed at the bottom 390 * of checker/cpu.cc. 391 */ 392template <class Impl> 393class Checker : public CheckerCPU 394{ 395 private: 396 typedef typename Impl::DynInstPtr DynInstPtr; 397 398 public: 399 Checker(Params *p) 400 : CheckerCPU(p), updateThisCycle(false), unverifiedInst(NULL) 401 { } 402 403 void switchOut(); 404 void takeOverFrom(BaseCPU *oldCPU); 405 406 void advancePC(Fault fault); 407 408 void verify(DynInstPtr &inst); 409 410 void validateInst(DynInstPtr &inst); 411 void validateExecution(DynInstPtr &inst); 412 void validateState(); 413 414 void copyResult(DynInstPtr &inst, uint64_t mismatch_val, int start_idx); 415 void handlePendingInt(); 416 417 private: 418 void handleError(DynInstPtr &inst) 419 { 420 if (exitOnError) { 421 dumpAndExit(inst); 422 } else if (updateOnError) { 423 updateThisCycle = true; 424 } 425 } 426 427 void dumpAndExit(DynInstPtr &inst); 428 429 bool updateThisCycle; 430 431 DynInstPtr unverifiedInst; 432 433 std::list<DynInstPtr> instList; 434 typedef typename std::list<DynInstPtr>::iterator InstListIt; 435 void dumpInsts(); 436}; 437 438#endif // __CPU_CHECKER_CPU_HH__ 439