cpu.hh revision 8733
12315SN/A/* 28733Sgeoffrey.blake@arm.com * Copyright (c) 2011 ARM Limited 38733Sgeoffrey.blake@arm.com * All rights reserved 48733Sgeoffrey.blake@arm.com * 58733Sgeoffrey.blake@arm.com * The license below extends only to copyright in the software and shall 68733Sgeoffrey.blake@arm.com * not be construed as granting a license to any other intellectual 78733Sgeoffrey.blake@arm.com * property including but not limited to intellectual property relating 88733Sgeoffrey.blake@arm.com * to a hardware implementation of the functionality of the software 98733Sgeoffrey.blake@arm.com * licensed hereunder. You may use the software subject to the license 108733Sgeoffrey.blake@arm.com * terms below provided that you ensure that this notice is replicated 118733Sgeoffrey.blake@arm.com * unmodified and in its entirety in all distributions of the software, 128733Sgeoffrey.blake@arm.com * modified or unmodified, in source code or in binary form. 138733Sgeoffrey.blake@arm.com * 142332SN/A * Copyright (c) 2006 The Regents of The University of Michigan 152315SN/A * All rights reserved. 162315SN/A * 172315SN/A * Redistribution and use in source and binary forms, with or without 182315SN/A * modification, are permitted provided that the following conditions are 192315SN/A * met: redistributions of source code must retain the above copyright 202315SN/A * notice, this list of conditions and the following disclaimer; 212315SN/A * redistributions in binary form must reproduce the above copyright 222315SN/A * notice, this list of conditions and the following disclaimer in the 232315SN/A * documentation and/or other materials provided with the distribution; 242315SN/A * neither the name of the copyright holders nor the names of its 252315SN/A * contributors may be used to endorse or promote products derived from 262315SN/A * this software without specific prior written permission. 272315SN/A * 282315SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292315SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302315SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312315SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322315SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332315SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342315SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352315SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362315SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372315SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382315SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392689Sktlim@umich.edu * 402689Sktlim@umich.edu * Authors: Kevin Lim 412315SN/A */ 422315SN/A 432315SN/A#ifndef __CPU_CHECKER_CPU_HH__ 442315SN/A#define __CPU_CHECKER_CPU_HH__ 452315SN/A 462315SN/A#include <list> 478229Snate@binkert.org#include <map> 482315SN/A#include <queue> 492315SN/A 508733Sgeoffrey.blake@arm.com#include "arch/predecoder.hh" 512669Sktlim@umich.edu#include "arch/types.hh" 522315SN/A#include "base/statistics.hh" 532315SN/A#include "config/full_system.hh" 542315SN/A#include "cpu/base.hh" 552315SN/A#include "cpu/base_dyn_inst.hh" 568229Snate@binkert.org#include "cpu/pc_event.hh" 572683Sktlim@umich.edu#include "cpu/simple_thread.hh" 582315SN/A#include "cpu/static_inst.hh" 598733Sgeoffrey.blake@arm.com#include "debug/Checker.hh" 608733Sgeoffrey.blake@arm.com#include "params/CheckerCPU.hh" 612315SN/A#include "sim/eventq.hh" 622315SN/A 632315SN/A// forward declarations 642315SN/A#if FULL_SYSTEM 653468Sgblack@eecs.umich.edunamespace TheISA 663468Sgblack@eecs.umich.edu{ 676022Sgblack@eecs.umich.edu class TLB; 683468Sgblack@eecs.umich.edu} 692315SN/Aclass Processor; 702315SN/Aclass PhysicalMemory; 712315SN/A 722315SN/A#else 732315SN/A 742315SN/Aclass Process; 752315SN/A 762315SN/A#endif // FULL_SYSTEM 772315SN/Atemplate <class> 782315SN/Aclass BaseDynInst; 792680Sktlim@umich.educlass ThreadContext; 802315SN/Aclass MemInterface; 812315SN/Aclass Checkpoint; 822669Sktlim@umich.educlass Request; 832315SN/A 842350SN/A/** 852350SN/A * CheckerCPU class. Dynamically verifies instructions as they are 862350SN/A * completed by making sure that the instruction and its results match 872350SN/A * the independent execution of the benchmark inside the checker. The 882350SN/A * checker verifies instructions in order, regardless of the order in 892350SN/A * which instructions complete. There are certain results that can 902350SN/A * not be verified, specifically the result of a store conditional or 912350SN/A * the values of uncached accesses. In these cases, and with 922350SN/A * instructions marked as "IsUnverifiable", the checker assumes that 932350SN/A * the value from the main CPU's execution is correct and simply 942680Sktlim@umich.edu * copies that value. It provides a CheckerThreadContext (see 952683Sktlim@umich.edu * checker/thread_context.hh) that provides hooks for updating the 962680Sktlim@umich.edu * Checker's state through any ThreadContext accesses. This allows the 972350SN/A * checker to be able to correctly verify instructions, even with 982680Sktlim@umich.edu * external accesses to the ThreadContext that change state. 992350SN/A */ 1002315SN/Aclass CheckerCPU : public BaseCPU 1012315SN/A{ 1022315SN/A protected: 1032315SN/A typedef TheISA::MachInst MachInst; 1042669Sktlim@umich.edu typedef TheISA::FloatReg FloatReg; 1052669Sktlim@umich.edu typedef TheISA::FloatRegBits FloatRegBits; 1062315SN/A typedef TheISA::MiscReg MiscReg; 1072315SN/A public: 1082315SN/A virtual void init(); 1092315SN/A 1102315SN/A public: 1115529Snate@binkert.org typedef CheckerCPUParams Params; 1125529Snate@binkert.org const Params *params() const 1138733Sgeoffrey.blake@arm.com { return reinterpret_cast<const Params *>(_params); } 1142315SN/A CheckerCPU(Params *p); 1152315SN/A virtual ~CheckerCPU(); 1162315SN/A 1178733Sgeoffrey.blake@arm.com std::vector<Process*> workload; 1182679Sktlim@umich.edu 1192315SN/A void setSystem(System *system); 1202315SN/A 1212315SN/A System *systemPtr; 1222679Sktlim@umich.edu 1232679Sktlim@umich.edu void setIcachePort(Port *icache_port); 1242679Sktlim@umich.edu 1252679Sktlim@umich.edu Port *icachePort; 1262679Sktlim@umich.edu 1272679Sktlim@umich.edu void setDcachePort(Port *dcache_port); 1282679Sktlim@umich.edu 1292679Sktlim@umich.edu Port *dcachePort; 1302679Sktlim@umich.edu 1312871Sktlim@umich.edu virtual Port *getPort(const std::string &name, int idx) 1322871Sktlim@umich.edu { 1332871Sktlim@umich.edu panic("Not supported on checker!"); 1342871Sktlim@umich.edu return NULL; 1352871Sktlim@umich.edu } 1362871Sktlim@umich.edu 1372315SN/A public: 1382683Sktlim@umich.edu // Primary thread being run. 1392683Sktlim@umich.edu SimpleThread *thread; 1402315SN/A 1412680Sktlim@umich.edu ThreadContext *tc; 1422315SN/A 1436022Sgblack@eecs.umich.edu TheISA::TLB *itb; 1446022Sgblack@eecs.umich.edu TheISA::TLB *dtb; 1452315SN/A 1462315SN/A#if FULL_SYSTEM 1472315SN/A Addr dbg_vtophys(Addr addr); 1482315SN/A#endif 1492315SN/A 1502315SN/A union Result { 1512315SN/A uint64_t integer; 1522315SN/A double dbl; 1538733Sgeoffrey.blake@arm.com void set(uint64_t i) { integer = i; } 1548733Sgeoffrey.blake@arm.com void set(double d) { dbl = d; } 1558733Sgeoffrey.blake@arm.com void get(uint64_t& i) { i = integer; } 1568733Sgeoffrey.blake@arm.com void get(double& d) { d = dbl; } 1572315SN/A }; 1582315SN/A 1598733Sgeoffrey.blake@arm.com // ISAs like ARM can have multiple destination registers to check, 1608733Sgeoffrey.blake@arm.com // keep them all in a std::queue 1618733Sgeoffrey.blake@arm.com std::queue<Result> result; 1622315SN/A 1632315SN/A // current instruction 1648733Sgeoffrey.blake@arm.com TheISA::MachInst machInst; 1652315SN/A 1662679Sktlim@umich.edu // Pointer to the one memory request. 1672679Sktlim@umich.edu RequestPtr memReq; 1682315SN/A 1692315SN/A StaticInstPtr curStaticInst; 1708733Sgeoffrey.blake@arm.com StaticInstPtr curMacroStaticInst; 1712315SN/A 1722315SN/A // number of simulated instructions 1732315SN/A Counter numInst; 1742315SN/A Counter startNumInst; 1752315SN/A 1762315SN/A std::queue<int> miscRegIdxs; 1772315SN/A 1788733Sgeoffrey.blake@arm.com TheISA::TLB* getITBPtr() { return itb; } 1798733Sgeoffrey.blake@arm.com TheISA::TLB* getDTBPtr() { return dtb; } 1808733Sgeoffrey.blake@arm.com 1812315SN/A virtual Counter totalInstructions() const 1822315SN/A { 1832930Sktlim@umich.edu return 0; 1842315SN/A } 1852315SN/A 1862315SN/A // number of simulated loads 1872315SN/A Counter numLoad; 1882315SN/A Counter startNumLoad; 1892315SN/A 1902315SN/A virtual void serialize(std::ostream &os); 1912315SN/A virtual void unserialize(Checkpoint *cp, const std::string §ion); 1922315SN/A 1932315SN/A // These functions are only used in CPU models that split 1942315SN/A // effective address computation from the actual memory access. 1952315SN/A void setEA(Addr EA) { panic("SimpleCPU::setEA() not implemented\n"); } 1965543Ssaidi@eecs.umich.edu Addr getEA() { panic("SimpleCPU::getEA() not implemented\n"); } 1972315SN/A 1982315SN/A // The register accessor methods provide the index of the 1992315SN/A // instruction's operand (e.g., 0 or 1), not the architectural 2002315SN/A // register index, to simplify the implementation of register 2012315SN/A // renaming. We find the architectural register index by indexing 2022315SN/A // into the instruction's own operand index table. Note that a 2032315SN/A // raw pointer to the StaticInst is provided instead of a 2042315SN/A // ref-counted StaticInstPtr to redice overhead. This is fine as 2052315SN/A // long as these methods don't copy the pointer into any long-term 2062315SN/A // storage (which is pretty hard to imagine they would have reason 2072315SN/A // to do). 2082315SN/A 2093735Sstever@eecs.umich.edu uint64_t readIntRegOperand(const StaticInst *si, int idx) 2102315SN/A { 2112683Sktlim@umich.edu return thread->readIntReg(si->srcRegIdx(idx)); 2122315SN/A } 2132315SN/A 2143735Sstever@eecs.umich.edu FloatReg readFloatRegOperand(const StaticInst *si, int idx) 2152315SN/A { 2162315SN/A int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; 2172683Sktlim@umich.edu return thread->readFloatReg(reg_idx); 2182315SN/A } 2192315SN/A 2203735Sstever@eecs.umich.edu FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx) 2212669Sktlim@umich.edu { 2222669Sktlim@umich.edu int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; 2232683Sktlim@umich.edu return thread->readFloatRegBits(reg_idx); 2242315SN/A } 2252315SN/A 2268733Sgeoffrey.blake@arm.com template <class T> 2278733Sgeoffrey.blake@arm.com void setResult(T t) 2288733Sgeoffrey.blake@arm.com { 2298733Sgeoffrey.blake@arm.com Result instRes; 2308733Sgeoffrey.blake@arm.com instRes.set(t); 2318733Sgeoffrey.blake@arm.com result.push(instRes); 2328733Sgeoffrey.blake@arm.com } 2338733Sgeoffrey.blake@arm.com 2343735Sstever@eecs.umich.edu void setIntRegOperand(const StaticInst *si, int idx, uint64_t val) 2352315SN/A { 2362683Sktlim@umich.edu thread->setIntReg(si->destRegIdx(idx), val); 2378733Sgeoffrey.blake@arm.com setResult<uint64_t>(val); 2382315SN/A } 2392315SN/A 2403735Sstever@eecs.umich.edu void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val) 2412669Sktlim@umich.edu { 2422669Sktlim@umich.edu int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; 2432683Sktlim@umich.edu thread->setFloatReg(reg_idx, val); 2448733Sgeoffrey.blake@arm.com setResult<double>(val); 2452315SN/A } 2462315SN/A 2473735Sstever@eecs.umich.edu void setFloatRegOperandBits(const StaticInst *si, int idx, 2483735Sstever@eecs.umich.edu FloatRegBits val) 2492315SN/A { 2502315SN/A int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; 2512683Sktlim@umich.edu thread->setFloatRegBits(reg_idx, val); 2528733Sgeoffrey.blake@arm.com setResult<uint64_t>(val); 2532315SN/A } 2542315SN/A 2558733Sgeoffrey.blake@arm.com bool readPredicate() { return thread->readPredicate(); } 2568733Sgeoffrey.blake@arm.com void setPredicate(bool val) 2578733Sgeoffrey.blake@arm.com { 2588733Sgeoffrey.blake@arm.com thread->setPredicate(val); 2598733Sgeoffrey.blake@arm.com } 2602669Sktlim@umich.edu 2618733Sgeoffrey.blake@arm.com TheISA::PCState pcState() { return thread->pcState(); } 2628733Sgeoffrey.blake@arm.com void pcState(const TheISA::PCState &val) 2638733Sgeoffrey.blake@arm.com { 2648733Sgeoffrey.blake@arm.com DPRINTF(Checker, "Changing PC to %s, old PC %s.\n", 2658733Sgeoffrey.blake@arm.com val, thread->pcState()); 2668733Sgeoffrey.blake@arm.com thread->pcState(val); 2678733Sgeoffrey.blake@arm.com } 2688733Sgeoffrey.blake@arm.com Addr instAddr() { return thread->instAddr(); } 2698733Sgeoffrey.blake@arm.com Addr nextInstAddr() { return thread->nextInstAddr(); } 2708733Sgeoffrey.blake@arm.com MicroPC microPC() { return thread->microPC(); } 2718733Sgeoffrey.blake@arm.com ////////////////////////////////////////// 2722315SN/A 2734172Ssaidi@eecs.umich.edu MiscReg readMiscRegNoEffect(int misc_reg) 2744172Ssaidi@eecs.umich.edu { 2754172Ssaidi@eecs.umich.edu return thread->readMiscRegNoEffect(misc_reg); 2764172Ssaidi@eecs.umich.edu } 2774172Ssaidi@eecs.umich.edu 2782315SN/A MiscReg readMiscReg(int misc_reg) 2792315SN/A { 2802683Sktlim@umich.edu return thread->readMiscReg(misc_reg); 2812315SN/A } 2822315SN/A 2834172Ssaidi@eecs.umich.edu void setMiscRegNoEffect(int misc_reg, const MiscReg &val) 2842315SN/A { 2854172Ssaidi@eecs.umich.edu miscRegIdxs.push(misc_reg); 2864172Ssaidi@eecs.umich.edu return thread->setMiscRegNoEffect(misc_reg, val); 2872315SN/A } 2882315SN/A 2893468Sgblack@eecs.umich.edu void setMiscReg(int misc_reg, const MiscReg &val) 2902315SN/A { 2912315SN/A miscRegIdxs.push(misc_reg); 2922683Sktlim@umich.edu return thread->setMiscReg(misc_reg, val); 2932315SN/A } 2942315SN/A 2958733Sgeoffrey.blake@arm.com MiscReg readMiscRegOperand(const StaticInst *si, int idx) 2968733Sgeoffrey.blake@arm.com { 2978733Sgeoffrey.blake@arm.com int reg_idx = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag; 2988733Sgeoffrey.blake@arm.com return thread->readMiscReg(reg_idx); 2998733Sgeoffrey.blake@arm.com } 3008733Sgeoffrey.blake@arm.com 3018733Sgeoffrey.blake@arm.com void setMiscRegOperand( 3028733Sgeoffrey.blake@arm.com const StaticInst *si, int idx, const MiscReg &val) 3038733Sgeoffrey.blake@arm.com { 3048733Sgeoffrey.blake@arm.com int reg_idx = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag; 3058733Sgeoffrey.blake@arm.com return thread->setMiscReg(reg_idx, val); 3068733Sgeoffrey.blake@arm.com } 3078733Sgeoffrey.blake@arm.com ///////////////////////////////////////// 3088733Sgeoffrey.blake@arm.com 3098733Sgeoffrey.blake@arm.com void recordPCChange(const TheISA::PCState &val) 3108733Sgeoffrey.blake@arm.com { 3118733Sgeoffrey.blake@arm.com changedPC = true; 3128733Sgeoffrey.blake@arm.com newPCState = val; 3138733Sgeoffrey.blake@arm.com } 3142315SN/A 3155358Sgblack@eecs.umich.edu void demapPage(Addr vaddr, uint64_t asn) 3165358Sgblack@eecs.umich.edu { 3175358Sgblack@eecs.umich.edu this->itb->demapPage(vaddr, asn); 3185358Sgblack@eecs.umich.edu this->dtb->demapPage(vaddr, asn); 3195358Sgblack@eecs.umich.edu } 3205358Sgblack@eecs.umich.edu 3215358Sgblack@eecs.umich.edu void demapInstPage(Addr vaddr, uint64_t asn) 3225358Sgblack@eecs.umich.edu { 3235358Sgblack@eecs.umich.edu this->itb->demapPage(vaddr, asn); 3245358Sgblack@eecs.umich.edu } 3255358Sgblack@eecs.umich.edu 3265358Sgblack@eecs.umich.edu void demapDataPage(Addr vaddr, uint64_t asn) 3275358Sgblack@eecs.umich.edu { 3285358Sgblack@eecs.umich.edu this->dtb->demapPage(vaddr, asn); 3295358Sgblack@eecs.umich.edu } 3305358Sgblack@eecs.umich.edu 3318733Sgeoffrey.blake@arm.com Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags); 3328733Sgeoffrey.blake@arm.com Fault writeMem(uint8_t *data, unsigned size, 3338733Sgeoffrey.blake@arm.com Addr addr, unsigned flags, uint64_t *res); 3348733Sgeoffrey.blake@arm.com 3358733Sgeoffrey.blake@arm.com void setStCondFailures(unsigned sc_failures) 3368733Sgeoffrey.blake@arm.com {} 3378733Sgeoffrey.blake@arm.com ///////////////////////////////////////////////////// 3388733Sgeoffrey.blake@arm.com 3392315SN/A#if FULL_SYSTEM 3405702Ssaidi@eecs.umich.edu Fault hwrei() { return thread->hwrei(); } 3415702Ssaidi@eecs.umich.edu bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); } 3428733Sgeoffrey.blake@arm.com void wakeup() { } 3432315SN/A#else 3442315SN/A // Assume that the normal CPU's call to syscall was successful. 3452332SN/A // The checker's state would have already been updated by the syscall. 3462669Sktlim@umich.edu void syscall(uint64_t callnum) { } 3472315SN/A#endif 3482315SN/A 3492315SN/A void handleError() 3502315SN/A { 3512315SN/A if (exitOnError) 3522732Sktlim@umich.edu dumpAndExit(); 3532315SN/A } 3542732Sktlim@umich.edu 3558733Sgeoffrey.blake@arm.com bool checkFlags(Request *unverified_req, Addr vAddr, 3568733Sgeoffrey.blake@arm.com Addr pAddr, int flags); 3572315SN/A 3582732Sktlim@umich.edu void dumpAndExit(); 3592732Sktlim@umich.edu 3602680Sktlim@umich.edu ThreadContext *tcBase() { return tc; } 3612683Sktlim@umich.edu SimpleThread *threadBase() { return thread; } 3622315SN/A 3632315SN/A Result unverifiedResult; 3642669Sktlim@umich.edu Request *unverifiedReq; 3652679Sktlim@umich.edu uint8_t *unverifiedMemData; 3662315SN/A 3672315SN/A bool changedPC; 3682315SN/A bool willChangePC; 3698733Sgeoffrey.blake@arm.com TheISA::PCState newPCState; 3702315SN/A bool changedNextPC; 3712315SN/A bool exitOnError; 3722354SN/A bool updateOnError; 3732732Sktlim@umich.edu bool warnOnlyOnLoadError; 3742315SN/A 3752315SN/A InstSeqNum youngestSN; 3762315SN/A}; 3772315SN/A 3782350SN/A/** 3792350SN/A * Templated Checker class. This Checker class is templated on the 3802350SN/A * DynInstPtr of the instruction type that will be verified. Proper 3812350SN/A * template instantiations of the Checker must be placed at the bottom 3822350SN/A * of checker/cpu.cc. 3832350SN/A */ 3848733Sgeoffrey.blake@arm.comtemplate <class Impl> 3852315SN/Aclass Checker : public CheckerCPU 3862315SN/A{ 3878733Sgeoffrey.blake@arm.com private: 3888733Sgeoffrey.blake@arm.com typedef typename Impl::DynInstPtr DynInstPtr; 3898733Sgeoffrey.blake@arm.com 3902315SN/A public: 3912315SN/A Checker(Params *p) 3928733Sgeoffrey.blake@arm.com : CheckerCPU(p), updateThisCycle(false), unverifiedInst(NULL), 3938733Sgeoffrey.blake@arm.com predecoder(NULL) 3942315SN/A { } 3952315SN/A 3962840Sktlim@umich.edu void switchOut(); 3972315SN/A void takeOverFrom(BaseCPU *oldCPU); 3982315SN/A 3998733Sgeoffrey.blake@arm.com void advancePC(Fault fault); 4008733Sgeoffrey.blake@arm.com 4012732Sktlim@umich.edu void verify(DynInstPtr &inst); 4022315SN/A 4032315SN/A void validateInst(DynInstPtr &inst); 4042315SN/A void validateExecution(DynInstPtr &inst); 4052315SN/A void validateState(); 4062315SN/A 4078733Sgeoffrey.blake@arm.com void copyResult(DynInstPtr &inst, uint64_t mismatch_val, int start_idx); 4088733Sgeoffrey.blake@arm.com void handlePendingInt(); 4092732Sktlim@umich.edu 4102732Sktlim@umich.edu private: 4112732Sktlim@umich.edu void handleError(DynInstPtr &inst) 4122732Sktlim@umich.edu { 4132360SN/A if (exitOnError) { 4142732Sktlim@umich.edu dumpAndExit(inst); 4152360SN/A } else if (updateOnError) { 4162354SN/A updateThisCycle = true; 4172360SN/A } 4182732Sktlim@umich.edu } 4192732Sktlim@umich.edu 4202732Sktlim@umich.edu void dumpAndExit(DynInstPtr &inst); 4212732Sktlim@umich.edu 4222354SN/A bool updateThisCycle; 4232354SN/A 4242354SN/A DynInstPtr unverifiedInst; 4258733Sgeoffrey.blake@arm.com TheISA::Predecoder predecoder; 4262354SN/A 4272315SN/A std::list<DynInstPtr> instList; 4282315SN/A typedef typename std::list<DynInstPtr>::iterator InstListIt; 4292315SN/A void dumpInsts(); 4302315SN/A}; 4312315SN/A 4322315SN/A#endif // __CPU_CHECKER_CPU_HH__ 433