cpu.hh revision 8733
1/* 2 * Copyright (c) 2011 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2006 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Kevin Lim 41 */ 42 43#ifndef __CPU_CHECKER_CPU_HH__ 44#define __CPU_CHECKER_CPU_HH__ 45 46#include <list> 47#include <map> 48#include <queue> 49 50#include "arch/predecoder.hh" 51#include "arch/types.hh" 52#include "base/statistics.hh" 53#include "config/full_system.hh" 54#include "cpu/base.hh" 55#include "cpu/base_dyn_inst.hh" 56#include "cpu/pc_event.hh" 57#include "cpu/simple_thread.hh" 58#include "cpu/static_inst.hh" 59#include "debug/Checker.hh" 60#include "params/CheckerCPU.hh" 61#include "sim/eventq.hh" 62 63// forward declarations 64#if FULL_SYSTEM 65namespace TheISA 66{ 67 class TLB; 68} 69class Processor; 70class PhysicalMemory; 71 72#else 73 74class Process; 75 76#endif // FULL_SYSTEM 77template <class> 78class BaseDynInst; 79class ThreadContext; 80class MemInterface; 81class Checkpoint; 82class Request; 83 84/** 85 * CheckerCPU class. Dynamically verifies instructions as they are 86 * completed by making sure that the instruction and its results match 87 * the independent execution of the benchmark inside the checker. The 88 * checker verifies instructions in order, regardless of the order in 89 * which instructions complete. There are certain results that can 90 * not be verified, specifically the result of a store conditional or 91 * the values of uncached accesses. In these cases, and with 92 * instructions marked as "IsUnverifiable", the checker assumes that 93 * the value from the main CPU's execution is correct and simply 94 * copies that value. It provides a CheckerThreadContext (see 95 * checker/thread_context.hh) that provides hooks for updating the 96 * Checker's state through any ThreadContext accesses. This allows the 97 * checker to be able to correctly verify instructions, even with 98 * external accesses to the ThreadContext that change state. 99 */ 100class CheckerCPU : public BaseCPU 101{ 102 protected: 103 typedef TheISA::MachInst MachInst; 104 typedef TheISA::FloatReg FloatReg; 105 typedef TheISA::FloatRegBits FloatRegBits; 106 typedef TheISA::MiscReg MiscReg; 107 public: 108 virtual void init(); 109 110 public: 111 typedef CheckerCPUParams Params; 112 const Params *params() const 113 { return reinterpret_cast<const Params *>(_params); } 114 CheckerCPU(Params *p); 115 virtual ~CheckerCPU(); 116 117 std::vector<Process*> workload; 118 119 void setSystem(System *system); 120 121 System *systemPtr; 122 123 void setIcachePort(Port *icache_port); 124 125 Port *icachePort; 126 127 void setDcachePort(Port *dcache_port); 128 129 Port *dcachePort; 130 131 virtual Port *getPort(const std::string &name, int idx) 132 { 133 panic("Not supported on checker!"); 134 return NULL; 135 } 136 137 public: 138 // Primary thread being run. 139 SimpleThread *thread; 140 141 ThreadContext *tc; 142 143 TheISA::TLB *itb; 144 TheISA::TLB *dtb; 145 146#if FULL_SYSTEM 147 Addr dbg_vtophys(Addr addr); 148#endif 149 150 union Result { 151 uint64_t integer; 152 double dbl; 153 void set(uint64_t i) { integer = i; } 154 void set(double d) { dbl = d; } 155 void get(uint64_t& i) { i = integer; } 156 void get(double& d) { d = dbl; } 157 }; 158 159 // ISAs like ARM can have multiple destination registers to check, 160 // keep them all in a std::queue 161 std::queue<Result> result; 162 163 // current instruction 164 TheISA::MachInst machInst; 165 166 // Pointer to the one memory request. 167 RequestPtr memReq; 168 169 StaticInstPtr curStaticInst; 170 StaticInstPtr curMacroStaticInst; 171 172 // number of simulated instructions 173 Counter numInst; 174 Counter startNumInst; 175 176 std::queue<int> miscRegIdxs; 177 178 TheISA::TLB* getITBPtr() { return itb; } 179 TheISA::TLB* getDTBPtr() { return dtb; } 180 181 virtual Counter totalInstructions() const 182 { 183 return 0; 184 } 185 186 // number of simulated loads 187 Counter numLoad; 188 Counter startNumLoad; 189 190 virtual void serialize(std::ostream &os); 191 virtual void unserialize(Checkpoint *cp, const std::string §ion); 192 193 // These functions are only used in CPU models that split 194 // effective address computation from the actual memory access. 195 void setEA(Addr EA) { panic("SimpleCPU::setEA() not implemented\n"); } 196 Addr getEA() { panic("SimpleCPU::getEA() not implemented\n"); } 197 198 // The register accessor methods provide the index of the 199 // instruction's operand (e.g., 0 or 1), not the architectural 200 // register index, to simplify the implementation of register 201 // renaming. We find the architectural register index by indexing 202 // into the instruction's own operand index table. Note that a 203 // raw pointer to the StaticInst is provided instead of a 204 // ref-counted StaticInstPtr to redice overhead. This is fine as 205 // long as these methods don't copy the pointer into any long-term 206 // storage (which is pretty hard to imagine they would have reason 207 // to do). 208 209 uint64_t readIntRegOperand(const StaticInst *si, int idx) 210 { 211 return thread->readIntReg(si->srcRegIdx(idx)); 212 } 213 214 FloatReg readFloatRegOperand(const StaticInst *si, int idx) 215 { 216 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; 217 return thread->readFloatReg(reg_idx); 218 } 219 220 FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx) 221 { 222 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; 223 return thread->readFloatRegBits(reg_idx); 224 } 225 226 template <class T> 227 void setResult(T t) 228 { 229 Result instRes; 230 instRes.set(t); 231 result.push(instRes); 232 } 233 234 void setIntRegOperand(const StaticInst *si, int idx, uint64_t val) 235 { 236 thread->setIntReg(si->destRegIdx(idx), val); 237 setResult<uint64_t>(val); 238 } 239 240 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val) 241 { 242 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; 243 thread->setFloatReg(reg_idx, val); 244 setResult<double>(val); 245 } 246 247 void setFloatRegOperandBits(const StaticInst *si, int idx, 248 FloatRegBits val) 249 { 250 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; 251 thread->setFloatRegBits(reg_idx, val); 252 setResult<uint64_t>(val); 253 } 254 255 bool readPredicate() { return thread->readPredicate(); } 256 void setPredicate(bool val) 257 { 258 thread->setPredicate(val); 259 } 260 261 TheISA::PCState pcState() { return thread->pcState(); } 262 void pcState(const TheISA::PCState &val) 263 { 264 DPRINTF(Checker, "Changing PC to %s, old PC %s.\n", 265 val, thread->pcState()); 266 thread->pcState(val); 267 } 268 Addr instAddr() { return thread->instAddr(); } 269 Addr nextInstAddr() { return thread->nextInstAddr(); } 270 MicroPC microPC() { return thread->microPC(); } 271 ////////////////////////////////////////// 272 273 MiscReg readMiscRegNoEffect(int misc_reg) 274 { 275 return thread->readMiscRegNoEffect(misc_reg); 276 } 277 278 MiscReg readMiscReg(int misc_reg) 279 { 280 return thread->readMiscReg(misc_reg); 281 } 282 283 void setMiscRegNoEffect(int misc_reg, const MiscReg &val) 284 { 285 miscRegIdxs.push(misc_reg); 286 return thread->setMiscRegNoEffect(misc_reg, val); 287 } 288 289 void setMiscReg(int misc_reg, const MiscReg &val) 290 { 291 miscRegIdxs.push(misc_reg); 292 return thread->setMiscReg(misc_reg, val); 293 } 294 295 MiscReg readMiscRegOperand(const StaticInst *si, int idx) 296 { 297 int reg_idx = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag; 298 return thread->readMiscReg(reg_idx); 299 } 300 301 void setMiscRegOperand( 302 const StaticInst *si, int idx, const MiscReg &val) 303 { 304 int reg_idx = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag; 305 return thread->setMiscReg(reg_idx, val); 306 } 307 ///////////////////////////////////////// 308 309 void recordPCChange(const TheISA::PCState &val) 310 { 311 changedPC = true; 312 newPCState = val; 313 } 314 315 void demapPage(Addr vaddr, uint64_t asn) 316 { 317 this->itb->demapPage(vaddr, asn); 318 this->dtb->demapPage(vaddr, asn); 319 } 320 321 void demapInstPage(Addr vaddr, uint64_t asn) 322 { 323 this->itb->demapPage(vaddr, asn); 324 } 325 326 void demapDataPage(Addr vaddr, uint64_t asn) 327 { 328 this->dtb->demapPage(vaddr, asn); 329 } 330 331 Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags); 332 Fault writeMem(uint8_t *data, unsigned size, 333 Addr addr, unsigned flags, uint64_t *res); 334 335 void setStCondFailures(unsigned sc_failures) 336 {} 337 ///////////////////////////////////////////////////// 338 339#if FULL_SYSTEM 340 Fault hwrei() { return thread->hwrei(); } 341 bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); } 342 void wakeup() { } 343#else 344 // Assume that the normal CPU's call to syscall was successful. 345 // The checker's state would have already been updated by the syscall. 346 void syscall(uint64_t callnum) { } 347#endif 348 349 void handleError() 350 { 351 if (exitOnError) 352 dumpAndExit(); 353 } 354 355 bool checkFlags(Request *unverified_req, Addr vAddr, 356 Addr pAddr, int flags); 357 358 void dumpAndExit(); 359 360 ThreadContext *tcBase() { return tc; } 361 SimpleThread *threadBase() { return thread; } 362 363 Result unverifiedResult; 364 Request *unverifiedReq; 365 uint8_t *unverifiedMemData; 366 367 bool changedPC; 368 bool willChangePC; 369 TheISA::PCState newPCState; 370 bool changedNextPC; 371 bool exitOnError; 372 bool updateOnError; 373 bool warnOnlyOnLoadError; 374 375 InstSeqNum youngestSN; 376}; 377 378/** 379 * Templated Checker class. This Checker class is templated on the 380 * DynInstPtr of the instruction type that will be verified. Proper 381 * template instantiations of the Checker must be placed at the bottom 382 * of checker/cpu.cc. 383 */ 384template <class Impl> 385class Checker : public CheckerCPU 386{ 387 private: 388 typedef typename Impl::DynInstPtr DynInstPtr; 389 390 public: 391 Checker(Params *p) 392 : CheckerCPU(p), updateThisCycle(false), unverifiedInst(NULL), 393 predecoder(NULL) 394 { } 395 396 void switchOut(); 397 void takeOverFrom(BaseCPU *oldCPU); 398 399 void advancePC(Fault fault); 400 401 void verify(DynInstPtr &inst); 402 403 void validateInst(DynInstPtr &inst); 404 void validateExecution(DynInstPtr &inst); 405 void validateState(); 406 407 void copyResult(DynInstPtr &inst, uint64_t mismatch_val, int start_idx); 408 void handlePendingInt(); 409 410 private: 411 void handleError(DynInstPtr &inst) 412 { 413 if (exitOnError) { 414 dumpAndExit(inst); 415 } else if (updateOnError) { 416 updateThisCycle = true; 417 } 418 } 419 420 void dumpAndExit(DynInstPtr &inst); 421 422 bool updateThisCycle; 423 424 DynInstPtr unverifiedInst; 425 TheISA::Predecoder predecoder; 426 427 std::list<DynInstPtr> instList; 428 typedef typename std::list<DynInstPtr>::iterator InstListIt; 429 void dumpInsts(); 430}; 431 432#endif // __CPU_CHECKER_CPU_HH__ 433