cpu.cc revision 2722:610b13e19da0
1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim 29 */ 30 31#include <list> 32#include <string> 33 34#include "base/refcnt.hh" 35#include "cpu/base.hh" 36#include "cpu/base_dyn_inst.hh" 37#include "cpu/checker/cpu.hh" 38#include "cpu/simple_thread.hh" 39#include "cpu/thread_context.hh" 40#include "cpu/static_inst.hh" 41#include "mem/packet_impl.hh" 42#include "sim/byteswap.hh" 43#include "sim/sim_object.hh" 44#include "sim/stats.hh" 45 46#include "cpu/o3/alpha_dyn_inst.hh" 47#include "cpu/o3/alpha_impl.hh" 48 49//#include "cpu/ozone/dyn_inst.hh" 50//#include "cpu/ozone/ozone_impl.hh" 51//#include "cpu/ozone/simple_impl.hh" 52 53#if FULL_SYSTEM 54#include "sim/system.hh" 55#include "arch/vtophys.hh" 56#endif // FULL_SYSTEM 57 58using namespace std; 59//The CheckerCPU does alpha only 60using namespace AlphaISA; 61 62void 63CheckerCPU::init() 64{ 65} 66 67CheckerCPU::CheckerCPU(Params *p) 68 : BaseCPU(p), thread(NULL), tc(NULL) 69{ 70 memReq = NULL; 71 72 numInst = 0; 73 startNumInst = 0; 74 numLoad = 0; 75 startNumLoad = 0; 76 youngestSN = 0; 77 78 changedPC = willChangePC = changedNextPC = false; 79 80 exitOnError = p->exitOnError; 81#if FULL_SYSTEM 82 itb = p->itb; 83 dtb = p->dtb; 84 systemPtr = NULL; 85#else 86 process = p->process; 87#endif 88} 89 90CheckerCPU::~CheckerCPU() 91{ 92} 93 94void 95CheckerCPU::setMemory(MemObject *mem) 96{ 97#if !FULL_SYSTEM 98 memPtr = mem; 99 thread = new SimpleThread(this, /* thread_num */ 0, process, 100 /* asid */ 0, mem); 101 102 thread->setStatus(ThreadContext::Suspended); 103 tc = thread->getTC(); 104 threadContexts.push_back(tc); 105#endif 106} 107 108void 109CheckerCPU::setSystem(System *system) 110{ 111#if FULL_SYSTEM 112 systemPtr = system; 113 114 thread = new SimpleThread(this, 0, systemPtr, itb, dtb, false); 115 116 thread->setStatus(ThreadContext::Suspended); 117 tc = thread->getTC(); 118 threadContexts.push_back(tc); 119 delete thread->kernelStats; 120 thread->kernelStats = NULL; 121#endif 122} 123 124void 125CheckerCPU::setIcachePort(Port *icache_port) 126{ 127 icachePort = icache_port; 128} 129 130void 131CheckerCPU::setDcachePort(Port *dcache_port) 132{ 133 dcachePort = dcache_port; 134} 135 136void 137CheckerCPU::serialize(ostream &os) 138{ 139/* 140 BaseCPU::serialize(os); 141 SERIALIZE_SCALAR(inst); 142 nameOut(os, csprintf("%s.xc", name())); 143 thread->serialize(os); 144 cacheCompletionEvent.serialize(os); 145*/ 146} 147 148void 149CheckerCPU::unserialize(Checkpoint *cp, const string §ion) 150{ 151/* 152 BaseCPU::unserialize(cp, section); 153 UNSERIALIZE_SCALAR(inst); 154 thread->unserialize(cp, csprintf("%s.xc", section)); 155*/ 156} 157 158Fault 159CheckerCPU::copySrcTranslate(Addr src) 160{ 161 panic("Unimplemented!"); 162} 163 164Fault 165CheckerCPU::copy(Addr dest) 166{ 167 panic("Unimplemented!"); 168} 169 170template <class T> 171Fault 172CheckerCPU::read(Addr addr, T &data, unsigned flags) 173{ 174 // need to fill in CPU & thread IDs here 175 memReq = new Request(); 176 177 memReq->setVirt(0, addr, sizeof(T), flags, thread->readPC()); 178 179 // translate to physical address 180 translateDataReadReq(memReq); 181 182 Packet *pkt = new Packet(memReq, Packet::ReadReq, Packet::Broadcast); 183 184 pkt->dataStatic(&data); 185 186 if (!(memReq->getFlags() & UNCACHEABLE)) { 187 // Access memory to see if we have the same data 188 dcachePort->sendFunctional(pkt); 189 } else { 190 // Assume the data is correct if it's an uncached access 191 memcpy(&data, &unverifiedResult.integer, sizeof(T)); 192 } 193 194 delete pkt; 195 196 return NoFault; 197} 198 199#ifndef DOXYGEN_SHOULD_SKIP_THIS 200 201template 202Fault 203CheckerCPU::read(Addr addr, uint64_t &data, unsigned flags); 204 205template 206Fault 207CheckerCPU::read(Addr addr, uint32_t &data, unsigned flags); 208 209template 210Fault 211CheckerCPU::read(Addr addr, uint16_t &data, unsigned flags); 212 213template 214Fault 215CheckerCPU::read(Addr addr, uint8_t &data, unsigned flags); 216 217#endif //DOXYGEN_SHOULD_SKIP_THIS 218 219template<> 220Fault 221CheckerCPU::read(Addr addr, double &data, unsigned flags) 222{ 223 return read(addr, *(uint64_t*)&data, flags); 224} 225 226template<> 227Fault 228CheckerCPU::read(Addr addr, float &data, unsigned flags) 229{ 230 return read(addr, *(uint32_t*)&data, flags); 231} 232 233template<> 234Fault 235CheckerCPU::read(Addr addr, int32_t &data, unsigned flags) 236{ 237 return read(addr, (uint32_t&)data, flags); 238} 239 240template <class T> 241Fault 242CheckerCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) 243{ 244 // need to fill in CPU & thread IDs here 245 memReq = new Request(); 246 247 memReq->setVirt(0, addr, sizeof(T), flags, thread->readPC()); 248 249 // translate to physical address 250 thread->translateDataWriteReq(memReq); 251 252 // Can compare the write data and result only if it's cacheable, 253 // not a store conditional, or is a store conditional that 254 // succeeded. 255 // @todo: Verify that actual memory matches up with these values. 256 // Right now it only verifies that the instruction data is the 257 // same as what was in the request that got sent to memory; there 258 // is no verification that it is the same as what is in memory. 259 // This is because the LSQ would have to be snooped in the CPU to 260 // verify this data. 261 if (unverifiedReq && 262 !(unverifiedReq->getFlags() & UNCACHEABLE) && 263 (!(unverifiedReq->getFlags() & LOCKED) || 264 ((unverifiedReq->getFlags() & LOCKED) && 265 unverifiedReq->getScResult() == 1))) { 266 T inst_data; 267/* 268 // This code would work if the LSQ allowed for snooping. 269 Packet *pkt = new Packet(memReq, Packet::ReadReq, Packet::Broadcast); 270 pkt.dataStatic(&inst_data); 271 272 dcachePort->sendFunctional(pkt); 273 274 delete pkt; 275*/ 276 memcpy(&inst_data, unverifiedMemData, sizeof(T)); 277 278 if (data != inst_data) { 279 warn("%lli: Store value does not match value in memory! " 280 "Instruction: %#x, memory: %#x", 281 curTick, inst_data, data); 282 handleError(); 283 } 284 } 285 286 // Assume the result was the same as the one passed in. This checker 287 // doesn't check if the SC should succeed or fail, it just checks the 288 // value. 289 if (res && unverifiedReq->scResultValid()) 290 *res = unverifiedReq->getScResult(); 291 292 return NoFault; 293} 294 295 296#ifndef DOXYGEN_SHOULD_SKIP_THIS 297template 298Fault 299CheckerCPU::write(uint64_t data, Addr addr, unsigned flags, uint64_t *res); 300 301template 302Fault 303CheckerCPU::write(uint32_t data, Addr addr, unsigned flags, uint64_t *res); 304 305template 306Fault 307CheckerCPU::write(uint16_t data, Addr addr, unsigned flags, uint64_t *res); 308 309template 310Fault 311CheckerCPU::write(uint8_t data, Addr addr, unsigned flags, uint64_t *res); 312 313#endif //DOXYGEN_SHOULD_SKIP_THIS 314 315template<> 316Fault 317CheckerCPU::write(double data, Addr addr, unsigned flags, uint64_t *res) 318{ 319 return write(*(uint64_t*)&data, addr, flags, res); 320} 321 322template<> 323Fault 324CheckerCPU::write(float data, Addr addr, unsigned flags, uint64_t *res) 325{ 326 return write(*(uint32_t*)&data, addr, flags, res); 327} 328 329template<> 330Fault 331CheckerCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res) 332{ 333 return write((uint32_t)data, addr, flags, res); 334} 335 336 337#if FULL_SYSTEM 338Addr 339CheckerCPU::dbg_vtophys(Addr addr) 340{ 341 return vtophys(tc, addr); 342} 343#endif // FULL_SYSTEM 344 345bool 346CheckerCPU::translateInstReq(Request *req) 347{ 348#if FULL_SYSTEM 349 return (thread->translateInstReq(req) == NoFault); 350#else 351 thread->translateInstReq(req); 352 return true; 353#endif 354} 355 356void 357CheckerCPU::translateDataReadReq(Request *req) 358{ 359 thread->translateDataReadReq(req); 360 361 if (req->getVaddr() != unverifiedReq->getVaddr()) { 362 warn("%lli: Request virtual addresses do not match! Inst: %#x, " 363 "checker: %#x", 364 curTick, unverifiedReq->getVaddr(), req->getVaddr()); 365 handleError(); 366 } 367 req->setPaddr(unverifiedReq->getPaddr()); 368 369 if (checkFlags(req)) { 370 warn("%lli: Request flags do not match! Inst: %#x, checker: %#x", 371 curTick, unverifiedReq->getFlags(), req->getFlags()); 372 handleError(); 373 } 374} 375 376void 377CheckerCPU::translateDataWriteReq(Request *req) 378{ 379 thread->translateDataWriteReq(req); 380 381 if (req->getVaddr() != unverifiedReq->getVaddr()) { 382 warn("%lli: Request virtual addresses do not match! Inst: %#x, " 383 "checker: %#x", 384 curTick, unverifiedReq->getVaddr(), req->getVaddr()); 385 handleError(); 386 } 387 req->setPaddr(unverifiedReq->getPaddr()); 388 389 if (checkFlags(req)) { 390 warn("%lli: Request flags do not match! Inst: %#x, checker: %#x", 391 curTick, unverifiedReq->getFlags(), req->getFlags()); 392 handleError(); 393 } 394} 395 396bool 397CheckerCPU::checkFlags(Request *req) 398{ 399 // Remove any dynamic flags that don't have to do with the request itself. 400 unsigned flags = unverifiedReq->getFlags(); 401 unsigned mask = LOCKED | PHYSICAL | VPTE | ALTMODE | UNCACHEABLE | NO_FAULT; 402 flags = flags & (mask); 403 if (flags == req->getFlags()) { 404 return false; 405 } else { 406 return true; 407 } 408} 409 410template <class DynInstPtr> 411void 412Checker<DynInstPtr>::tick(DynInstPtr &completed_inst) 413{ 414 DynInstPtr inst; 415 416 // Either check this instruction, or add it to a list of 417 // instructions waiting to be checked. Instructions must be 418 // checked in program order, so if a store has committed yet not 419 // completed, there may be some instructions that are waiting 420 // behind it that have completed and must be checked. 421 if (!instList.empty()) { 422 if (youngestSN < completed_inst->seqNum) { 423 DPRINTF(Checker, "Adding instruction [sn:%lli] PC:%#x to list.\n", 424 completed_inst->seqNum, completed_inst->readPC()); 425 instList.push_back(completed_inst); 426 youngestSN = completed_inst->seqNum; 427 } 428 429 if (!instList.front()->isCompleted()) { 430 return; 431 } else { 432 inst = instList.front(); 433 instList.pop_front(); 434 } 435 } else { 436 if (!completed_inst->isCompleted()) { 437 if (youngestSN < completed_inst->seqNum) { 438 DPRINTF(Checker, "Adding instruction [sn:%lli] PC:%#x to list.\n", 439 completed_inst->seqNum, completed_inst->readPC()); 440 instList.push_back(completed_inst); 441 youngestSN = completed_inst->seqNum; 442 } 443 return; 444 } else { 445 if (youngestSN < completed_inst->seqNum) { 446 inst = completed_inst; 447 youngestSN = completed_inst->seqNum; 448 } else { 449 return; 450 } 451 } 452 } 453 454 // Try to check all instructions that are completed, ending if we 455 // run out of instructions to check or if an instruction is not 456 // yet completed. 457 while (1) { 458 DPRINTF(Checker, "Processing instruction [sn:%lli] PC:%#x.\n", 459 inst->seqNum, inst->readPC()); 460 unverifiedResult.integer = inst->readIntResult(); 461 unverifiedReq = inst->req; 462 unverifiedMemData = inst->memData; 463 numCycles++; 464 465 Fault fault = NoFault; 466 467 // maintain $r0 semantics 468 thread->setIntReg(ZeroReg, 0); 469#ifdef TARGET_ALPHA 470 thread->setFloatRegDouble(ZeroReg, 0.0); 471#endif // TARGET_ALPHA 472 473 // Check if any recent PC changes match up with anything we 474 // expect to happen. This is mostly to check if traps or 475 // PC-based events have occurred in both the checker and CPU. 476 if (changedPC) { 477 DPRINTF(Checker, "Changed PC recently to %#x\n", 478 thread->readPC()); 479 if (willChangePC) { 480 if (newPC == thread->readPC()) { 481 DPRINTF(Checker, "Changed PC matches expected PC\n"); 482 } else { 483 warn("%lli: Changed PC does not match expected PC, " 484 "changed: %#x, expected: %#x", 485 curTick, thread->readPC(), newPC); 486 handleError(); 487 } 488 willChangePC = false; 489 } 490 changedPC = false; 491 } 492 if (changedNextPC) { 493 DPRINTF(Checker, "Changed NextPC recently to %#x\n", 494 thread->readNextPC()); 495 changedNextPC = false; 496 } 497 498 // Try to fetch the instruction 499 500#if FULL_SYSTEM 501#define IFETCH_FLAGS(pc) ((pc) & 1) ? PHYSICAL : 0 502#else 503#define IFETCH_FLAGS(pc) 0 504#endif 505 506 uint64_t fetch_PC = thread->readPC() & ~3; 507 508 // set up memory request for instruction fetch 509 memReq = new Request(inst->threadNumber, fetch_PC, 510 sizeof(uint32_t), 511 IFETCH_FLAGS(thread->readPC()), 512 fetch_PC, thread->readCpuId(), inst->threadNumber); 513 514 bool succeeded = translateInstReq(memReq); 515 516 if (!succeeded) { 517 if (inst->getFault() == NoFault) { 518 // In this case the instruction was not a dummy 519 // instruction carrying an ITB fault. In the single 520 // threaded case the ITB should still be able to 521 // translate this instruction; in the SMT case it's 522 // possible that its ITB entry was kicked out. 523 warn("%lli: Instruction PC %#x was not found in the ITB!", 524 curTick, thread->readPC()); 525 handleError(); 526 527 // go to the next instruction 528 thread->setPC(thread->readNextPC()); 529 thread->setNextPC(thread->readNextPC() + sizeof(MachInst)); 530 531 return; 532 } else { 533 // The instruction is carrying an ITB fault. Handle 534 // the fault and see if our results match the CPU on 535 // the next tick(). 536 fault = inst->getFault(); 537 } 538 } 539 540 if (fault == NoFault) { 541 Packet *pkt = new Packet(memReq, Packet::ReadReq, 542 Packet::Broadcast); 543 544 pkt->dataStatic(&machInst); 545 546 icachePort->sendFunctional(pkt); 547 548 delete pkt; 549 550 // keep an instruction count 551 numInst++; 552 553 // decode the instruction 554 machInst = gtoh(machInst); 555 // Checks that the instruction matches what we expected it to be. 556 // Checks both the machine instruction and the PC. 557 validateInst(inst); 558 559 curStaticInst = StaticInst::decode(makeExtMI(machInst, 560 thread->readPC())); 561 562#if FULL_SYSTEM 563 thread->setInst(machInst); 564#endif // FULL_SYSTEM 565 566 fault = inst->getFault(); 567 } 568 569 // Discard fetch's memReq. 570 delete memReq; 571 memReq = NULL; 572 573 // Either the instruction was a fault and we should process the fault, 574 // or we should just go ahead execute the instruction. This assumes 575 // that the instruction is properly marked as a fault. 576 if (fault == NoFault) { 577 578 thread->funcExeInst++; 579 580 fault = curStaticInst->execute(this, NULL); 581 582 // Checks to make sure instrution results are correct. 583 validateExecution(inst); 584 585 if (curStaticInst->isLoad()) { 586 ++numLoad; 587 } 588 } 589 590 if (fault != NoFault) { 591#if FULL_SYSTEM 592 fault->invoke(tc); 593 willChangePC = true; 594 newPC = thread->readPC(); 595 DPRINTF(Checker, "Fault, PC is now %#x\n", newPC); 596#else // !FULL_SYSTEM 597 fatal("fault (%d) detected @ PC 0x%08p", fault, thread->readPC()); 598#endif // FULL_SYSTEM 599 } else { 600#if THE_ISA != MIPS_ISA 601 // go to the next instruction 602 thread->setPC(thread->readNextPC()); 603 thread->setNextPC(thread->readNextPC() + sizeof(MachInst)); 604#else 605 // go to the next instruction 606 thread->setPC(thread->readNextPC()); 607 thread->setNextPC(thread->readNextNPC()); 608 thread->setNextNPC(thread->readNextNPC() + sizeof(MachInst)); 609#endif 610 611 } 612 613#if FULL_SYSTEM 614 // @todo: Determine if these should happen only if the 615 // instruction hasn't faulted. In the SimpleCPU case this may 616 // not be true, but in the O3 or Ozone case this may be true. 617 Addr oldpc; 618 int count = 0; 619 do { 620 oldpc = thread->readPC(); 621 system->pcEventQueue.service(tc); 622 count++; 623 } while (oldpc != thread->readPC()); 624 if (count > 1) { 625 willChangePC = true; 626 newPC = thread->readPC(); 627 DPRINTF(Checker, "PC Event, PC is now %#x\n", newPC); 628 } 629#endif 630 631 // @todo: Optionally can check all registers. (Or just those 632 // that have been modified). 633 validateState(); 634 635 if (memReq) { 636 delete memReq; 637 memReq = NULL; 638 } 639 640 // Continue verifying instructions if there's another completed 641 // instruction waiting to be verified. 642 if (instList.empty()) { 643 break; 644 } else if (instList.front()->isCompleted()) { 645 inst = instList.front(); 646 instList.pop_front(); 647 } else { 648 break; 649 } 650 } 651} 652 653template <class DynInstPtr> 654void 655Checker<DynInstPtr>::switchOut(Sampler *s) 656{ 657 instList.clear(); 658} 659 660template <class DynInstPtr> 661void 662Checker<DynInstPtr>::takeOverFrom(BaseCPU *oldCPU) 663{ 664} 665 666template <class DynInstPtr> 667void 668Checker<DynInstPtr>::validateInst(DynInstPtr &inst) 669{ 670 if (inst->readPC() != thread->readPC()) { 671 warn("%lli: PCs do not match! Inst: %#x, checker: %#x", 672 curTick, inst->readPC(), thread->readPC()); 673 if (changedPC) { 674 warn("%lli: Changed PCs recently, may not be an error", 675 curTick); 676 } else { 677 handleError(); 678 } 679 } 680 681 MachInst mi = static_cast<MachInst>(inst->staticInst->machInst); 682 683 if (mi != machInst) { 684 warn("%lli: Binary instructions do not match! Inst: %#x, " 685 "checker: %#x", 686 curTick, mi, machInst); 687 handleError(); 688 } 689} 690 691template <class DynInstPtr> 692void 693Checker<DynInstPtr>::validateExecution(DynInstPtr &inst) 694{ 695 if (inst->numDestRegs()) { 696 // @todo: Support more destination registers. 697 if (inst->isUnverifiable()) { 698 // Unverifiable instructions assume they were executed 699 // properly by the CPU. Grab the result from the 700 // instruction and write it to the register. 701 RegIndex idx = inst->destRegIdx(0); 702 if (idx < TheISA::FP_Base_DepTag) { 703 thread->setIntReg(idx, inst->readIntResult()); 704 } else if (idx < TheISA::Fpcr_DepTag) { 705 thread->setFloatRegBits(idx, inst->readIntResult()); 706 } else { 707 thread->setMiscReg(idx, inst->readIntResult()); 708 } 709 } else if (result.integer != inst->readIntResult()) { 710 warn("%lli: Instruction results do not match! (Values may not " 711 "actually be integers) Inst: %#x, checker: %#x", 712 curTick, inst->readIntResult(), result.integer); 713 handleError(); 714 } 715 } 716 717 if (inst->readNextPC() != thread->readNextPC()) { 718 warn("%lli: Instruction next PCs do not match! Inst: %#x, " 719 "checker: %#x", 720 curTick, inst->readNextPC(), thread->readNextPC()); 721 handleError(); 722 } 723 724 // Checking side effect registers can be difficult if they are not 725 // checked simultaneously with the execution of the instruction. 726 // This is because other valid instructions may have modified 727 // these registers in the meantime, and their values are not 728 // stored within the DynInst. 729 while (!miscRegIdxs.empty()) { 730 int misc_reg_idx = miscRegIdxs.front(); 731 miscRegIdxs.pop(); 732 733 if (inst->tcBase()->readMiscReg(misc_reg_idx) != 734 thread->readMiscReg(misc_reg_idx)) { 735 warn("%lli: Misc reg idx %i (side effect) does not match! " 736 "Inst: %#x, checker: %#x", 737 curTick, misc_reg_idx, 738 inst->tcBase()->readMiscReg(misc_reg_idx), 739 thread->readMiscReg(misc_reg_idx)); 740 handleError(); 741 } 742 } 743} 744 745template <class DynInstPtr> 746void 747Checker<DynInstPtr>::validateState() 748{ 749} 750 751template <class DynInstPtr> 752void 753Checker<DynInstPtr>::dumpInsts() 754{ 755 int num = 0; 756 757 InstListIt inst_list_it = --(instList.end()); 758 759 cprintf("Inst list size: %i\n", instList.size()); 760 761 while (inst_list_it != instList.end()) 762 { 763 cprintf("Instruction:%i\n", 764 num); 765 766 cprintf("PC:%#x\n[sn:%lli]\n[tid:%i]\n" 767 "Completed:%i\n", 768 (*inst_list_it)->readPC(), 769 (*inst_list_it)->seqNum, 770 (*inst_list_it)->threadNumber, 771 (*inst_list_it)->isCompleted()); 772 773 cprintf("\n"); 774 775 inst_list_it--; 776 ++num; 777 } 778 779} 780 781//template 782//class Checker<RefCountingPtr<OzoneDynInst<OzoneImpl> > >; 783 784template 785class Checker<RefCountingPtr<AlphaDynInst<AlphaSimpleImpl> > >; 786