cpu.cc revision 13453 
1/*
2 * Copyright (c) 2011,2013,2017 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Kevin Lim
41 *          Geoffrey Blake
42 */
43
44#include "cpu/checker/cpu.hh"
45
46#include <list>
47#include <string>
48
49#include "arch/generic/tlb.hh"
50#include "arch/kernel_stats.hh"
51#include "arch/vtophys.hh"
52#include "cpu/base.hh"
53#include "cpu/simple_thread.hh"
54#include "cpu/static_inst.hh"
55#include "cpu/thread_context.hh"
56#include "params/CheckerCPU.hh"
57#include "sim/full_system.hh"
58
59using namespace std;
60using namespace TheISA;
61
62void
63CheckerCPU::init()
64{
65    masterId = systemPtr->getMasterId(this);
66}
67
68CheckerCPU::CheckerCPU(Params *p)
69    : BaseCPU(p, true), systemPtr(NULL), icachePort(NULL), dcachePort(NULL),
70      tc(NULL), thread(NULL),
71      unverifiedReq(nullptr),
72      unverifiedMemData(nullptr)
73{
74    curStaticInst = NULL;
75    curMacroStaticInst = NULL;
76
77    numInst = 0;
78    startNumInst = 0;
79    numLoad = 0;
80    startNumLoad = 0;
81    youngestSN = 0;
82
83    changedPC = willChangePC = false;
84
85    exitOnError = p->exitOnError;
86    warnOnlyOnLoadError = p->warnOnlyOnLoadError;
87    itb = p->itb;
88    dtb = p->dtb;
89    workload = p->workload;
90
91    updateOnError = true;
92}
93
94CheckerCPU::~CheckerCPU()
95{
96}
97
98void
99CheckerCPU::setSystem(System *system)
100{
101    const Params *p(dynamic_cast<const Params *>(_params));
102
103    systemPtr = system;
104
105    if (FullSystem) {
106        thread = new SimpleThread(this, 0, systemPtr, itb, dtb,
107                                  p->isa[0], false);
108    } else {
109        thread = new SimpleThread(this, 0, systemPtr,
110                                  workload.size() ? workload[0] : NULL,
111                                  itb, dtb, p->isa[0]);
112    }
113
114    tc = thread->getTC();
115    threadContexts.push_back(tc);
116    thread->kernelStats = NULL;
117    // Thread should never be null after this
118    assert(thread != NULL);
119}
120
121void
122CheckerCPU::setIcachePort(MasterPort *icache_port)
123{
124    icachePort = icache_port;
125}
126
127void
128CheckerCPU::setDcachePort(MasterPort *dcache_port)
129{
130    dcachePort = dcache_port;
131}
132
133void
134CheckerCPU::serialize(ostream &os) const
135{
136}
137
138void
139CheckerCPU::unserialize(CheckpointIn &cp)
140{
141}
142
143Fault
144CheckerCPU::readMem(Addr addr, uint8_t *data, unsigned size,
145                    Request::Flags flags)
146{
147    Fault fault = NoFault;
148    int fullSize = size;
149    Addr secondAddr = roundDown(addr + size - 1, cacheLineSize());
150    bool checked_flags = false;
151    bool flags_match = true;
152    Addr pAddr = 0x0;
153
154
155    if (secondAddr > addr)
156       size = secondAddr - addr;
157
158    // Need to account for multiple accesses like the Atomic and TimingSimple
159    while (1) {
160        auto mem_req = std::make_shared<Request>(
161            0, addr, size, flags, masterId,
162            thread->pcState().instAddr(), tc->contextId());
163
164        // translate to physical address
165        fault = dtb->translateFunctional(mem_req, tc, BaseTLB::Read);
166
167        if (!checked_flags && fault == NoFault && unverifiedReq) {
168            flags_match = checkFlags(unverifiedReq, mem_req->getVaddr(),
169                                     mem_req->getPaddr(), mem_req->getFlags());
170            pAddr = mem_req->getPaddr();
171            checked_flags = true;
172        }
173
174        // Now do the access
175        if (fault == NoFault &&
176            !mem_req->getFlags().isSet(Request::NO_ACCESS)) {
177            PacketPtr pkt = Packet::createRead(mem_req);
178
179            pkt->dataStatic(data);
180
181            if (!(mem_req->isUncacheable() || mem_req->isMmappedIpr())) {
182                // Access memory to see if we have the same data
183                dcachePort->sendFunctional(pkt);
184            } else {
185                // Assume the data is correct if it's an uncached access
186                memcpy(data, unverifiedMemData, size);
187            }
188
189            delete pkt;
190        }
191
192        if (fault != NoFault) {
193            if (mem_req->isPrefetch()) {
194                fault = NoFault;
195            }
196            break;
197        }
198
199        //If we don't need to access a second cache line, stop now.
200        if (secondAddr <= addr)
201        {
202            break;
203        }
204
205        // Setup for accessing next cache line
206        data += size;
207        unverifiedMemData += size;
208        size = addr + fullSize - secondAddr;
209        addr = secondAddr;
210    }
211
212    if (!flags_match) {
213        warn("%lli: Flags do not match CPU:%#x %#x %#x Checker:%#x %#x %#x\n",
214             curTick(), unverifiedReq->getVaddr(), unverifiedReq->getPaddr(),
215             unverifiedReq->getFlags(), addr, pAddr, flags);
216        handleError();
217    }
218
219    return fault;
220}
221
222Fault
223CheckerCPU::writeMem(uint8_t *data, unsigned size,
224                     Addr addr, Request::Flags flags, uint64_t *res)
225{
226    Fault fault = NoFault;
227    bool checked_flags = false;
228    bool flags_match = true;
229    Addr pAddr = 0x0;
230    static uint8_t zero_data[64] = {};
231
232    int fullSize = size;
233
234    Addr secondAddr = roundDown(addr + size - 1, cacheLineSize());
235
236    if (secondAddr > addr)
237        size = secondAddr - addr;
238
239    // Need to account for a multiple access like Atomic and Timing CPUs
240    while (1) {
241        auto mem_req = std::make_shared<Request>(
242            0, addr, size, flags, masterId,
243            thread->pcState().instAddr(), tc->contextId());
244
245        // translate to physical address
246        fault = dtb->translateFunctional(mem_req, tc, BaseTLB::Write);
247
248        if (!checked_flags && fault == NoFault && unverifiedReq) {
249           flags_match = checkFlags(unverifiedReq, mem_req->getVaddr(),
250                                    mem_req->getPaddr(), mem_req->getFlags());
251           pAddr = mem_req->getPaddr();
252           checked_flags = true;
253        }
254
255        /*
256         * We don't actually check memory for the store because there
257         * is no guarantee it has left the lsq yet, and therefore we
258         * can't verify the memory on stores without lsq snooping
259         * enabled.  This is left as future work for the Checker: LSQ snooping
260         * and memory validation after stores have committed.
261         */
262        bool was_prefetch = mem_req->isPrefetch();
263
264        //If we don't need to access a second cache line, stop now.
265        if (fault != NoFault || secondAddr <= addr)
266        {
267            if (fault != NoFault && was_prefetch) {
268              fault = NoFault;
269            }
270            break;
271        }
272
273        //Update size and access address
274        size = addr + fullSize - secondAddr;
275        //And access the right address.
276        addr = secondAddr;
277   }
278
279   if (!flags_match) {
280       warn("%lli: Flags do not match CPU:%#x %#x Checker:%#x %#x %#x\n",
281            curTick(), unverifiedReq->getVaddr(), unverifiedReq->getPaddr(),
282            unverifiedReq->getFlags(), addr, pAddr, flags);
283       handleError();
284   }
285
286   // Assume the result was the same as the one passed in.  This checker
287   // doesn't check if the SC should succeed or fail, it just checks the
288   // value.
289   if (unverifiedReq && res && unverifiedReq->extraDataValid())
290       *res = unverifiedReq->getExtraData();
291
292   // Entire purpose here is to make sure we are getting the
293   // same data to send to the mem system as the CPU did.
294   // Cannot check this is actually what went to memory because
295   // there stores can be in ld/st queue or coherent operations
296   // overwriting values.
297   bool extraData = false;
298   if (unverifiedReq) {
299       extraData = unverifiedReq->extraDataValid() ?
300                        unverifiedReq->getExtraData() : true;
301   }
302
303   // If the request is to ZERO a cache block, there is no data to check
304   // against, but it's all zero. We need something to compare to, so use a
305   // const set of zeros.
306   if (flags & Request::STORE_NO_DATA) {
307       assert(!data);
308       assert(sizeof(zero_data) <= fullSize);
309       data = zero_data;
310   }
311
312   if (unverifiedReq && unverifiedMemData &&
313       memcmp(data, unverifiedMemData, fullSize) && extraData) {
314           warn("%lli: Store value does not match value sent to memory! "
315                  "data: %#x inst_data: %#x", curTick(), data,
316                  unverifiedMemData);
317       handleError();
318   }
319
320   return fault;
321}
322
323Addr
324CheckerCPU::dbg_vtophys(Addr addr)
325{
326    return vtophys(tc, addr);
327}
328
329/**
330 * Checks if the flags set by the Checker and Checkee match.
331 */
332bool
333CheckerCPU::checkFlags(const RequestPtr &unverified_req, Addr vAddr,
334                       Addr pAddr, int flags)
335{
336    Addr unverifiedVAddr = unverified_req->getVaddr();
337    Addr unverifiedPAddr = unverified_req->getPaddr();
338    int unverifiedFlags = unverified_req->getFlags();
339
340    if (unverifiedVAddr != vAddr ||
341        unverifiedPAddr != pAddr ||
342        unverifiedFlags != flags) {
343        return false;
344    }
345
346    return true;
347}
348
349void
350CheckerCPU::dumpAndExit()
351{
352    warn("%lli: Checker PC:%s",
353         curTick(), thread->pcState());
354    panic("Checker found an error!");
355}
356