cpu.cc revision 10505:38c7a9ea7729
12131SN/A/* 25268Sksewell@umich.edu * Copyright (c) 2011,2013 ARM Limited 35254Sksewell@umich.edu * All rights reserved 45254Sksewell@umich.edu * 52131SN/A * The license below extends only to copyright in the software and shall 65254Sksewell@umich.edu * not be construed as granting a license to any other intellectual 75254Sksewell@umich.edu * property including but not limited to intellectual property relating 85254Sksewell@umich.edu * to a hardware implementation of the functionality of the software 95254Sksewell@umich.edu * licensed hereunder. You may use the software subject to the license 105254Sksewell@umich.edu * terms below provided that you ensure that this notice is replicated 115254Sksewell@umich.edu * unmodified and in its entirety in all distributions of the software, 125254Sksewell@umich.edu * modified or unmodified, in source code or in binary form. 135254Sksewell@umich.edu * 145254Sksewell@umich.edu * Copyright (c) 2006 The Regents of The University of Michigan 155254Sksewell@umich.edu * All rights reserved. 162131SN/A * 175254Sksewell@umich.edu * Redistribution and use in source and binary forms, with or without 185254Sksewell@umich.edu * modification, are permitted provided that the following conditions are 195254Sksewell@umich.edu * met: redistributions of source code must retain the above copyright 205254Sksewell@umich.edu * notice, this list of conditions and the following disclaimer; 215254Sksewell@umich.edu * redistributions in binary form must reproduce the above copyright 225254Sksewell@umich.edu * notice, this list of conditions and the following disclaimer in the 235254Sksewell@umich.edu * documentation and/or other materials provided with the distribution; 245254Sksewell@umich.edu * neither the name of the copyright holders nor the names of its 255254Sksewell@umich.edu * contributors may be used to endorse or promote products derived from 265254Sksewell@umich.edu * this software without specific prior written permission. 275254Sksewell@umich.edu * 282665Ssaidi@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 295254Sksewell@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 305254Sksewell@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 315222Sksewell@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322131SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332131SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342239SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 357676Snate@binkert.org * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 367676Snate@binkert.org * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 377676Snate@binkert.org * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382680Sktlim@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 398232Snate@binkert.org * 407676Snate@binkert.org * Authors: Kevin Lim 412800Ssaidi@eecs.umich.edu * Geoffrey Blake 427676Snate@binkert.org */ 432800Ssaidi@eecs.umich.edu 442800Ssaidi@eecs.umich.edu#include <list> 452131SN/A#include <string> 462447SN/A 472447SN/A#include "arch/kernel_stats.hh" 482131SN/A#include "arch/vtophys.hh" 498566Sgblack@eecs.umich.edu#include "cpu/checker/cpu.hh" 502131SN/A#include "cpu/base.hh" 518566Sgblack@eecs.umich.edu#include "cpu/simple_thread.hh" 528566Sgblack@eecs.umich.edu#include "cpu/static_inst.hh" 532447SN/A#include "cpu/thread_context.hh" 548566Sgblack@eecs.umich.edu#include "params/CheckerCPU.hh" 558566Sgblack@eecs.umich.edu#include "sim/full_system.hh" 568566Sgblack@eecs.umich.edu#include "sim/tlb.hh" 578566Sgblack@eecs.umich.edu 585222Sksewell@umich.eduusing namespace std; 598566Sgblack@eecs.umich.eduusing namespace TheISA; 605222Sksewell@umich.edu 618566Sgblack@eecs.umich.eduvoid 625222Sksewell@umich.eduCheckerCPU::init() 632447SN/A{ 648566Sgblack@eecs.umich.edu masterId = systemPtr->getMasterId(name()); 658566Sgblack@eecs.umich.edu} 665222Sksewell@umich.edu 678566Sgblack@eecs.umich.eduCheckerCPU::CheckerCPU(Params *p) 688566Sgblack@eecs.umich.edu : BaseCPU(p, true), systemPtr(NULL), icachePort(NULL), dcachePort(NULL), 695222Sksewell@umich.edu tc(NULL), thread(NULL) 708566Sgblack@eecs.umich.edu{ 718566Sgblack@eecs.umich.edu memReq = NULL; 725222Sksewell@umich.edu curStaticInst = NULL; 738566Sgblack@eecs.umich.edu curMacroStaticInst = NULL; 748566Sgblack@eecs.umich.edu 755222Sksewell@umich.edu numInst = 0; 768566Sgblack@eecs.umich.edu startNumInst = 0; 778566Sgblack@eecs.umich.edu numLoad = 0; 784661Sksewell@umich.edu startNumLoad = 0; 798566Sgblack@eecs.umich.edu youngestSN = 0; 808566Sgblack@eecs.umich.edu 814661Sksewell@umich.edu changedPC = willChangePC = false; 828566Sgblack@eecs.umich.edu 838566Sgblack@eecs.umich.edu exitOnError = p->exitOnError; 844661Sksewell@umich.edu warnOnlyOnLoadError = p->warnOnlyOnLoadError; 858566Sgblack@eecs.umich.edu itb = p->itb; 868566Sgblack@eecs.umich.edu dtb = p->dtb; 872447SN/A workload = p->workload; 888566Sgblack@eecs.umich.edu 898566Sgblack@eecs.umich.edu updateOnError = true; 904661Sksewell@umich.edu} 918566Sgblack@eecs.umich.edu 928566Sgblack@eecs.umich.eduCheckerCPU::~CheckerCPU() 932447SN/A{ 948566Sgblack@eecs.umich.edu} 958566Sgblack@eecs.umich.edu 965222Sksewell@umich.eduvoid 978566Sgblack@eecs.umich.eduCheckerCPU::setSystem(System *system) 988566Sgblack@eecs.umich.edu{ 995222Sksewell@umich.edu const Params *p(dynamic_cast<const Params *>(_params)); 1008566Sgblack@eecs.umich.edu 1018566Sgblack@eecs.umich.edu systemPtr = system; 1025222Sksewell@umich.edu 1038566Sgblack@eecs.umich.edu if (FullSystem) { 1048566Sgblack@eecs.umich.edu thread = new SimpleThread(this, 0, systemPtr, itb, dtb, 1055222Sksewell@umich.edu p->isa[0], false); 1068566Sgblack@eecs.umich.edu } else { 1078566Sgblack@eecs.umich.edu thread = new SimpleThread(this, 0, systemPtr, 1085222Sksewell@umich.edu workload.size() ? workload[0] : NULL, 1098566Sgblack@eecs.umich.edu itb, dtb, p->isa[0]); 1108566Sgblack@eecs.umich.edu } 1115222Sksewell@umich.edu 1128566Sgblack@eecs.umich.edu tc = thread->getTC(); 1138566Sgblack@eecs.umich.edu threadContexts.push_back(tc); 1145222Sksewell@umich.edu thread->kernelStats = NULL; 1158566Sgblack@eecs.umich.edu // Thread should never be null after this 1168566Sgblack@eecs.umich.edu assert(thread != NULL); 1172447SN/A} 1188566Sgblack@eecs.umich.edu 1198566Sgblack@eecs.umich.eduvoid 1202447SN/ACheckerCPU::setIcachePort(MasterPort *icache_port) 1218566Sgblack@eecs.umich.edu{ 1228566Sgblack@eecs.umich.edu icachePort = icache_port; 1232447SN/A} 1248566Sgblack@eecs.umich.edu 1258566Sgblack@eecs.umich.eduvoid 1262447SN/ACheckerCPU::setDcachePort(MasterPort *dcache_port) 1278566Sgblack@eecs.umich.edu{ 1288566Sgblack@eecs.umich.edu dcachePort = dcache_port; 1292447SN/A} 1308566Sgblack@eecs.umich.edu 1318566Sgblack@eecs.umich.eduvoid 1322447SN/ACheckerCPU::serialize(ostream &os) 1338566Sgblack@eecs.umich.edu{ 1348566Sgblack@eecs.umich.edu} 1352447SN/A 1368566Sgblack@eecs.umich.eduvoid 1378566Sgblack@eecs.umich.eduCheckerCPU::unserialize(Checkpoint *cp, const string §ion) 1382447SN/A{ 1398566Sgblack@eecs.umich.edu} 1408566Sgblack@eecs.umich.edu 1414661Sksewell@umich.eduFault 1425222Sksewell@umich.eduCheckerCPU::readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags) 1436378Sgblack@eecs.umich.edu{ 1448566Sgblack@eecs.umich.edu Fault fault = NoFault; 1455222Sksewell@umich.edu int fullSize = size; 1466378Sgblack@eecs.umich.edu Addr secondAddr = roundDown(addr + size - 1, cacheLineSize()); 1476378Sgblack@eecs.umich.edu bool checked_flags = false; 1486378Sgblack@eecs.umich.edu bool flags_match = true; 1495222Sksewell@umich.edu Addr pAddr = 0x0; 1505222Sksewell@umich.edu 1516378Sgblack@eecs.umich.edu 1528566Sgblack@eecs.umich.edu if (secondAddr > addr) 1535222Sksewell@umich.edu size = secondAddr - addr; 1546378Sgblack@eecs.umich.edu 1556383Sgblack@eecs.umich.edu // Need to account for multiple accesses like the Atomic and TimingSimple 1566379Sgblack@eecs.umich.edu while (1) { 1576378Sgblack@eecs.umich.edu memReq = new Request(); 1586383Sgblack@eecs.umich.edu memReq->setVirt(0, addr, size, flags, masterId, thread->pcState().instAddr()); 1596379Sgblack@eecs.umich.edu 1606379Sgblack@eecs.umich.edu // translate to physical address 1616383Sgblack@eecs.umich.edu fault = dtb->translateFunctional(memReq, tc, BaseTLB::Read); 1625222Sksewell@umich.edu 1635222Sksewell@umich.edu if (!checked_flags && fault == NoFault && unverifiedReq) { 1646378Sgblack@eecs.umich.edu flags_match = checkFlags(unverifiedReq, memReq->getVaddr(), 1656379Sgblack@eecs.umich.edu memReq->getPaddr(), memReq->getFlags()); 1666383Sgblack@eecs.umich.edu pAddr = memReq->getPaddr(); 1675222Sksewell@umich.edu checked_flags = true; 1686378Sgblack@eecs.umich.edu } 1696378Sgblack@eecs.umich.edu 1706378Sgblack@eecs.umich.edu // Now do the access 1716378Sgblack@eecs.umich.edu if (fault == NoFault && 1726378Sgblack@eecs.umich.edu !memReq->getFlags().isSet(Request::NO_ACCESS)) { 1736379Sgblack@eecs.umich.edu PacketPtr pkt = Packet::createRead(memReq); 1746378Sgblack@eecs.umich.edu 1756383Sgblack@eecs.umich.edu pkt->dataStatic(data); 1766378Sgblack@eecs.umich.edu 1776379Sgblack@eecs.umich.edu if (!(memReq->isUncacheable() || memReq->isMmappedIpr())) { 1786378Sgblack@eecs.umich.edu // Access memory to see if we have the same data 1796383Sgblack@eecs.umich.edu dcachePort->sendFunctional(pkt); 1806378Sgblack@eecs.umich.edu } else { 1816379Sgblack@eecs.umich.edu // Assume the data is correct if it's an uncached access 1826378Sgblack@eecs.umich.edu memcpy(data, unverifiedMemData, size); 1835222Sksewell@umich.edu } 1846378Sgblack@eecs.umich.edu 1856383Sgblack@eecs.umich.edu delete memReq; 1866379Sgblack@eecs.umich.edu memReq = NULL; 1876379Sgblack@eecs.umich.edu delete pkt; 1886379Sgblack@eecs.umich.edu } 1896383Sgblack@eecs.umich.edu 1906378Sgblack@eecs.umich.edu if (fault != NoFault) { 1916378Sgblack@eecs.umich.edu if (memReq->isPrefetch()) { 1926378Sgblack@eecs.umich.edu fault = NoFault; 1937678Sgblack@eecs.umich.edu } 1946378Sgblack@eecs.umich.edu delete memReq; 1956378Sgblack@eecs.umich.edu memReq = NULL; 1966378Sgblack@eecs.umich.edu break; 1976378Sgblack@eecs.umich.edu } 1986378Sgblack@eecs.umich.edu 1996378Sgblack@eecs.umich.edu if (memReq != NULL) { 2006383Sgblack@eecs.umich.edu delete memReq; 2016378Sgblack@eecs.umich.edu } 2026378Sgblack@eecs.umich.edu 2036379Sgblack@eecs.umich.edu //If we don't need to access a second cache line, stop now. 2046378Sgblack@eecs.umich.edu if (secondAddr <= addr) 2056383Sgblack@eecs.umich.edu { 2066378Sgblack@eecs.umich.edu break; 2076378Sgblack@eecs.umich.edu } 2086378Sgblack@eecs.umich.edu 2096378Sgblack@eecs.umich.edu // Setup for accessing next cache line 2106378Sgblack@eecs.umich.edu data += size; 2116378Sgblack@eecs.umich.edu unverifiedMemData += size; 2126378Sgblack@eecs.umich.edu size = addr + fullSize - secondAddr; 2137678Sgblack@eecs.umich.edu addr = secondAddr; 2146378Sgblack@eecs.umich.edu } 2156378Sgblack@eecs.umich.edu 2166378Sgblack@eecs.umich.edu if (!flags_match) { 2176383Sgblack@eecs.umich.edu warn("%lli: Flags do not match CPU:%#x %#x %#x Checker:%#x %#x %#x\n", 2186378Sgblack@eecs.umich.edu curTick(), unverifiedReq->getVaddr(), unverifiedReq->getPaddr(), 2196378Sgblack@eecs.umich.edu unverifiedReq->getFlags(), addr, pAddr, flags); 2206378Sgblack@eecs.umich.edu handleError(); 2216378Sgblack@eecs.umich.edu } 2226383Sgblack@eecs.umich.edu 2236378Sgblack@eecs.umich.edu return fault; 2246378Sgblack@eecs.umich.edu} 2256378Sgblack@eecs.umich.edu 2266378Sgblack@eecs.umich.eduFault 2277678Sgblack@eecs.umich.eduCheckerCPU::writeMem(uint8_t *data, unsigned size, 2286378Sgblack@eecs.umich.edu Addr addr, unsigned flags, uint64_t *res) 2296378Sgblack@eecs.umich.edu{ 2306378Sgblack@eecs.umich.edu Fault fault = NoFault; 2316378Sgblack@eecs.umich.edu bool checked_flags = false; 2326378Sgblack@eecs.umich.edu bool flags_match = true; 2336378Sgblack@eecs.umich.edu Addr pAddr = 0x0; 2346378Sgblack@eecs.umich.edu static uint8_t zero_data[64] = {}; 2356383Sgblack@eecs.umich.edu 2366378Sgblack@eecs.umich.edu int fullSize = size; 2376378Sgblack@eecs.umich.edu 2386378Sgblack@eecs.umich.edu Addr secondAddr = roundDown(addr + size - 1, cacheLineSize()); 2396378Sgblack@eecs.umich.edu 2407678Sgblack@eecs.umich.edu if (secondAddr > addr) 2416378Sgblack@eecs.umich.edu size = secondAddr - addr; 2426378Sgblack@eecs.umich.edu 2436378Sgblack@eecs.umich.edu // Need to account for a multiple access like Atomic and Timing CPUs 2446378Sgblack@eecs.umich.edu while (1) { 2456378Sgblack@eecs.umich.edu memReq = new Request(); 2466378Sgblack@eecs.umich.edu memReq->setVirt(0, addr, size, flags, masterId, thread->pcState().instAddr()); 2476383Sgblack@eecs.umich.edu 2486378Sgblack@eecs.umich.edu // translate to physical address 2496378Sgblack@eecs.umich.edu fault = dtb->translateFunctional(memReq, tc, BaseTLB::Write); 2506378Sgblack@eecs.umich.edu 2516378Sgblack@eecs.umich.edu if (!checked_flags && fault == NoFault && unverifiedReq) { 2527678Sgblack@eecs.umich.edu flags_match = checkFlags(unverifiedReq, memReq->getVaddr(), 2536378Sgblack@eecs.umich.edu memReq->getPaddr(), memReq->getFlags()); 2546378Sgblack@eecs.umich.edu pAddr = memReq->getPaddr(); 2556378Sgblack@eecs.umich.edu checked_flags = true; 2566383Sgblack@eecs.umich.edu } 2576383Sgblack@eecs.umich.edu 2586379Sgblack@eecs.umich.edu /* 2596379Sgblack@eecs.umich.edu * We don't actually check memory for the store because there 2606379Sgblack@eecs.umich.edu * is no guarantee it has left the lsq yet, and therefore we 2616383Sgblack@eecs.umich.edu * can't verify the memory on stores without lsq snooping 2626379Sgblack@eecs.umich.edu * enabled. This is left as future work for the Checker: LSQ snooping 2636383Sgblack@eecs.umich.edu * and memory validation after stores have committed. 2646379Sgblack@eecs.umich.edu */ 2656383Sgblack@eecs.umich.edu bool was_prefetch = memReq->isPrefetch(); 2666378Sgblack@eecs.umich.edu 2676378Sgblack@eecs.umich.edu delete memReq; 2686378Sgblack@eecs.umich.edu 2696378Sgblack@eecs.umich.edu //If we don't need to access a second cache line, stop now. 2706378Sgblack@eecs.umich.edu if (fault != NoFault || secondAddr <= addr) 2716378Sgblack@eecs.umich.edu { 2726383Sgblack@eecs.umich.edu if (fault != NoFault && was_prefetch) { 2736379Sgblack@eecs.umich.edu fault = NoFault; 2746378Sgblack@eecs.umich.edu } 2756378Sgblack@eecs.umich.edu break; 2766378Sgblack@eecs.umich.edu } 2777678Sgblack@eecs.umich.edu 2786378Sgblack@eecs.umich.edu //Update size and access address 2796378Sgblack@eecs.umich.edu size = addr + fullSize - secondAddr; 2806378Sgblack@eecs.umich.edu //And access the right address. 2816383Sgblack@eecs.umich.edu addr = secondAddr; 2826378Sgblack@eecs.umich.edu } 2836378Sgblack@eecs.umich.edu 2846378Sgblack@eecs.umich.edu if (!flags_match) { 2856378Sgblack@eecs.umich.edu warn("%lli: Flags do not match CPU:%#x %#x Checker:%#x %#x %#x\n", 2866383Sgblack@eecs.umich.edu curTick(), unverifiedReq->getVaddr(), unverifiedReq->getPaddr(), 2876378Sgblack@eecs.umich.edu unverifiedReq->getFlags(), addr, pAddr, flags); 2886378Sgblack@eecs.umich.edu handleError(); 2896378Sgblack@eecs.umich.edu } 2906378Sgblack@eecs.umich.edu 2917678Sgblack@eecs.umich.edu // Assume the result was the same as the one passed in. This checker 2926378Sgblack@eecs.umich.edu // doesn't check if the SC should succeed or fail, it just checks the 2936378Sgblack@eecs.umich.edu // value. 2946378Sgblack@eecs.umich.edu if (unverifiedReq && res && unverifiedReq->extraDataValid()) 2956383Sgblack@eecs.umich.edu *res = unverifiedReq->getExtraData(); 2966383Sgblack@eecs.umich.edu 2976379Sgblack@eecs.umich.edu // Entire purpose here is to make sure we are getting the 2986379Sgblack@eecs.umich.edu // same data to send to the mem system as the CPU did. 2996379Sgblack@eecs.umich.edu // Cannot check this is actually what went to memory because 3006383Sgblack@eecs.umich.edu // there stores can be in ld/st queue or coherent operations 3016379Sgblack@eecs.umich.edu // overwriting values. 3026383Sgblack@eecs.umich.edu bool extraData = false; 3036379Sgblack@eecs.umich.edu if (unverifiedReq) { 3046383Sgblack@eecs.umich.edu extraData = unverifiedReq->extraDataValid() ? 3056378Sgblack@eecs.umich.edu unverifiedReq->getExtraData() : true; 3066378Sgblack@eecs.umich.edu } 3076378Sgblack@eecs.umich.edu 3086378Sgblack@eecs.umich.edu // If the request is to ZERO a cache block, there is no data to check 3096378Sgblack@eecs.umich.edu // against, but it's all zero. We need something to compare to, so use a 3106383Sgblack@eecs.umich.edu // const set of zeros. 3116378Sgblack@eecs.umich.edu if (flags & Request::CACHE_BLOCK_ZERO) { 3126379Sgblack@eecs.umich.edu assert(!data); 3136383Sgblack@eecs.umich.edu assert(sizeof(zero_data) <= fullSize); 3146378Sgblack@eecs.umich.edu data = zero_data; 3156378Sgblack@eecs.umich.edu } 3166378Sgblack@eecs.umich.edu 3177678Sgblack@eecs.umich.edu if (unverifiedReq && unverifiedMemData && 3186378Sgblack@eecs.umich.edu memcmp(data, unverifiedMemData, fullSize) && extraData) { 3196383Sgblack@eecs.umich.edu warn("%lli: Store value does not match value sent to memory! " 3206378Sgblack@eecs.umich.edu "data: %#x inst_data: %#x", curTick(), data, 3216383Sgblack@eecs.umich.edu unverifiedMemData); 3226383Sgblack@eecs.umich.edu handleError(); 3236379Sgblack@eecs.umich.edu } 3246379Sgblack@eecs.umich.edu 3256379Sgblack@eecs.umich.edu return fault; 3266383Sgblack@eecs.umich.edu} 3276383Sgblack@eecs.umich.edu 3286379Sgblack@eecs.umich.eduAddr 3296383Sgblack@eecs.umich.eduCheckerCPU::dbg_vtophys(Addr addr) 3306378Sgblack@eecs.umich.edu{ 3316383Sgblack@eecs.umich.edu return vtophys(tc, addr); 3326378Sgblack@eecs.umich.edu} 3336378Sgblack@eecs.umich.edu 3346379Sgblack@eecs.umich.edu/** 3356378Sgblack@eecs.umich.edu * Checks if the flags set by the Checker and Checkee match. 3366383Sgblack@eecs.umich.edu */ 3376378Sgblack@eecs.umich.edubool 3386378Sgblack@eecs.umich.eduCheckerCPU::checkFlags(Request *unverified_req, Addr vAddr, 3396383Sgblack@eecs.umich.edu Addr pAddr, int flags) 3406378Sgblack@eecs.umich.edu{ 3416378Sgblack@eecs.umich.edu Addr unverifiedVAddr = unverified_req->getVaddr(); 3426378Sgblack@eecs.umich.edu Addr unverifiedPAddr = unverified_req->getPaddr(); 3436378Sgblack@eecs.umich.edu int unverifiedFlags = unverified_req->getFlags(); 3446378Sgblack@eecs.umich.edu 3456378Sgblack@eecs.umich.edu if (unverifiedVAddr != vAddr || 3466378Sgblack@eecs.umich.edu unverifiedPAddr != pAddr || 3477678Sgblack@eecs.umich.edu unverifiedFlags != flags) { 3486378Sgblack@eecs.umich.edu return false; 3496378Sgblack@eecs.umich.edu } 3506378Sgblack@eecs.umich.edu 3516378Sgblack@eecs.umich.edu return true; 3526383Sgblack@eecs.umich.edu} 3536383Sgblack@eecs.umich.edu 3546379Sgblack@eecs.umich.eduvoid 3556379Sgblack@eecs.umich.eduCheckerCPU::dumpAndExit() 3566379Sgblack@eecs.umich.edu{ 3576383Sgblack@eecs.umich.edu warn("%lli: Checker PC:%s", 3586378Sgblack@eecs.umich.edu curTick(), thread->pcState()); 3596383Sgblack@eecs.umich.edu panic("Checker found an error!"); 3606379Sgblack@eecs.umich.edu} 3616383Sgblack@eecs.umich.edu