base_dyn_inst.hh revision 5890:bdef71accd68
1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim 29 */ 30 31#ifndef __CPU_BASE_DYN_INST_HH__ 32#define __CPU_BASE_DYN_INST_HH__ 33 34#include <bitset> 35#include <list> 36#include <string> 37 38#include "arch/faults.hh" 39#include "base/fast_alloc.hh" 40#include "base/trace.hh" 41#include "config/full_system.hh" 42#include "cpu/o3/comm.hh" 43#include "cpu/exetrace.hh" 44#include "cpu/inst_seq.hh" 45#include "cpu/op_class.hh" 46#include "cpu/static_inst.hh" 47#include "mem/packet.hh" 48#include "sim/system.hh" 49 50/** 51 * @file 52 * Defines a dynamic instruction context. 53 */ 54 55// Forward declaration. 56class StaticInstPtr; 57 58template <class Impl> 59class BaseDynInst : public FastAlloc, public RefCounted 60{ 61 public: 62 // Typedef for the CPU. 63 typedef typename Impl::CPUType ImplCPU; 64 typedef typename ImplCPU::ImplState ImplState; 65 66 // Logical register index type. 67 typedef TheISA::RegIndex RegIndex; 68 // Integer register type. 69 typedef TheISA::IntReg IntReg; 70 // Floating point register type. 71 typedef TheISA::FloatReg FloatReg; 72 73 // The DynInstPtr type. 74 typedef typename Impl::DynInstPtr DynInstPtr; 75 76 // The list of instructions iterator type. 77 typedef typename std::list<DynInstPtr>::iterator ListIt; 78 79 enum { 80 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, /// Max source regs 81 MaxInstDestRegs = TheISA::MaxInstDestRegs, /// Max dest regs 82 }; 83 84 /** The StaticInst used by this BaseDynInst. */ 85 StaticInstPtr staticInst; 86 87 //////////////////////////////////////////// 88 // 89 // INSTRUCTION EXECUTION 90 // 91 //////////////////////////////////////////// 92 /** InstRecord that tracks this instructions. */ 93 Trace::InstRecord *traceData; 94 95 void demapPage(Addr vaddr, uint64_t asn) 96 { 97 cpu->demapPage(vaddr, asn); 98 } 99 void demapInstPage(Addr vaddr, uint64_t asn) 100 { 101 cpu->demapPage(vaddr, asn); 102 } 103 void demapDataPage(Addr vaddr, uint64_t asn) 104 { 105 cpu->demapPage(vaddr, asn); 106 } 107 108 /** 109 * Does a read to a given address. 110 * @param addr The address to read. 111 * @param data The read's data is written into this parameter. 112 * @param flags The request's flags. 113 * @return Returns any fault due to the read. 114 */ 115 template <class T> 116 Fault read(Addr addr, T &data, unsigned flags); 117 118 /** 119 * Does a write to a given address. 120 * @param data The data to be written. 121 * @param addr The address to write to. 122 * @param flags The request's flags. 123 * @param res The result of the write (for load locked/store conditionals). 124 * @return Returns any fault due to the write. 125 */ 126 template <class T> 127 Fault write(T data, Addr addr, unsigned flags, 128 uint64_t *res); 129 130 void prefetch(Addr addr, unsigned flags); 131 void writeHint(Addr addr, int size, unsigned flags); 132 Fault copySrcTranslate(Addr src); 133 Fault copy(Addr dest); 134 135 /** @todo: Consider making this private. */ 136 public: 137 /** The sequence number of the instruction. */ 138 InstSeqNum seqNum; 139 140 enum Status { 141 IqEntry, /// Instruction is in the IQ 142 RobEntry, /// Instruction is in the ROB 143 LsqEntry, /// Instruction is in the LSQ 144 Completed, /// Instruction has completed 145 ResultReady, /// Instruction has its result 146 CanIssue, /// Instruction can issue and execute 147 Issued, /// Instruction has issued 148 Executed, /// Instruction has executed 149 CanCommit, /// Instruction can commit 150 AtCommit, /// Instruction has reached commit 151 Committed, /// Instruction has committed 152 Squashed, /// Instruction is squashed 153 SquashedInIQ, /// Instruction is squashed in the IQ 154 SquashedInLSQ, /// Instruction is squashed in the LSQ 155 SquashedInROB, /// Instruction is squashed in the ROB 156 RecoverInst, /// Is a recover instruction 157 BlockingInst, /// Is a blocking instruction 158 ThreadsyncWait, /// Is a thread synchronization instruction 159 SerializeBefore, /// Needs to serialize on 160 /// instructions ahead of it 161 SerializeAfter, /// Needs to serialize instructions behind it 162 SerializeHandled, /// Serialization has been handled 163 NumStatus 164 }; 165 166 /** The status of this BaseDynInst. Several bits can be set. */ 167 std::bitset<NumStatus> status; 168 169 /** The thread this instruction is from. */ 170 short threadNumber; 171 172 /** data address space ID, for loads & stores. */ 173 short asid; 174 175 /** How many source registers are ready. */ 176 unsigned readyRegs; 177 178 /** Pointer to the Impl's CPU object. */ 179 ImplCPU *cpu; 180 181 /** Pointer to the thread state. */ 182 ImplState *thread; 183 184 /** The kind of fault this instruction has generated. */ 185 Fault fault; 186 187 /** Pointer to the data for the memory access. */ 188 uint8_t *memData; 189 190 /** The effective virtual address (lds & stores only). */ 191 Addr effAddr; 192 193 /** Is the effective virtual address valid. */ 194 bool effAddrValid; 195 196 /** The effective physical address. */ 197 Addr physEffAddr; 198 199 /** Effective virtual address for a copy source. */ 200 Addr copySrcEffAddr; 201 202 /** Effective physical address for a copy source. */ 203 Addr copySrcPhysEffAddr; 204 205 /** The memory request flags (from translation). */ 206 unsigned memReqFlags; 207 208 union Result { 209 uint64_t integer; 210// float fp; 211 double dbl; 212 }; 213 214 /** The result of the instruction; assumes for now that there's only one 215 * destination register. 216 */ 217 Result instResult; 218 219 /** Records changes to result? */ 220 bool recordResult; 221 222 /** PC of this instruction. */ 223 Addr PC; 224 225 /** Micro PC of this instruction. */ 226 Addr microPC; 227 228 protected: 229 /** Next non-speculative PC. It is not filled in at fetch, but rather 230 * once the target of the branch is truly known (either decode or 231 * execute). 232 */ 233 Addr nextPC; 234 235 /** Next non-speculative NPC. Target PC for Mips or Sparc. */ 236 Addr nextNPC; 237 238 /** Next non-speculative micro PC. */ 239 Addr nextMicroPC; 240 241 /** Predicted next PC. */ 242 Addr predPC; 243 244 /** Predicted next NPC. */ 245 Addr predNPC; 246 247 /** Predicted next microPC */ 248 Addr predMicroPC; 249 250 /** If this is a branch that was predicted taken */ 251 bool predTaken; 252 253 public: 254 255#ifdef DEBUG 256 void dumpSNList(); 257#endif 258 259 /** Whether or not the source register is ready. 260 * @todo: Not sure this should be here vs the derived class. 261 */ 262 bool _readySrcRegIdx[MaxInstSrcRegs]; 263 264 protected: 265 /** Flattened register index of the destination registers of this 266 * instruction. 267 */ 268 TheISA::RegIndex _flatDestRegIdx[TheISA::MaxInstDestRegs]; 269 270 /** Flattened register index of the source registers of this 271 * instruction. 272 */ 273 TheISA::RegIndex _flatSrcRegIdx[TheISA::MaxInstSrcRegs]; 274 275 /** Physical register index of the destination registers of this 276 * instruction. 277 */ 278 PhysRegIndex _destRegIdx[TheISA::MaxInstDestRegs]; 279 280 /** Physical register index of the source registers of this 281 * instruction. 282 */ 283 PhysRegIndex _srcRegIdx[TheISA::MaxInstSrcRegs]; 284 285 /** Physical register index of the previous producers of the 286 * architected destinations. 287 */ 288 PhysRegIndex _prevDestRegIdx[TheISA::MaxInstDestRegs]; 289 290 public: 291 292 /** Returns the physical register index of the i'th destination 293 * register. 294 */ 295 PhysRegIndex renamedDestRegIdx(int idx) const 296 { 297 return _destRegIdx[idx]; 298 } 299 300 /** Returns the physical register index of the i'th source register. */ 301 PhysRegIndex renamedSrcRegIdx(int idx) const 302 { 303 return _srcRegIdx[idx]; 304 } 305 306 /** Returns the flattened register index of the i'th destination 307 * register. 308 */ 309 TheISA::RegIndex flattenedDestRegIdx(int idx) const 310 { 311 return _flatDestRegIdx[idx]; 312 } 313 314 /** Returns the flattened register index of the i'th source register */ 315 TheISA::RegIndex flattenedSrcRegIdx(int idx) const 316 { 317 return _flatSrcRegIdx[idx]; 318 } 319 320 /** Returns the physical register index of the previous physical register 321 * that remapped to the same logical register index. 322 */ 323 PhysRegIndex prevDestRegIdx(int idx) const 324 { 325 return _prevDestRegIdx[idx]; 326 } 327 328 /** Renames a destination register to a physical register. Also records 329 * the previous physical register that the logical register mapped to. 330 */ 331 void renameDestReg(int idx, 332 PhysRegIndex renamed_dest, 333 PhysRegIndex previous_rename) 334 { 335 _destRegIdx[idx] = renamed_dest; 336 _prevDestRegIdx[idx] = previous_rename; 337 } 338 339 /** Renames a source logical register to the physical register which 340 * has/will produce that logical register's result. 341 * @todo: add in whether or not the source register is ready. 342 */ 343 void renameSrcReg(int idx, PhysRegIndex renamed_src) 344 { 345 _srcRegIdx[idx] = renamed_src; 346 } 347 348 /** Flattens a source architectural register index into a logical index. 349 */ 350 void flattenSrcReg(int idx, TheISA::RegIndex flattened_src) 351 { 352 _flatSrcRegIdx[idx] = flattened_src; 353 } 354 355 /** Flattens a destination architectural register index into a logical 356 * index. 357 */ 358 void flattenDestReg(int idx, TheISA::RegIndex flattened_dest) 359 { 360 _flatDestRegIdx[idx] = flattened_dest; 361 } 362 /** BaseDynInst constructor given a binary instruction. 363 * @param staticInst A StaticInstPtr to the underlying instruction. 364 * @param PC The PC of the instruction. 365 * @param pred_PC The predicted next PC. 366 * @param pred_NPC The predicted next NPC. 367 * @param seq_num The sequence number of the instruction. 368 * @param cpu Pointer to the instruction's CPU. 369 */ 370 BaseDynInst(StaticInstPtr staticInst, Addr PC, Addr NPC, Addr microPC, 371 Addr pred_PC, Addr pred_NPC, Addr pred_MicroPC, 372 InstSeqNum seq_num, ImplCPU *cpu); 373 374 /** BaseDynInst constructor given a binary instruction. 375 * @param inst The binary instruction. 376 * @param PC The PC of the instruction. 377 * @param pred_PC The predicted next PC. 378 * @param pred_NPC The predicted next NPC. 379 * @param seq_num The sequence number of the instruction. 380 * @param cpu Pointer to the instruction's CPU. 381 */ 382 BaseDynInst(TheISA::ExtMachInst inst, Addr PC, Addr NPC, Addr microPC, 383 Addr pred_PC, Addr pred_NPC, Addr pred_MicroPC, 384 InstSeqNum seq_num, ImplCPU *cpu); 385 386 /** BaseDynInst constructor given a StaticInst pointer. 387 * @param _staticInst The StaticInst for this BaseDynInst. 388 */ 389 BaseDynInst(StaticInstPtr &_staticInst); 390 391 /** BaseDynInst destructor. */ 392 ~BaseDynInst(); 393 394 private: 395 /** Function to initialize variables in the constructors. */ 396 void initVars(); 397 398 public: 399 /** Dumps out contents of this BaseDynInst. */ 400 void dump(); 401 402 /** Dumps out contents of this BaseDynInst into given string. */ 403 void dump(std::string &outstring); 404 405 /** Read this CPU's ID. */ 406 int cpuId() { return cpu->cpuId(); } 407 408 /** Read this context's system-wide ID **/ 409 int contextId() { return thread->contextId(); } 410 411 /** Returns the fault type. */ 412 Fault getFault() { return fault; } 413 414 /** Checks whether or not this instruction has had its branch target 415 * calculated yet. For now it is not utilized and is hacked to be 416 * always false. 417 * @todo: Actually use this instruction. 418 */ 419 bool doneTargCalc() { return false; } 420 421 /** Returns the next PC. This could be the speculative next PC if it is 422 * called prior to the actual branch target being calculated. 423 */ 424 Addr readNextPC() { return nextPC; } 425 426 /** Returns the next NPC. This could be the speculative next NPC if it is 427 * called prior to the actual branch target being calculated. 428 */ 429 Addr readNextNPC() 430 { 431#if ISA_HAS_DELAY_SLOT 432 return nextNPC; 433#else 434 return nextPC + sizeof(TheISA::MachInst); 435#endif 436 } 437 438 Addr readNextMicroPC() 439 { 440 return nextMicroPC; 441 } 442 443 /** Set the predicted target of this current instruction. */ 444 void setPredTarg(Addr predicted_PC, Addr predicted_NPC, 445 Addr predicted_MicroPC) 446 { 447 predPC = predicted_PC; 448 predNPC = predicted_NPC; 449 predMicroPC = predicted_MicroPC; 450 } 451 452 /** Returns the predicted PC immediately after the branch. */ 453 Addr readPredPC() { return predPC; } 454 455 /** Returns the predicted PC two instructions after the branch */ 456 Addr readPredNPC() { return predNPC; } 457 458 /** Returns the predicted micro PC after the branch */ 459 Addr readPredMicroPC() { return predMicroPC; } 460 461 /** Returns whether the instruction was predicted taken or not. */ 462 bool readPredTaken() 463 { 464 return predTaken; 465 } 466 467 void setPredTaken(bool predicted_taken) 468 { 469 predTaken = predicted_taken; 470 } 471 472 /** Returns whether the instruction mispredicted. */ 473 bool mispredicted() 474 { 475 return readPredPC() != readNextPC() || 476 readPredNPC() != readNextNPC() || 477 readPredMicroPC() != readNextMicroPC(); 478 } 479 480 // 481 // Instruction types. Forward checks to StaticInst object. 482 // 483 bool isNop() const { return staticInst->isNop(); } 484 bool isMemRef() const { return staticInst->isMemRef(); } 485 bool isLoad() const { return staticInst->isLoad(); } 486 bool isStore() const { return staticInst->isStore(); } 487 bool isStoreConditional() const 488 { return staticInst->isStoreConditional(); } 489 bool isInstPrefetch() const { return staticInst->isInstPrefetch(); } 490 bool isDataPrefetch() const { return staticInst->isDataPrefetch(); } 491 bool isCopy() const { return staticInst->isCopy(); } 492 bool isInteger() const { return staticInst->isInteger(); } 493 bool isFloating() const { return staticInst->isFloating(); } 494 bool isControl() const { return staticInst->isControl(); } 495 bool isCall() const { return staticInst->isCall(); } 496 bool isReturn() const { return staticInst->isReturn(); } 497 bool isDirectCtrl() const { return staticInst->isDirectCtrl(); } 498 bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); } 499 bool isCondCtrl() const { return staticInst->isCondCtrl(); } 500 bool isUncondCtrl() const { return staticInst->isUncondCtrl(); } 501 bool isCondDelaySlot() const { return staticInst->isCondDelaySlot(); } 502 bool isThreadSync() const { return staticInst->isThreadSync(); } 503 bool isSerializing() const { return staticInst->isSerializing(); } 504 bool isSerializeBefore() const 505 { return staticInst->isSerializeBefore() || status[SerializeBefore]; } 506 bool isSerializeAfter() const 507 { return staticInst->isSerializeAfter() || status[SerializeAfter]; } 508 bool isMemBarrier() const { return staticInst->isMemBarrier(); } 509 bool isWriteBarrier() const { return staticInst->isWriteBarrier(); } 510 bool isNonSpeculative() const { return staticInst->isNonSpeculative(); } 511 bool isQuiesce() const { return staticInst->isQuiesce(); } 512 bool isIprAccess() const { return staticInst->isIprAccess(); } 513 bool isUnverifiable() const { return staticInst->isUnverifiable(); } 514 bool isSyscall() const { return staticInst->isSyscall(); } 515 bool isMacroop() const { return staticInst->isMacroop(); } 516 bool isMicroop() const { return staticInst->isMicroop(); } 517 bool isDelayedCommit() const { return staticInst->isDelayedCommit(); } 518 bool isLastMicroop() const { return staticInst->isLastMicroop(); } 519 bool isFirstMicroop() const { return staticInst->isFirstMicroop(); } 520 bool isMicroBranch() const { return staticInst->isMicroBranch(); } 521 522 /** Temporarily sets this instruction as a serialize before instruction. */ 523 void setSerializeBefore() { status.set(SerializeBefore); } 524 525 /** Clears the serializeBefore part of this instruction. */ 526 void clearSerializeBefore() { status.reset(SerializeBefore); } 527 528 /** Checks if this serializeBefore is only temporarily set. */ 529 bool isTempSerializeBefore() { return status[SerializeBefore]; } 530 531 /** Temporarily sets this instruction as a serialize after instruction. */ 532 void setSerializeAfter() { status.set(SerializeAfter); } 533 534 /** Clears the serializeAfter part of this instruction.*/ 535 void clearSerializeAfter() { status.reset(SerializeAfter); } 536 537 /** Checks if this serializeAfter is only temporarily set. */ 538 bool isTempSerializeAfter() { return status[SerializeAfter]; } 539 540 /** Sets the serialization part of this instruction as handled. */ 541 void setSerializeHandled() { status.set(SerializeHandled); } 542 543 /** Checks if the serialization part of this instruction has been 544 * handled. This does not apply to the temporary serializing 545 * state; it only applies to this instruction's own permanent 546 * serializing state. 547 */ 548 bool isSerializeHandled() { return status[SerializeHandled]; } 549 550 /** Returns the opclass of this instruction. */ 551 OpClass opClass() const { return staticInst->opClass(); } 552 553 /** Returns the branch target address. */ 554 Addr branchTarget() const { return staticInst->branchTarget(PC); } 555 556 /** Returns the number of source registers. */ 557 int8_t numSrcRegs() const { return staticInst->numSrcRegs(); } 558 559 /** Returns the number of destination registers. */ 560 int8_t numDestRegs() const { return staticInst->numDestRegs(); } 561 562 // the following are used to track physical register usage 563 // for machines with separate int & FP reg files 564 int8_t numFPDestRegs() const { return staticInst->numFPDestRegs(); } 565 int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); } 566 567 /** Returns the logical register index of the i'th destination register. */ 568 RegIndex destRegIdx(int i) const { return staticInst->destRegIdx(i); } 569 570 /** Returns the logical register index of the i'th source register. */ 571 RegIndex srcRegIdx(int i) const { return staticInst->srcRegIdx(i); } 572 573 /** Returns the result of an integer instruction. */ 574 uint64_t readIntResult() { return instResult.integer; } 575 576 /** Returns the result of a floating point instruction. */ 577 float readFloatResult() { return (float)instResult.dbl; } 578 579 /** Returns the result of a floating point (double) instruction. */ 580 double readDoubleResult() { return instResult.dbl; } 581 582 /** Records an integer register being set to a value. */ 583 void setIntRegOperand(const StaticInst *si, int idx, uint64_t val) 584 { 585 if (recordResult) 586 instResult.integer = val; 587 } 588 589 /** Records an fp register being set to a value. */ 590 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val, 591 int width) 592 { 593 if (recordResult) { 594 if (width == 32) 595 instResult.dbl = (double)val; 596 else if (width == 64) 597 instResult.dbl = val; 598 else 599 panic("Unsupported width!"); 600 } 601 } 602 603 /** Records an fp register being set to a value. */ 604 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val) 605 { 606 if (recordResult) 607 instResult.dbl = (double)val; 608 } 609 610 /** Records an fp register being set to an integer value. */ 611 void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val, 612 int width) 613 { 614 if (recordResult) 615 instResult.integer = val; 616 } 617 618 /** Records an fp register being set to an integer value. */ 619 void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val) 620 { 621 if (recordResult) 622 instResult.integer = val; 623 } 624 625 /** Records that one of the source registers is ready. */ 626 void markSrcRegReady(); 627 628 /** Marks a specific register as ready. */ 629 void markSrcRegReady(RegIndex src_idx); 630 631 /** Returns if a source register is ready. */ 632 bool isReadySrcRegIdx(int idx) const 633 { 634 return this->_readySrcRegIdx[idx]; 635 } 636 637 /** Sets this instruction as completed. */ 638 void setCompleted() { status.set(Completed); } 639 640 /** Returns whether or not this instruction is completed. */ 641 bool isCompleted() const { return status[Completed]; } 642 643 /** Marks the result as ready. */ 644 void setResultReady() { status.set(ResultReady); } 645 646 /** Returns whether or not the result is ready. */ 647 bool isResultReady() const { return status[ResultReady]; } 648 649 /** Sets this instruction as ready to issue. */ 650 void setCanIssue() { status.set(CanIssue); } 651 652 /** Returns whether or not this instruction is ready to issue. */ 653 bool readyToIssue() const { return status[CanIssue]; } 654 655 /** Clears this instruction being able to issue. */ 656 void clearCanIssue() { status.reset(CanIssue); } 657 658 /** Sets this instruction as issued from the IQ. */ 659 void setIssued() { status.set(Issued); } 660 661 /** Returns whether or not this instruction has issued. */ 662 bool isIssued() const { return status[Issued]; } 663 664 /** Clears this instruction as being issued. */ 665 void clearIssued() { status.reset(Issued); } 666 667 /** Sets this instruction as executed. */ 668 void setExecuted() { status.set(Executed); } 669 670 /** Returns whether or not this instruction has executed. */ 671 bool isExecuted() const { return status[Executed]; } 672 673 /** Sets this instruction as ready to commit. */ 674 void setCanCommit() { status.set(CanCommit); } 675 676 /** Clears this instruction as being ready to commit. */ 677 void clearCanCommit() { status.reset(CanCommit); } 678 679 /** Returns whether or not this instruction is ready to commit. */ 680 bool readyToCommit() const { return status[CanCommit]; } 681 682 void setAtCommit() { status.set(AtCommit); } 683 684 bool isAtCommit() { return status[AtCommit]; } 685 686 /** Sets this instruction as committed. */ 687 void setCommitted() { status.set(Committed); } 688 689 /** Returns whether or not this instruction is committed. */ 690 bool isCommitted() const { return status[Committed]; } 691 692 /** Sets this instruction as squashed. */ 693 void setSquashed() { status.set(Squashed); } 694 695 /** Returns whether or not this instruction is squashed. */ 696 bool isSquashed() const { return status[Squashed]; } 697 698 //Instruction Queue Entry 699 //----------------------- 700 /** Sets this instruction as a entry the IQ. */ 701 void setInIQ() { status.set(IqEntry); } 702 703 /** Sets this instruction as a entry the IQ. */ 704 void clearInIQ() { status.reset(IqEntry); } 705 706 /** Returns whether or not this instruction has issued. */ 707 bool isInIQ() const { return status[IqEntry]; } 708 709 /** Sets this instruction as squashed in the IQ. */ 710 void setSquashedInIQ() { status.set(SquashedInIQ); status.set(Squashed);} 711 712 /** Returns whether or not this instruction is squashed in the IQ. */ 713 bool isSquashedInIQ() const { return status[SquashedInIQ]; } 714 715 716 //Load / Store Queue Functions 717 //----------------------- 718 /** Sets this instruction as a entry the LSQ. */ 719 void setInLSQ() { status.set(LsqEntry); } 720 721 /** Sets this instruction as a entry the LSQ. */ 722 void removeInLSQ() { status.reset(LsqEntry); } 723 724 /** Returns whether or not this instruction is in the LSQ. */ 725 bool isInLSQ() const { return status[LsqEntry]; } 726 727 /** Sets this instruction as squashed in the LSQ. */ 728 void setSquashedInLSQ() { status.set(SquashedInLSQ);} 729 730 /** Returns whether or not this instruction is squashed in the LSQ. */ 731 bool isSquashedInLSQ() const { return status[SquashedInLSQ]; } 732 733 734 //Reorder Buffer Functions 735 //----------------------- 736 /** Sets this instruction as a entry the ROB. */ 737 void setInROB() { status.set(RobEntry); } 738 739 /** Sets this instruction as a entry the ROB. */ 740 void clearInROB() { status.reset(RobEntry); } 741 742 /** Returns whether or not this instruction is in the ROB. */ 743 bool isInROB() const { return status[RobEntry]; } 744 745 /** Sets this instruction as squashed in the ROB. */ 746 void setSquashedInROB() { status.set(SquashedInROB); } 747 748 /** Returns whether or not this instruction is squashed in the ROB. */ 749 bool isSquashedInROB() const { return status[SquashedInROB]; } 750 751 /** Read the PC of this instruction. */ 752 const Addr readPC() const { return PC; } 753 754 /**Read the micro PC of this instruction. */ 755 const Addr readMicroPC() const { return microPC; } 756 757 /** Set the next PC of this instruction (its actual target). */ 758 void setNextPC(Addr val) 759 { 760 nextPC = val; 761 } 762 763 /** Set the next NPC of this instruction (the target in Mips or Sparc).*/ 764 void setNextNPC(Addr val) 765 { 766#if ISA_HAS_DELAY_SLOT 767 nextNPC = val; 768#endif 769 } 770 771 void setNextMicroPC(Addr val) 772 { 773 nextMicroPC = val; 774 } 775 776 /** Sets the ASID. */ 777 void setASID(short addr_space_id) { asid = addr_space_id; } 778 779 /** Sets the thread id. */ 780 void setTid(unsigned tid) { threadNumber = tid; } 781 782 /** Sets the pointer to the thread state. */ 783 void setThreadState(ImplState *state) { thread = state; } 784 785 /** Returns the thread context. */ 786 ThreadContext *tcBase() { return thread->getTC(); } 787 788 private: 789 /** Instruction effective address. 790 * @todo: Consider if this is necessary or not. 791 */ 792 Addr instEffAddr; 793 794 /** Whether or not the effective address calculation is completed. 795 * @todo: Consider if this is necessary or not. 796 */ 797 bool eaCalcDone; 798 799 /** Is this instruction's memory access uncacheable. */ 800 bool isUncacheable; 801 802 /** Has this instruction generated a memory request. */ 803 bool reqMade; 804 805 public: 806 /** Sets the effective address. */ 807 void setEA(Addr &ea) { instEffAddr = ea; eaCalcDone = true; } 808 809 /** Returns the effective address. */ 810 const Addr &getEA() const { return instEffAddr; } 811 812 /** Returns whether or not the eff. addr. calculation has been completed. */ 813 bool doneEACalc() { return eaCalcDone; } 814 815 /** Returns whether or not the eff. addr. source registers are ready. */ 816 bool eaSrcsReady(); 817 818 /** Whether or not the memory operation is done. */ 819 bool memOpDone; 820 821 /** Is this instruction's memory access uncacheable. */ 822 bool uncacheable() { return isUncacheable; } 823 824 /** Has this instruction generated a memory request. */ 825 bool hasRequest() { return reqMade; } 826 827 public: 828 /** Load queue index. */ 829 int16_t lqIdx; 830 831 /** Store queue index. */ 832 int16_t sqIdx; 833 834 /** Iterator pointing to this BaseDynInst in the list of all insts. */ 835 ListIt instListIt; 836 837 /** Returns iterator to this instruction in the list of all insts. */ 838 ListIt &getInstListIt() { return instListIt; } 839 840 /** Sets iterator for this instruction in the list of all insts. */ 841 void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; } 842 843 public: 844 /** Returns the number of consecutive store conditional failures. */ 845 unsigned readStCondFailures() 846 { return thread->storeCondFailures; } 847 848 /** Sets the number of consecutive store conditional failures. */ 849 void setStCondFailures(unsigned sc_failures) 850 { thread->storeCondFailures = sc_failures; } 851}; 852 853template<class Impl> 854template<class T> 855inline Fault 856BaseDynInst<Impl>::read(Addr addr, T &data, unsigned flags) 857{ 858 reqMade = true; 859 Request *req = new Request(); 860 req->setVirt(asid, addr, sizeof(T), flags, this->PC); 861 req->setThreadContext(thread->contextId(), threadNumber); 862 863 fault = cpu->dtb->translate(req, thread->getTC(), false); 864 865 if (req->isUncacheable()) 866 isUncacheable = true; 867 868 if (fault == NoFault) { 869 effAddr = req->getVaddr(); 870 effAddrValid = true; 871 physEffAddr = req->getPaddr(); 872 memReqFlags = req->getFlags(); 873 874#if 0 875 if (cpu->system->memctrl->badaddr(physEffAddr)) { 876 fault = TheISA::genMachineCheckFault(); 877 data = (T)-1; 878 this->setExecuted(); 879 } else { 880 fault = cpu->read(req, data, lqIdx); 881 } 882#else 883 fault = cpu->read(req, data, lqIdx); 884#endif 885 } else { 886 // Return a fixed value to keep simulation deterministic even 887 // along misspeculated paths. 888 data = (T)-1; 889 890 // Commit will have to clean up whatever happened. Set this 891 // instruction as executed. 892 this->setExecuted(); 893 delete req; 894 } 895 896 if (traceData) { 897 traceData->setAddr(addr); 898 traceData->setData(data); 899 } 900 901 return fault; 902} 903 904template<class Impl> 905template<class T> 906inline Fault 907BaseDynInst<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res) 908{ 909 if (traceData) { 910 traceData->setAddr(addr); 911 traceData->setData(data); 912 } 913 914 reqMade = true; 915 Request *req = new Request(); 916 req->setVirt(asid, addr, sizeof(T), flags, this->PC); 917 req->setThreadContext(thread->contextId(), threadNumber); 918 919 fault = cpu->dtb->translate(req, thread->getTC(), true); 920 921 if (req->isUncacheable()) 922 isUncacheable = true; 923 924 if (fault == NoFault) { 925 effAddr = req->getVaddr(); 926 effAddrValid = true; 927 physEffAddr = req->getPaddr(); 928 memReqFlags = req->getFlags(); 929 930 if (req->isCondSwap()) { 931 assert(res); 932 req->setExtraData(*res); 933 } 934#if 0 935 if (cpu->system->memctrl->badaddr(physEffAddr)) { 936 fault = TheISA::genMachineCheckFault(); 937 } else { 938 fault = cpu->write(req, data, sqIdx); 939 } 940#else 941 fault = cpu->write(req, data, sqIdx); 942#endif 943 } else { 944 delete req; 945 } 946 947 return fault; 948} 949 950#endif // __CPU_BASE_DYN_INST_HH__ 951