base_dyn_inst.hh revision 4636 
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31#ifndef __CPU_BASE_DYN_INST_HH__
32#define __CPU_BASE_DYN_INST_HH__
33
34#include <bitset>
35#include <list>
36#include <string>
37
38#include "arch/faults.hh"
39#include "base/fast_alloc.hh"
40#include "base/trace.hh"
41#include "config/full_system.hh"
42#include "cpu/o3/comm.hh"
43#include "cpu/exetrace.hh"
44#include "cpu/inst_seq.hh"
45#include "cpu/op_class.hh"
46#include "cpu/static_inst.hh"
47#include "mem/packet.hh"
48#include "sim/system.hh"
49
50/**
51 * @file
52 * Defines a dynamic instruction context.
53 */
54
55// Forward declaration.
56class StaticInstPtr;
57
58template <class Impl>
59class BaseDynInst : public FastAlloc, public RefCounted
60{
61  public:
62    // Typedef for the CPU.
63    typedef typename Impl::CPUType ImplCPU;
64    typedef typename ImplCPU::ImplState ImplState;
65
66    // Logical register index type.
67    typedef TheISA::RegIndex RegIndex;
68    // Integer register type.
69    typedef TheISA::IntReg IntReg;
70    // Floating point register type.
71    typedef TheISA::FloatReg FloatReg;
72
73    // The DynInstPtr type.
74    typedef typename Impl::DynInstPtr DynInstPtr;
75
76    // The list of instructions iterator type.
77    typedef typename std::list<DynInstPtr>::iterator ListIt;
78
79    enum {
80        MaxInstSrcRegs = TheISA::MaxInstSrcRegs,	/// Max source regs
81        MaxInstDestRegs = TheISA::MaxInstDestRegs,	/// Max dest regs
82    };
83
84    /** The StaticInst used by this BaseDynInst. */
85    StaticInstPtr staticInst;
86
87    ////////////////////////////////////////////
88    //
89    // INSTRUCTION EXECUTION
90    //
91    ////////////////////////////////////////////
92    /** InstRecord that tracks this instructions. */
93    Trace::InstRecord *traceData;
94
95    /**
96     * Does a read to a given address.
97     * @param addr The address to read.
98     * @param data The read's data is written into this parameter.
99     * @param flags The request's flags.
100     * @return Returns any fault due to the read.
101     */
102    template <class T>
103    Fault read(Addr addr, T &data, unsigned flags);
104
105    /**
106     * Does a write to a given address.
107     * @param data The data to be written.
108     * @param addr The address to write to.
109     * @param flags The request's flags.
110     * @param res The result of the write (for load locked/store conditionals).
111     * @return Returns any fault due to the write.
112     */
113    template <class T>
114    Fault write(T data, Addr addr, unsigned flags,
115                        uint64_t *res);
116
117    void prefetch(Addr addr, unsigned flags);
118    void writeHint(Addr addr, int size, unsigned flags);
119    Fault copySrcTranslate(Addr src);
120    Fault copy(Addr dest);
121
122    /** @todo: Consider making this private. */
123  public:
124    /** The sequence number of the instruction. */
125    InstSeqNum seqNum;
126
127    enum Status {
128        IqEntry,                 /// Instruction is in the IQ
129        RobEntry,                /// Instruction is in the ROB
130        LsqEntry,                /// Instruction is in the LSQ
131        Completed,               /// Instruction has completed
132        ResultReady,             /// Instruction has its result
133        CanIssue,                /// Instruction can issue and execute
134        Issued,                  /// Instruction has issued
135        Executed,                /// Instruction has executed
136        CanCommit,               /// Instruction can commit
137        AtCommit,                /// Instruction has reached commit
138        Committed,               /// Instruction has committed
139        Squashed,                /// Instruction is squashed
140        SquashedInIQ,            /// Instruction is squashed in the IQ
141        SquashedInLSQ,           /// Instruction is squashed in the LSQ
142        SquashedInROB,           /// Instruction is squashed in the ROB
143        RecoverInst,             /// Is a recover instruction
144        BlockingInst,            /// Is a blocking instruction
145        ThreadsyncWait,          /// Is a thread synchronization instruction
146        SerializeBefore,         /// Needs to serialize on
147                                 /// instructions ahead of it
148        SerializeAfter,          /// Needs to serialize instructions behind it
149        SerializeHandled,        /// Serialization has been handled
150        NumStatus
151    };
152
153    /** The status of this BaseDynInst.  Several bits can be set. */
154    std::bitset<NumStatus> status;
155
156    /** The thread this instruction is from. */
157    short threadNumber;
158
159    /** data address space ID, for loads & stores. */
160    short asid;
161
162    /** How many source registers are ready. */
163    unsigned readyRegs;
164
165    /** Pointer to the Impl's CPU object. */
166    ImplCPU *cpu;
167
168    /** Pointer to the thread state. */
169    ImplState *thread;
170
171    /** The kind of fault this instruction has generated. */
172    Fault fault;
173
174    /** Pointer to the data for the memory access. */
175    uint8_t *memData;
176
177    /** The effective virtual address (lds & stores only). */
178    Addr effAddr;
179
180    /** Is the effective virtual address valid. */
181    bool effAddrValid;
182
183    /** The effective physical address. */
184    Addr physEffAddr;
185
186    /** Effective virtual address for a copy source. */
187    Addr copySrcEffAddr;
188
189    /** Effective physical address for a copy source. */
190    Addr copySrcPhysEffAddr;
191
192    /** The memory request flags (from translation). */
193    unsigned memReqFlags;
194
195    union Result {
196        uint64_t integer;
197//        float fp;
198        double dbl;
199    };
200
201    /** The result of the instruction; assumes for now that there's only one
202     *  destination register.
203     */
204    Result instResult;
205
206    /** Records changes to result? */
207    bool recordResult;
208
209    /** PC of this instruction. */
210    Addr PC;
211
212    /** Micro PC of this instruction. */
213    Addr microPC;
214
215  protected:
216    /** Next non-speculative PC.  It is not filled in at fetch, but rather
217     *  once the target of the branch is truly known (either decode or
218     *  execute).
219     */
220    Addr nextPC;
221
222    /** Next non-speculative NPC. Target PC for Mips or Sparc. */
223    Addr nextNPC;
224
225    /** Next non-speculative micro PC. */
226    Addr nextMicroPC;
227
228    /** Predicted next PC. */
229    Addr predPC;
230
231    /** Predicted next NPC. */
232    Addr predNPC;
233
234    /** Predicted next microPC */
235    Addr predMicroPC;
236
237    /** If this is a branch that was predicted taken */
238    bool predTaken;
239
240  public:
241
242    /** Count of total number of dynamic instructions. */
243    static int instcount;
244
245#ifdef DEBUG
246    void dumpSNList();
247#endif
248
249    /** Whether or not the source register is ready.
250     *  @todo: Not sure this should be here vs the derived class.
251     */
252    bool _readySrcRegIdx[MaxInstSrcRegs];
253
254  protected:
255    /** Flattened register index of the destination registers of this
256     *  instruction.
257     */
258    TheISA::RegIndex _flatDestRegIdx[TheISA::MaxInstDestRegs];
259
260    /** Flattened register index of the source registers of this
261     *  instruction.
262     */
263    TheISA::RegIndex _flatSrcRegIdx[TheISA::MaxInstSrcRegs];
264
265    /** Physical register index of the destination registers of this
266     *  instruction.
267     */
268    PhysRegIndex _destRegIdx[TheISA::MaxInstDestRegs];
269
270    /** Physical register index of the source registers of this
271     *  instruction.
272     */
273    PhysRegIndex _srcRegIdx[TheISA::MaxInstSrcRegs];
274
275    /** Physical register index of the previous producers of the
276     *  architected destinations.
277     */
278    PhysRegIndex _prevDestRegIdx[TheISA::MaxInstDestRegs];
279
280  public:
281
282    /** Returns the physical register index of the i'th destination
283     *  register.
284     */
285    PhysRegIndex renamedDestRegIdx(int idx) const
286    {
287        return _destRegIdx[idx];
288    }
289
290    /** Returns the physical register index of the i'th source register. */
291    PhysRegIndex renamedSrcRegIdx(int idx) const
292    {
293        return _srcRegIdx[idx];
294    }
295
296    /** Returns the flattened register index of the i'th destination
297     *  register.
298     */
299    TheISA::RegIndex flattenedDestRegIdx(int idx) const
300    {
301        return _flatDestRegIdx[idx];
302    }
303
304    /** Returns the flattened register index of the i'th source register */
305    TheISA::RegIndex flattenedSrcRegIdx(int idx) const
306    {
307        return _flatSrcRegIdx[idx];
308    }
309
310    /** Returns the physical register index of the previous physical register
311     *  that remapped to the same logical register index.
312     */
313    PhysRegIndex prevDestRegIdx(int idx) const
314    {
315        return _prevDestRegIdx[idx];
316    }
317
318    /** Renames a destination register to a physical register.  Also records
319     *  the previous physical register that the logical register mapped to.
320     */
321    void renameDestReg(int idx,
322                       PhysRegIndex renamed_dest,
323                       PhysRegIndex previous_rename)
324    {
325        _destRegIdx[idx] = renamed_dest;
326        _prevDestRegIdx[idx] = previous_rename;
327    }
328
329    /** Renames a source logical register to the physical register which
330     *  has/will produce that logical register's result.
331     *  @todo: add in whether or not the source register is ready.
332     */
333    void renameSrcReg(int idx, PhysRegIndex renamed_src)
334    {
335        _srcRegIdx[idx] = renamed_src;
336    }
337
338    /** Flattens a source architectural register index into a logical index.
339     */
340    void flattenSrcReg(int idx, TheISA::RegIndex flattened_src)
341    {
342        _flatSrcRegIdx[idx] = flattened_src;
343    }
344
345    /** Flattens a destination architectural register index into a logical
346     * index.
347     */
348    void flattenDestReg(int idx, TheISA::RegIndex flattened_dest)
349    {
350        _flatDestRegIdx[idx] = flattened_dest;
351    }
352    /** BaseDynInst constructor given a binary instruction.
353     *  @param staticInst A StaticInstPtr to the underlying instruction.
354     *  @param PC The PC of the instruction.
355     *  @param pred_PC The predicted next PC.
356     *  @param pred_NPC The predicted next NPC.
357     *  @param seq_num The sequence number of the instruction.
358     *  @param cpu Pointer to the instruction's CPU.
359     */
360    BaseDynInst(StaticInstPtr staticInst, Addr PC, Addr NPC, Addr microPC,
361            Addr pred_PC, Addr pred_NPC, Addr pred_MicroPC,
362            InstSeqNum seq_num, ImplCPU *cpu);
363
364    /** BaseDynInst constructor given a binary instruction.
365     *  @param inst The binary instruction.
366     *  @param PC The PC of the instruction.
367     *  @param pred_PC The predicted next PC.
368     *  @param pred_NPC The predicted next NPC.
369     *  @param seq_num The sequence number of the instruction.
370     *  @param cpu Pointer to the instruction's CPU.
371     */
372    BaseDynInst(TheISA::ExtMachInst inst, Addr PC, Addr NPC, Addr microPC,
373            Addr pred_PC, Addr pred_NPC, Addr pred_MicroPC,
374            InstSeqNum seq_num, ImplCPU *cpu);
375
376    /** BaseDynInst constructor given a StaticInst pointer.
377     *  @param _staticInst The StaticInst for this BaseDynInst.
378     */
379    BaseDynInst(StaticInstPtr &_staticInst);
380
381    /** BaseDynInst destructor. */
382    ~BaseDynInst();
383
384  private:
385    /** Function to initialize variables in the constructors. */
386    void initVars();
387
388  public:
389    /** Dumps out contents of this BaseDynInst. */
390    void dump();
391
392    /** Dumps out contents of this BaseDynInst into given string. */
393    void dump(std::string &outstring);
394
395    /** Read this CPU's ID. */
396    int readCpuId() { return cpu->readCpuId(); }
397
398    /** Returns the fault type. */
399    Fault getFault() { return fault; }
400
401    /** Checks whether or not this instruction has had its branch target
402     *  calculated yet.  For now it is not utilized and is hacked to be
403     *  always false.
404     *  @todo: Actually use this instruction.
405     */
406    bool doneTargCalc() { return false; }
407
408    /** Returns the next PC.  This could be the speculative next PC if it is
409     *  called prior to the actual branch target being calculated.
410     */
411    Addr readNextPC() { return nextPC; }
412
413    /** Returns the next NPC.  This could be the speculative next NPC if it is
414     *  called prior to the actual branch target being calculated.
415     */
416    Addr readNextNPC()
417    {
418#if ISA_HAS_DELAY_SLOT
419        return nextNPC;
420#else
421        return nextPC + sizeof(TheISA::MachInst);
422#endif
423    }
424
425    Addr readNextMicroPC()
426    {
427        return nextMicroPC;
428    }
429
430    /** Set the predicted target of this current instruction. */
431    void setPredTarg(Addr predicted_PC, Addr predicted_NPC,
432            Addr predicted_MicroPC)
433    {
434        predPC = predicted_PC;
435        predNPC = predicted_NPC;
436        predMicroPC = predicted_MicroPC;
437    }
438
439    /** Returns the predicted PC immediately after the branch. */
440    Addr readPredPC() { return predPC; }
441
442    /** Returns the predicted PC two instructions after the branch */
443    Addr readPredNPC() { return predNPC; }
444
445    /** Returns the predicted micro PC after the branch */
446    Addr readPredMicroPC() { return predMicroPC; }
447
448    /** Returns whether the instruction was predicted taken or not. */
449    bool readPredTaken()
450    {
451        return predTaken;
452    }
453
454    void setPredTaken(bool predicted_taken)
455    {
456        predTaken = predicted_taken;
457    }
458
459    /** Returns whether the instruction mispredicted. */
460    bool mispredicted()
461    {
462        return readPredPC() != readNextPC() ||
463            readPredNPC() != readNextNPC() ||
464            readPredMicroPC() != readNextMicroPC();
465    }
466
467    //
468    //  Instruction types.  Forward checks to StaticInst object.
469    //
470    bool isNop()	  const { return staticInst->isNop(); }
471    bool isMemRef()    	  const { return staticInst->isMemRef(); }
472    bool isLoad()	  const { return staticInst->isLoad(); }
473    bool isStore()	  const { return staticInst->isStore(); }
474    bool isStoreConditional() const
475    { return staticInst->isStoreConditional(); }
476    bool isInstPrefetch() const { return staticInst->isInstPrefetch(); }
477    bool isDataPrefetch() const { return staticInst->isDataPrefetch(); }
478    bool isCopy()         const { return staticInst->isCopy(); }
479    bool isInteger()	  const { return staticInst->isInteger(); }
480    bool isFloating()	  const { return staticInst->isFloating(); }
481    bool isControl()	  const { return staticInst->isControl(); }
482    bool isCall()	  const { return staticInst->isCall(); }
483    bool isReturn()	  const { return staticInst->isReturn(); }
484    bool isDirectCtrl()	  const { return staticInst->isDirectCtrl(); }
485    bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); }
486    bool isCondCtrl()	  const { return staticInst->isCondCtrl(); }
487    bool isUncondCtrl()	  const { return staticInst->isUncondCtrl(); }
488    bool isCondDelaySlot() const { return staticInst->isCondDelaySlot(); }
489    bool isThreadSync()   const { return staticInst->isThreadSync(); }
490    bool isSerializing()  const { return staticInst->isSerializing(); }
491    bool isSerializeBefore() const
492    { return staticInst->isSerializeBefore() || status[SerializeBefore]; }
493    bool isSerializeAfter() const
494    { return staticInst->isSerializeAfter() || status[SerializeAfter]; }
495    bool isMemBarrier()   const { return staticInst->isMemBarrier(); }
496    bool isWriteBarrier() const { return staticInst->isWriteBarrier(); }
497    bool isNonSpeculative() const { return staticInst->isNonSpeculative(); }
498    bool isQuiesce() const { return staticInst->isQuiesce(); }
499    bool isIprAccess() const { return staticInst->isIprAccess(); }
500    bool isUnverifiable() const { return staticInst->isUnverifiable(); }
501    bool isMacroOp() const { return staticInst->isMacroOp(); }
502    bool isMicroOp() const { return staticInst->isMicroOp(); }
503    bool isDelayedCommit() const { return staticInst->isDelayedCommit(); }
504    bool isLastMicroOp() const { return staticInst->isLastMicroOp(); }
505    bool isFirstMicroOp() const { return staticInst->isFirstMicroOp(); }
506    bool isMicroBranch() const { return staticInst->isMicroBranch(); }
507
508    /** Temporarily sets this instruction as a serialize before instruction. */
509    void setSerializeBefore() { status.set(SerializeBefore); }
510
511    /** Clears the serializeBefore part of this instruction. */
512    void clearSerializeBefore() { status.reset(SerializeBefore); }
513
514    /** Checks if this serializeBefore is only temporarily set. */
515    bool isTempSerializeBefore() { return status[SerializeBefore]; }
516
517    /** Temporarily sets this instruction as a serialize after instruction. */
518    void setSerializeAfter() { status.set(SerializeAfter); }
519
520    /** Clears the serializeAfter part of this instruction.*/
521    void clearSerializeAfter() { status.reset(SerializeAfter); }
522
523    /** Checks if this serializeAfter is only temporarily set. */
524    bool isTempSerializeAfter() { return status[SerializeAfter]; }
525
526    /** Sets the serialization part of this instruction as handled. */
527    void setSerializeHandled() { status.set(SerializeHandled); }
528
529    /** Checks if the serialization part of this instruction has been
530     *  handled.  This does not apply to the temporary serializing
531     *  state; it only applies to this instruction's own permanent
532     *  serializing state.
533     */
534    bool isSerializeHandled() { return status[SerializeHandled]; }
535
536    /** Returns the opclass of this instruction. */
537    OpClass opClass() const { return staticInst->opClass(); }
538
539    /** Returns the branch target address. */
540    Addr branchTarget() const { return staticInst->branchTarget(PC); }
541
542    /** Returns the number of source registers. */
543    int8_t numSrcRegs()	const { return staticInst->numSrcRegs(); }
544
545    /** Returns the number of destination registers. */
546    int8_t numDestRegs() const { return staticInst->numDestRegs(); }
547
548    // the following are used to track physical register usage
549    // for machines with separate int & FP reg files
550    int8_t numFPDestRegs()  const { return staticInst->numFPDestRegs(); }
551    int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); }
552
553    /** Returns the logical register index of the i'th destination register. */
554    RegIndex destRegIdx(int i) const { return staticInst->destRegIdx(i); }
555
556    /** Returns the logical register index of the i'th source register. */
557    RegIndex srcRegIdx(int i) const { return staticInst->srcRegIdx(i); }
558
559    /** Returns the result of an integer instruction. */
560    uint64_t readIntResult() { return instResult.integer; }
561
562    /** Returns the result of a floating point instruction. */
563    float readFloatResult() { return (float)instResult.dbl; }
564
565    /** Returns the result of a floating point (double) instruction. */
566    double readDoubleResult() { return instResult.dbl; }
567
568    /** Records an integer register being set to a value. */
569    void setIntRegOperand(const StaticInst *si, int idx, uint64_t val)
570    {
571        if (recordResult)
572            instResult.integer = val;
573    }
574
575    /** Records an fp register being set to a value. */
576    void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val,
577                            int width)
578    {
579        if (recordResult) {
580            if (width == 32)
581                instResult.dbl = (double)val;
582            else if (width == 64)
583                instResult.dbl = val;
584            else
585                panic("Unsupported width!");
586        }
587    }
588
589    /** Records an fp register being set to a value. */
590    void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
591    {
592        if (recordResult)
593            instResult.dbl = (double)val;
594    }
595
596    /** Records an fp register being set to an integer value. */
597    void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val,
598                                int width)
599    {
600        if (recordResult)
601            instResult.integer = val;
602    }
603
604    /** Records an fp register being set to an integer value. */
605    void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val)
606    {
607        if (recordResult)
608            instResult.integer = val;
609    }
610
611    /** Records that one of the source registers is ready. */
612    void markSrcRegReady();
613
614    /** Marks a specific register as ready. */
615    void markSrcRegReady(RegIndex src_idx);
616
617    /** Returns if a source register is ready. */
618    bool isReadySrcRegIdx(int idx) const
619    {
620        return this->_readySrcRegIdx[idx];
621    }
622
623    /** Sets this instruction as completed. */
624    void setCompleted() { status.set(Completed); }
625
626    /** Returns whether or not this instruction is completed. */
627    bool isCompleted() const { return status[Completed]; }
628
629    /** Marks the result as ready. */
630    void setResultReady() { status.set(ResultReady); }
631
632    /** Returns whether or not the result is ready. */
633    bool isResultReady() const { return status[ResultReady]; }
634
635    /** Sets this instruction as ready to issue. */
636    void setCanIssue() { status.set(CanIssue); }
637
638    /** Returns whether or not this instruction is ready to issue. */
639    bool readyToIssue() const { return status[CanIssue]; }
640
641    /** Clears this instruction being able to issue. */
642    void clearCanIssue() { status.reset(CanIssue); }
643
644    /** Sets this instruction as issued from the IQ. */
645    void setIssued() { status.set(Issued); }
646
647    /** Returns whether or not this instruction has issued. */
648    bool isIssued() const { return status[Issued]; }
649
650    /** Clears this instruction as being issued. */
651    void clearIssued() { status.reset(Issued); }
652
653    /** Sets this instruction as executed. */
654    void setExecuted() { status.set(Executed); }
655
656    /** Returns whether or not this instruction has executed. */
657    bool isExecuted() const { return status[Executed]; }
658
659    /** Sets this instruction as ready to commit. */
660    void setCanCommit() { status.set(CanCommit); }
661
662    /** Clears this instruction as being ready to commit. */
663    void clearCanCommit() { status.reset(CanCommit); }
664
665    /** Returns whether or not this instruction is ready to commit. */
666    bool readyToCommit() const { return status[CanCommit]; }
667
668    void setAtCommit() { status.set(AtCommit); }
669
670    bool isAtCommit() { return status[AtCommit]; }
671
672    /** Sets this instruction as committed. */
673    void setCommitted() { status.set(Committed); }
674
675    /** Returns whether or not this instruction is committed. */
676    bool isCommitted() const { return status[Committed]; }
677
678    /** Sets this instruction as squashed. */
679    void setSquashed() { status.set(Squashed); }
680
681    /** Returns whether or not this instruction is squashed. */
682    bool isSquashed() const { return status[Squashed]; }
683
684    //Instruction Queue Entry
685    //-----------------------
686    /** Sets this instruction as a entry the IQ. */
687    void setInIQ() { status.set(IqEntry); }
688
689    /** Sets this instruction as a entry the IQ. */
690    void clearInIQ() { status.reset(IqEntry); }
691
692    /** Returns whether or not this instruction has issued. */
693    bool isInIQ() const { return status[IqEntry]; }
694
695    /** Sets this instruction as squashed in the IQ. */
696    void setSquashedInIQ() { status.set(SquashedInIQ); status.set(Squashed);}
697
698    /** Returns whether or not this instruction is squashed in the IQ. */
699    bool isSquashedInIQ() const { return status[SquashedInIQ]; }
700
701
702    //Load / Store Queue Functions
703    //-----------------------
704    /** Sets this instruction as a entry the LSQ. */
705    void setInLSQ() { status.set(LsqEntry); }
706
707    /** Sets this instruction as a entry the LSQ. */
708    void removeInLSQ() { status.reset(LsqEntry); }
709
710    /** Returns whether or not this instruction is in the LSQ. */
711    bool isInLSQ() const { return status[LsqEntry]; }
712
713    /** Sets this instruction as squashed in the LSQ. */
714    void setSquashedInLSQ() { status.set(SquashedInLSQ);}
715
716    /** Returns whether or not this instruction is squashed in the LSQ. */
717    bool isSquashedInLSQ() const { return status[SquashedInLSQ]; }
718
719
720    //Reorder Buffer Functions
721    //-----------------------
722    /** Sets this instruction as a entry the ROB. */
723    void setInROB() { status.set(RobEntry); }
724
725    /** Sets this instruction as a entry the ROB. */
726    void clearInROB() { status.reset(RobEntry); }
727
728    /** Returns whether or not this instruction is in the ROB. */
729    bool isInROB() const { return status[RobEntry]; }
730
731    /** Sets this instruction as squashed in the ROB. */
732    void setSquashedInROB() { status.set(SquashedInROB); }
733
734    /** Returns whether or not this instruction is squashed in the ROB. */
735    bool isSquashedInROB() const { return status[SquashedInROB]; }
736
737    /** Read the PC of this instruction. */
738    const Addr readPC() const { return PC; }
739
740    /**Read the micro PC of this instruction. */
741    const Addr readMicroPC() const { return microPC; }
742
743    /** Set the next PC of this instruction (its actual target). */
744    void setNextPC(Addr val)
745    {
746        nextPC = val;
747    }
748
749    /** Set the next NPC of this instruction (the target in Mips or Sparc).*/
750    void setNextNPC(Addr val)
751    {
752#if ISA_HAS_DELAY_SLOT
753        nextNPC = val;
754#endif
755    }
756
757    void setNextMicroPC(Addr val)
758    {
759        nextMicroPC = val;
760    }
761
762    /** Sets the ASID. */
763    void setASID(short addr_space_id) { asid = addr_space_id; }
764
765    /** Sets the thread id. */
766    void setTid(unsigned tid) { threadNumber = tid; }
767
768    /** Sets the pointer to the thread state. */
769    void setThreadState(ImplState *state) { thread = state; }
770
771    /** Returns the thread context. */
772    ThreadContext *tcBase() { return thread->getTC(); }
773
774  private:
775    /** Instruction effective address.
776     *  @todo: Consider if this is necessary or not.
777     */
778    Addr instEffAddr;
779
780    /** Whether or not the effective address calculation is completed.
781     *  @todo: Consider if this is necessary or not.
782     */
783    bool eaCalcDone;
784
785    /** Is this instruction's memory access uncacheable. */
786    bool isUncacheable;
787
788    /** Has this instruction generated a memory request. */
789    bool reqMade;
790
791  public:
792    /** Sets the effective address. */
793    void setEA(Addr &ea) { instEffAddr = ea; eaCalcDone = true; }
794
795    /** Returns the effective address. */
796    const Addr &getEA() const { return instEffAddr; }
797
798    /** Returns whether or not the eff. addr. calculation has been completed. */
799    bool doneEACalc() { return eaCalcDone; }
800
801    /** Returns whether or not the eff. addr. source registers are ready. */
802    bool eaSrcsReady();
803
804    /** Whether or not the memory operation is done. */
805    bool memOpDone;
806
807    /** Is this instruction's memory access uncacheable. */
808    bool uncacheable() { return isUncacheable; }
809
810    /** Has this instruction generated a memory request. */
811    bool hasRequest() { return reqMade; }
812
813  public:
814    /** Load queue index. */
815    int16_t lqIdx;
816
817    /** Store queue index. */
818    int16_t sqIdx;
819
820    /** Iterator pointing to this BaseDynInst in the list of all insts. */
821    ListIt instListIt;
822
823    /** Returns iterator to this instruction in the list of all insts. */
824    ListIt &getInstListIt() { return instListIt; }
825
826    /** Sets iterator for this instruction in the list of all insts. */
827    void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; }
828
829  public:
830    /** Returns the number of consecutive store conditional failures. */
831    unsigned readStCondFailures()
832    { return thread->storeCondFailures; }
833
834    /** Sets the number of consecutive store conditional failures. */
835    void setStCondFailures(unsigned sc_failures)
836    { thread->storeCondFailures = sc_failures; }
837};
838
839template<class Impl>
840template<class T>
841inline Fault
842BaseDynInst<Impl>::read(Addr addr, T &data, unsigned flags)
843{
844    reqMade = true;
845    Request *req = new Request();
846    req->setVirt(asid, addr, sizeof(T), flags, this->PC);
847    req->setThreadContext(thread->readCpuId(), threadNumber);
848
849    if ((req->getVaddr() & (TheISA::VMPageSize - 1)) + req->getSize() >
850        TheISA::VMPageSize) {
851        delete req;
852        return TheISA::genAlignmentFault();
853    }
854
855    fault = cpu->translateDataReadReq(req, thread);
856
857    if (req->isUncacheable())
858        isUncacheable = true;
859
860    if (fault == NoFault) {
861        effAddr = req->getVaddr();
862        effAddrValid = true;
863        physEffAddr = req->getPaddr();
864        memReqFlags = req->getFlags();
865
866#if 0
867        if (cpu->system->memctrl->badaddr(physEffAddr)) {
868            fault = TheISA::genMachineCheckFault();
869            data = (T)-1;
870            this->setExecuted();
871        } else {
872            fault = cpu->read(req, data, lqIdx);
873        }
874#else
875        fault = cpu->read(req, data, lqIdx);
876#endif
877    } else {
878        // Return a fixed value to keep simulation deterministic even
879        // along misspeculated paths.
880        data = (T)-1;
881
882        // Commit will have to clean up whatever happened.  Set this
883        // instruction as executed.
884        this->setExecuted();
885        delete req;
886    }
887
888    if (traceData) {
889        traceData->setAddr(addr);
890        traceData->setData(data);
891    }
892
893    return fault;
894}
895
896template<class Impl>
897template<class T>
898inline Fault
899BaseDynInst<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res)
900{
901    if (traceData) {
902        traceData->setAddr(addr);
903        traceData->setData(data);
904    }
905
906    reqMade = true;
907    Request *req = new Request();
908    req->setVirt(asid, addr, sizeof(T), flags, this->PC);
909    req->setThreadContext(thread->readCpuId(), threadNumber);
910
911    if ((req->getVaddr() & (TheISA::VMPageSize - 1)) + req->getSize() >
912        TheISA::VMPageSize) {
913        delete req;
914        return TheISA::genAlignmentFault();
915    }
916
917    fault = cpu->translateDataWriteReq(req, thread);
918
919    if (req->isUncacheable())
920        isUncacheable = true;
921
922    if (fault == NoFault) {
923        effAddr = req->getVaddr();
924        effAddrValid = true;
925        physEffAddr = req->getPaddr();
926        memReqFlags = req->getFlags();
927
928        if (req->isCondSwap()) {
929            assert(res);
930            req->setExtraData(*res);
931        }
932#if 0
933        if (cpu->system->memctrl->badaddr(physEffAddr)) {
934            fault = TheISA::genMachineCheckFault();
935        } else {
936            fault = cpu->write(req, data, sqIdx);
937        }
938#else
939        fault = cpu->write(req, data, sqIdx);
940#endif
941    } else {
942        delete req;
943    }
944
945    return fault;
946}
947
948#endif // __CPU_BASE_DYN_INST_HH__
949