base_dyn_inst.hh revision 3794:647d6bb9539a
1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim 29 */ 30 31#ifndef __CPU_BASE_DYN_INST_HH__ 32#define __CPU_BASE_DYN_INST_HH__ 33 34#include <bitset> 35#include <list> 36#include <string> 37 38#include "arch/faults.hh" 39#include "base/fast_alloc.hh" 40#include "base/trace.hh" 41#include "config/full_system.hh" 42#include "cpu/o3/comm.hh" 43#include "cpu/exetrace.hh" 44#include "cpu/inst_seq.hh" 45#include "cpu/op_class.hh" 46#include "cpu/static_inst.hh" 47#include "mem/packet.hh" 48#include "sim/system.hh" 49 50/** 51 * @file 52 * Defines a dynamic instruction context. 53 */ 54 55// Forward declaration. 56class StaticInstPtr; 57 58template <class Impl> 59class BaseDynInst : public FastAlloc, public RefCounted 60{ 61 public: 62 // Typedef for the CPU. 63 typedef typename Impl::CPUType ImplCPU; 64 typedef typename ImplCPU::ImplState ImplState; 65 66 // Logical register index type. 67 typedef TheISA::RegIndex RegIndex; 68 // Integer register type. 69 typedef TheISA::IntReg IntReg; 70 // Floating point register type. 71 typedef TheISA::FloatReg FloatReg; 72 73 // The DynInstPtr type. 74 typedef typename Impl::DynInstPtr DynInstPtr; 75 76 // The list of instructions iterator type. 77 typedef typename std::list<DynInstPtr>::iterator ListIt; 78 79 enum { 80 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, /// Max source regs 81 MaxInstDestRegs = TheISA::MaxInstDestRegs, /// Max dest regs 82 }; 83 84 /** The StaticInst used by this BaseDynInst. */ 85 StaticInstPtr staticInst; 86 87 //////////////////////////////////////////// 88 // 89 // INSTRUCTION EXECUTION 90 // 91 //////////////////////////////////////////// 92 /** InstRecord that tracks this instructions. */ 93 Trace::InstRecord *traceData; 94 95 /** 96 * Does a read to a given address. 97 * @param addr The address to read. 98 * @param data The read's data is written into this parameter. 99 * @param flags The request's flags. 100 * @return Returns any fault due to the read. 101 */ 102 template <class T> 103 Fault read(Addr addr, T &data, unsigned flags); 104 105 /** 106 * Does a write to a given address. 107 * @param data The data to be written. 108 * @param addr The address to write to. 109 * @param flags The request's flags. 110 * @param res The result of the write (for load locked/store conditionals). 111 * @return Returns any fault due to the write. 112 */ 113 template <class T> 114 Fault write(T data, Addr addr, unsigned flags, 115 uint64_t *res); 116 117 void prefetch(Addr addr, unsigned flags); 118 void writeHint(Addr addr, int size, unsigned flags); 119 Fault copySrcTranslate(Addr src); 120 Fault copy(Addr dest); 121 122 /** @todo: Consider making this private. */ 123 public: 124 /** The sequence number of the instruction. */ 125 InstSeqNum seqNum; 126 127 enum Status { 128 IqEntry, /// Instruction is in the IQ 129 RobEntry, /// Instruction is in the ROB 130 LsqEntry, /// Instruction is in the LSQ 131 Completed, /// Instruction has completed 132 ResultReady, /// Instruction has its result 133 CanIssue, /// Instruction can issue and execute 134 Issued, /// Instruction has issued 135 Executed, /// Instruction has executed 136 CanCommit, /// Instruction can commit 137 AtCommit, /// Instruction has reached commit 138 Committed, /// Instruction has committed 139 Squashed, /// Instruction is squashed 140 SquashedInIQ, /// Instruction is squashed in the IQ 141 SquashedInLSQ, /// Instruction is squashed in the LSQ 142 SquashedInROB, /// Instruction is squashed in the ROB 143 RecoverInst, /// Is a recover instruction 144 BlockingInst, /// Is a blocking instruction 145 ThreadsyncWait, /// Is a thread synchronization instruction 146 SerializeBefore, /// Needs to serialize on 147 /// instructions ahead of it 148 SerializeAfter, /// Needs to serialize instructions behind it 149 SerializeHandled, /// Serialization has been handled 150 NumStatus 151 }; 152 153 /** The status of this BaseDynInst. Several bits can be set. */ 154 std::bitset<NumStatus> status; 155 156 /** The thread this instruction is from. */ 157 short threadNumber; 158 159 /** data address space ID, for loads & stores. */ 160 short asid; 161 162 /** How many source registers are ready. */ 163 unsigned readyRegs; 164 165 /** Pointer to the Impl's CPU object. */ 166 ImplCPU *cpu; 167 168 /** Pointer to the thread state. */ 169 ImplState *thread; 170 171 /** The kind of fault this instruction has generated. */ 172 Fault fault; 173 174 /** The memory request. */ 175 Request *req; 176 177 /** Pointer to the data for the memory access. */ 178 uint8_t *memData; 179 180 /** The effective virtual address (lds & stores only). */ 181 Addr effAddr; 182 183 /** The effective physical address. */ 184 Addr physEffAddr; 185 186 /** Effective virtual address for a copy source. */ 187 Addr copySrcEffAddr; 188 189 /** Effective physical address for a copy source. */ 190 Addr copySrcPhysEffAddr; 191 192 /** The memory request flags (from translation). */ 193 unsigned memReqFlags; 194 195 union Result { 196 uint64_t integer; 197// float fp; 198 double dbl; 199 }; 200 201 /** The result of the instruction; assumes for now that there's only one 202 * destination register. 203 */ 204 Result instResult; 205 206 /** Records changes to result? */ 207 bool recordResult; 208 209 /** PC of this instruction. */ 210 Addr PC; 211 212 /** Next non-speculative PC. It is not filled in at fetch, but rather 213 * once the target of the branch is truly known (either decode or 214 * execute). 215 */ 216 Addr nextPC; 217 218 /** Next non-speculative NPC. Target PC for Mips or Sparc. */ 219 Addr nextNPC; 220 221 /** Predicted next PC. */ 222 Addr predPC; 223 224 /** Predicted next NPC. */ 225 Addr predNPC; 226 227 /** If this is a branch that was predicted taken */ 228 bool predTaken; 229 230 /** Count of total number of dynamic instructions. */ 231 static int instcount; 232 233#ifdef DEBUG 234 void dumpSNList(); 235#endif 236 237 /** Whether or not the source register is ready. 238 * @todo: Not sure this should be here vs the derived class. 239 */ 240 bool _readySrcRegIdx[MaxInstSrcRegs]; 241 242 protected: 243 /** Flattened register index of the destination registers of this 244 * instruction. 245 */ 246 TheISA::RegIndex _flatDestRegIdx[TheISA::MaxInstDestRegs]; 247 248 /** Flattened register index of the source registers of this 249 * instruction. 250 */ 251 TheISA::RegIndex _flatSrcRegIdx[TheISA::MaxInstSrcRegs]; 252 253 /** Physical register index of the destination registers of this 254 * instruction. 255 */ 256 PhysRegIndex _destRegIdx[TheISA::MaxInstDestRegs]; 257 258 /** Physical register index of the source registers of this 259 * instruction. 260 */ 261 PhysRegIndex _srcRegIdx[TheISA::MaxInstSrcRegs]; 262 263 /** Physical register index of the previous producers of the 264 * architected destinations. 265 */ 266 PhysRegIndex _prevDestRegIdx[TheISA::MaxInstDestRegs]; 267 268 public: 269 270 /** Returns the physical register index of the i'th destination 271 * register. 272 */ 273 PhysRegIndex renamedDestRegIdx(int idx) const 274 { 275 return _destRegIdx[idx]; 276 } 277 278 /** Returns the physical register index of the i'th source register. */ 279 PhysRegIndex renamedSrcRegIdx(int idx) const 280 { 281 return _srcRegIdx[idx]; 282 } 283 284 /** Returns the flattened register index of the i'th destination 285 * register. 286 */ 287 TheISA::RegIndex flattenedDestRegIdx(int idx) const 288 { 289 return _flatDestRegIdx[idx]; 290 } 291 292 /** Returns the flattened register index of the i'th source register */ 293 TheISA::RegIndex flattenedSrcRegIdx(int idx) const 294 { 295 return _flatSrcRegIdx[idx]; 296 } 297 298 /** Returns the physical register index of the previous physical register 299 * that remapped to the same logical register index. 300 */ 301 PhysRegIndex prevDestRegIdx(int idx) const 302 { 303 return _prevDestRegIdx[idx]; 304 } 305 306 /** Renames a destination register to a physical register. Also records 307 * the previous physical register that the logical register mapped to. 308 */ 309 void renameDestReg(int idx, 310 PhysRegIndex renamed_dest, 311 PhysRegIndex previous_rename) 312 { 313 _destRegIdx[idx] = renamed_dest; 314 _prevDestRegIdx[idx] = previous_rename; 315 } 316 317 /** Renames a source logical register to the physical register which 318 * has/will produce that logical register's result. 319 * @todo: add in whether or not the source register is ready. 320 */ 321 void renameSrcReg(int idx, PhysRegIndex renamed_src) 322 { 323 _srcRegIdx[idx] = renamed_src; 324 } 325 326 /** Flattens a source architectural register index into a logical index. 327 */ 328 void flattenSrcReg(int idx, TheISA::RegIndex flattened_src) 329 { 330 _flatSrcRegIdx[idx] = flattened_src; 331 } 332 333 /** Flattens a destination architectural register index into a logical 334 * index. 335 */ 336 void flattenDestReg(int idx, TheISA::RegIndex flattened_dest) 337 { 338 _flatDestRegIdx[idx] = flattened_dest; 339 } 340 341 /** BaseDynInst constructor given a binary instruction. 342 * @param inst The binary instruction. 343 * @param PC The PC of the instruction. 344 * @param pred_PC The predicted next PC. 345 * @param pred_NPC The predicted next NPC. 346 * @param seq_num The sequence number of the instruction. 347 * @param cpu Pointer to the instruction's CPU. 348 */ 349 BaseDynInst(TheISA::ExtMachInst inst, Addr PC, 350 Addr pred_PC, Addr pred_NPC, 351 InstSeqNum seq_num, ImplCPU *cpu); 352 353 /** BaseDynInst constructor given a StaticInst pointer. 354 * @param _staticInst The StaticInst for this BaseDynInst. 355 */ 356 BaseDynInst(StaticInstPtr &_staticInst); 357 358 /** BaseDynInst destructor. */ 359 ~BaseDynInst(); 360 361 private: 362 /** Function to initialize variables in the constructors. */ 363 void initVars(); 364 365 public: 366 /** Dumps out contents of this BaseDynInst. */ 367 void dump(); 368 369 /** Dumps out contents of this BaseDynInst into given string. */ 370 void dump(std::string &outstring); 371 372 /** Read this CPU's ID. */ 373 int readCpuId() { return cpu->readCpuId(); } 374 375 /** Returns the fault type. */ 376 Fault getFault() { return fault; } 377 378 /** Checks whether or not this instruction has had its branch target 379 * calculated yet. For now it is not utilized and is hacked to be 380 * always false. 381 * @todo: Actually use this instruction. 382 */ 383 bool doneTargCalc() { return false; } 384 385 /** Returns the next PC. This could be the speculative next PC if it is 386 * called prior to the actual branch target being calculated. 387 */ 388 Addr readNextPC() { return nextPC; } 389 390 /** Returns the next NPC. This could be the speculative next NPC if it is 391 * called prior to the actual branch target being calculated. 392 */ 393 Addr readNextNPC() { return nextNPC; } 394 395 /** Set the predicted target of this current instruction. */ 396 void setPredTarg(Addr predicted_PC, Addr predicted_NPC) 397 { 398 predPC = predicted_PC; 399 predNPC = predicted_NPC; 400 } 401 402 /** Returns the predicted PC immediately after the branch. */ 403 Addr readPredPC() { return predPC; } 404 405 /** Returns the predicted PC two instructions after the branch */ 406 Addr readPredNPC() { return predNPC; } 407 408 /** Returns whether the instruction was predicted taken or not. */ 409 bool readPredTaken() 410 { 411 return predTaken; 412 } 413 414 void setPredTaken(bool predicted_taken) 415 { 416 predTaken = predicted_taken; 417 } 418 419 /** Returns whether the instruction mispredicted. */ 420 bool mispredicted() 421 { 422 return predPC != nextPC || predNPC != nextNPC; 423 } 424 425 // 426 // Instruction types. Forward checks to StaticInst object. 427 // 428 bool isNop() const { return staticInst->isNop(); } 429 bool isMemRef() const { return staticInst->isMemRef(); } 430 bool isLoad() const { return staticInst->isLoad(); } 431 bool isStore() const { return staticInst->isStore(); } 432 bool isStoreConditional() const 433 { return staticInst->isStoreConditional(); } 434 bool isInstPrefetch() const { return staticInst->isInstPrefetch(); } 435 bool isDataPrefetch() const { return staticInst->isDataPrefetch(); } 436 bool isCopy() const { return staticInst->isCopy(); } 437 bool isInteger() const { return staticInst->isInteger(); } 438 bool isFloating() const { return staticInst->isFloating(); } 439 bool isControl() const { return staticInst->isControl(); } 440 bool isCall() const { return staticInst->isCall(); } 441 bool isReturn() const { return staticInst->isReturn(); } 442 bool isDirectCtrl() const { return staticInst->isDirectCtrl(); } 443 bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); } 444 bool isCondCtrl() const { return staticInst->isCondCtrl(); } 445 bool isUncondCtrl() const { return staticInst->isUncondCtrl(); } 446 bool isCondDelaySlot() const { return staticInst->isCondDelaySlot(); } 447 bool isThreadSync() const { return staticInst->isThreadSync(); } 448 bool isSerializing() const { return staticInst->isSerializing(); } 449 bool isSerializeBefore() const 450 { return staticInst->isSerializeBefore() || status[SerializeBefore]; } 451 bool isSerializeAfter() const 452 { return staticInst->isSerializeAfter() || status[SerializeAfter]; } 453 bool isMemBarrier() const { return staticInst->isMemBarrier(); } 454 bool isWriteBarrier() const { return staticInst->isWriteBarrier(); } 455 bool isNonSpeculative() const { return staticInst->isNonSpeculative(); } 456 bool isQuiesce() const { return staticInst->isQuiesce(); } 457 bool isIprAccess() const { return staticInst->isIprAccess(); } 458 bool isUnverifiable() const { return staticInst->isUnverifiable(); } 459 460 /** Temporarily sets this instruction as a serialize before instruction. */ 461 void setSerializeBefore() { status.set(SerializeBefore); } 462 463 /** Clears the serializeBefore part of this instruction. */ 464 void clearSerializeBefore() { status.reset(SerializeBefore); } 465 466 /** Checks if this serializeBefore is only temporarily set. */ 467 bool isTempSerializeBefore() { return status[SerializeBefore]; } 468 469 /** Temporarily sets this instruction as a serialize after instruction. */ 470 void setSerializeAfter() { status.set(SerializeAfter); } 471 472 /** Clears the serializeAfter part of this instruction.*/ 473 void clearSerializeAfter() { status.reset(SerializeAfter); } 474 475 /** Checks if this serializeAfter is only temporarily set. */ 476 bool isTempSerializeAfter() { return status[SerializeAfter]; } 477 478 /** Sets the serialization part of this instruction as handled. */ 479 void setSerializeHandled() { status.set(SerializeHandled); } 480 481 /** Checks if the serialization part of this instruction has been 482 * handled. This does not apply to the temporary serializing 483 * state; it only applies to this instruction's own permanent 484 * serializing state. 485 */ 486 bool isSerializeHandled() { return status[SerializeHandled]; } 487 488 /** Returns the opclass of this instruction. */ 489 OpClass opClass() const { return staticInst->opClass(); } 490 491 /** Returns the branch target address. */ 492 Addr branchTarget() const { return staticInst->branchTarget(PC); } 493 494 /** Returns the number of source registers. */ 495 int8_t numSrcRegs() const { return staticInst->numSrcRegs(); } 496 497 /** Returns the number of destination registers. */ 498 int8_t numDestRegs() const { return staticInst->numDestRegs(); } 499 500 // the following are used to track physical register usage 501 // for machines with separate int & FP reg files 502 int8_t numFPDestRegs() const { return staticInst->numFPDestRegs(); } 503 int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); } 504 505 /** Returns the logical register index of the i'th destination register. */ 506 RegIndex destRegIdx(int i) const { return staticInst->destRegIdx(i); } 507 508 /** Returns the logical register index of the i'th source register. */ 509 RegIndex srcRegIdx(int i) const { return staticInst->srcRegIdx(i); } 510 511 /** Returns the result of an integer instruction. */ 512 uint64_t readIntResult() { return instResult.integer; } 513 514 /** Returns the result of a floating point instruction. */ 515 float readFloatResult() { return (float)instResult.dbl; } 516 517 /** Returns the result of a floating point (double) instruction. */ 518 double readDoubleResult() { return instResult.dbl; } 519 520 /** Records an integer register being set to a value. */ 521 void setIntRegOperand(const StaticInst *si, int idx, uint64_t val) 522 { 523 if (recordResult) 524 instResult.integer = val; 525 } 526 527 /** Records an fp register being set to a value. */ 528 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val, 529 int width) 530 { 531 if (recordResult) { 532 if (width == 32) 533 instResult.dbl = (double)val; 534 else if (width == 64) 535 instResult.dbl = val; 536 else 537 panic("Unsupported width!"); 538 } 539 } 540 541 /** Records an fp register being set to a value. */ 542 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val) 543 { 544 if (recordResult) 545 instResult.dbl = (double)val; 546 } 547 548 /** Records an fp register being set to an integer value. */ 549 void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val, 550 int width) 551 { 552 if (recordResult) 553 instResult.integer = val; 554 } 555 556 /** Records an fp register being set to an integer value. */ 557 void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val) 558 { 559 if (recordResult) 560 instResult.integer = val; 561 } 562 563 /** Records that one of the source registers is ready. */ 564 void markSrcRegReady(); 565 566 /** Marks a specific register as ready. */ 567 void markSrcRegReady(RegIndex src_idx); 568 569 /** Returns if a source register is ready. */ 570 bool isReadySrcRegIdx(int idx) const 571 { 572 return this->_readySrcRegIdx[idx]; 573 } 574 575 /** Sets this instruction as completed. */ 576 void setCompleted() { status.set(Completed); } 577 578 /** Returns whether or not this instruction is completed. */ 579 bool isCompleted() const { return status[Completed]; } 580 581 /** Marks the result as ready. */ 582 void setResultReady() { status.set(ResultReady); } 583 584 /** Returns whether or not the result is ready. */ 585 bool isResultReady() const { return status[ResultReady]; } 586 587 /** Sets this instruction as ready to issue. */ 588 void setCanIssue() { status.set(CanIssue); } 589 590 /** Returns whether or not this instruction is ready to issue. */ 591 bool readyToIssue() const { return status[CanIssue]; } 592 593 /** Sets this instruction as issued from the IQ. */ 594 void setIssued() { status.set(Issued); } 595 596 /** Returns whether or not this instruction has issued. */ 597 bool isIssued() const { return status[Issued]; } 598 599 /** Sets this instruction as executed. */ 600 void setExecuted() { status.set(Executed); } 601 602 /** Returns whether or not this instruction has executed. */ 603 bool isExecuted() const { return status[Executed]; } 604 605 /** Sets this instruction as ready to commit. */ 606 void setCanCommit() { status.set(CanCommit); } 607 608 /** Clears this instruction as being ready to commit. */ 609 void clearCanCommit() { status.reset(CanCommit); } 610 611 /** Returns whether or not this instruction is ready to commit. */ 612 bool readyToCommit() const { return status[CanCommit]; } 613 614 void setAtCommit() { status.set(AtCommit); } 615 616 bool isAtCommit() { return status[AtCommit]; } 617 618 /** Sets this instruction as committed. */ 619 void setCommitted() { status.set(Committed); } 620 621 /** Returns whether or not this instruction is committed. */ 622 bool isCommitted() const { return status[Committed]; } 623 624 /** Sets this instruction as squashed. */ 625 void setSquashed() { status.set(Squashed); } 626 627 /** Returns whether or not this instruction is squashed. */ 628 bool isSquashed() const { return status[Squashed]; } 629 630 //Instruction Queue Entry 631 //----------------------- 632 /** Sets this instruction as a entry the IQ. */ 633 void setInIQ() { status.set(IqEntry); } 634 635 /** Sets this instruction as a entry the IQ. */ 636 void clearInIQ() { status.reset(IqEntry); } 637 638 /** Returns whether or not this instruction has issued. */ 639 bool isInIQ() const { return status[IqEntry]; } 640 641 /** Sets this instruction as squashed in the IQ. */ 642 void setSquashedInIQ() { status.set(SquashedInIQ); status.set(Squashed);} 643 644 /** Returns whether or not this instruction is squashed in the IQ. */ 645 bool isSquashedInIQ() const { return status[SquashedInIQ]; } 646 647 648 //Load / Store Queue Functions 649 //----------------------- 650 /** Sets this instruction as a entry the LSQ. */ 651 void setInLSQ() { status.set(LsqEntry); } 652 653 /** Sets this instruction as a entry the LSQ. */ 654 void removeInLSQ() { status.reset(LsqEntry); } 655 656 /** Returns whether or not this instruction is in the LSQ. */ 657 bool isInLSQ() const { return status[LsqEntry]; } 658 659 /** Sets this instruction as squashed in the LSQ. */ 660 void setSquashedInLSQ() { status.set(SquashedInLSQ);} 661 662 /** Returns whether or not this instruction is squashed in the LSQ. */ 663 bool isSquashedInLSQ() const { return status[SquashedInLSQ]; } 664 665 666 //Reorder Buffer Functions 667 //----------------------- 668 /** Sets this instruction as a entry the ROB. */ 669 void setInROB() { status.set(RobEntry); } 670 671 /** Sets this instruction as a entry the ROB. */ 672 void clearInROB() { status.reset(RobEntry); } 673 674 /** Returns whether or not this instruction is in the ROB. */ 675 bool isInROB() const { return status[RobEntry]; } 676 677 /** Sets this instruction as squashed in the ROB. */ 678 void setSquashedInROB() { status.set(SquashedInROB); } 679 680 /** Returns whether or not this instruction is squashed in the ROB. */ 681 bool isSquashedInROB() const { return status[SquashedInROB]; } 682 683 /** Read the PC of this instruction. */ 684 const Addr readPC() const { return PC; } 685 686 /** Set the next PC of this instruction (its actual target). */ 687 void setNextPC(uint64_t val) 688 { 689 nextPC = val; 690 } 691 692 /** Set the next NPC of this instruction (the target in Mips or Sparc).*/ 693 void setNextNPC(uint64_t val) 694 { 695 nextNPC = val; 696 } 697 698 /** Sets the ASID. */ 699 void setASID(short addr_space_id) { asid = addr_space_id; } 700 701 /** Sets the thread id. */ 702 void setTid(unsigned tid) { threadNumber = tid; } 703 704 /** Sets the pointer to the thread state. */ 705 void setThreadState(ImplState *state) { thread = state; } 706 707 /** Returns the thread context. */ 708 ThreadContext *tcBase() { return thread->getTC(); } 709 710 private: 711 /** Instruction effective address. 712 * @todo: Consider if this is necessary or not. 713 */ 714 Addr instEffAddr; 715 716 /** Whether or not the effective address calculation is completed. 717 * @todo: Consider if this is necessary or not. 718 */ 719 bool eaCalcDone; 720 721 public: 722 /** Sets the effective address. */ 723 void setEA(Addr &ea) { instEffAddr = ea; eaCalcDone = true; } 724 725 /** Returns the effective address. */ 726 const Addr &getEA() const { return instEffAddr; } 727 728 /** Returns whether or not the eff. addr. calculation has been completed. */ 729 bool doneEACalc() { return eaCalcDone; } 730 731 /** Returns whether or not the eff. addr. source registers are ready. */ 732 bool eaSrcsReady(); 733 734 /** Whether or not the memory operation is done. */ 735 bool memOpDone; 736 737 public: 738 /** Load queue index. */ 739 int16_t lqIdx; 740 741 /** Store queue index. */ 742 int16_t sqIdx; 743 744 /** Iterator pointing to this BaseDynInst in the list of all insts. */ 745 ListIt instListIt; 746 747 /** Returns iterator to this instruction in the list of all insts. */ 748 ListIt &getInstListIt() { return instListIt; } 749 750 /** Sets iterator for this instruction in the list of all insts. */ 751 void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; } 752 753 public: 754 /** Returns the number of consecutive store conditional failures. */ 755 unsigned readStCondFailures() 756 { return thread->storeCondFailures; } 757 758 /** Sets the number of consecutive store conditional failures. */ 759 void setStCondFailures(unsigned sc_failures) 760 { thread->storeCondFailures = sc_failures; } 761}; 762 763template<class Impl> 764template<class T> 765inline Fault 766BaseDynInst<Impl>::read(Addr addr, T &data, unsigned flags) 767{ 768 // Sometimes reads will get retried, so they may come through here 769 // twice. 770 if (!req) { 771 req = new Request(); 772 req->setVirt(asid, addr, sizeof(T), flags, this->PC); 773 req->setThreadContext(thread->readCpuId(), threadNumber); 774 } else { 775 assert(addr == req->getVaddr()); 776 } 777 778 if ((req->getVaddr() & (TheISA::VMPageSize - 1)) + req->getSize() > 779 TheISA::VMPageSize) { 780 return TheISA::genAlignmentFault(); 781 } 782 783 fault = cpu->translateDataReadReq(req, thread); 784 785 if (fault == NoFault) { 786 effAddr = req->getVaddr(); 787 physEffAddr = req->getPaddr(); 788 memReqFlags = req->getFlags(); 789 790#if 0 791 if (cpu->system->memctrl->badaddr(physEffAddr)) { 792 fault = TheISA::genMachineCheckFault(); 793 data = (T)-1; 794 this->setExecuted(); 795 } else { 796 fault = cpu->read(req, data, lqIdx); 797 } 798#else 799 fault = cpu->read(req, data, lqIdx); 800#endif 801 } else { 802 // Return a fixed value to keep simulation deterministic even 803 // along misspeculated paths. 804 data = (T)-1; 805 806 // Commit will have to clean up whatever happened. Set this 807 // instruction as executed. 808 this->setExecuted(); 809 } 810 811 if (traceData) { 812 traceData->setAddr(addr); 813 traceData->setData(data); 814 } 815 816 return fault; 817} 818 819template<class Impl> 820template<class T> 821inline Fault 822BaseDynInst<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res) 823{ 824 if (traceData) { 825 traceData->setAddr(addr); 826 traceData->setData(data); 827 } 828 829 assert(req == NULL); 830 831 req = new Request(); 832 req->setVirt(asid, addr, sizeof(T), flags, this->PC); 833 req->setThreadContext(thread->readCpuId(), threadNumber); 834 835 if ((req->getVaddr() & (TheISA::VMPageSize - 1)) + req->getSize() > 836 TheISA::VMPageSize) { 837 return TheISA::genAlignmentFault(); 838 } 839 840 fault = cpu->translateDataWriteReq(req, thread); 841 842 if (fault == NoFault) { 843 effAddr = req->getVaddr(); 844 physEffAddr = req->getPaddr(); 845 memReqFlags = req->getFlags(); 846#if 0 847 if (cpu->system->memctrl->badaddr(physEffAddr)) { 848 fault = TheISA::genMachineCheckFault(); 849 } else { 850 fault = cpu->write(req, data, sqIdx); 851 } 852#else 853 fault = cpu->write(req, data, sqIdx); 854#endif 855 } 856 857 if (res) { 858 // always return some result to keep misspeculated paths 859 // (which will ignore faults) deterministic 860 *res = (fault == NoFault) ? req->getScResult() : 0; 861 } 862 863 return fault; 864} 865 866#endif // __CPU_BASE_DYN_INST_HH__ 867