base_dyn_inst.hh revision 3791:f1783bae1afe
1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim 29 */ 30 31#ifndef __CPU_BASE_DYN_INST_HH__ 32#define __CPU_BASE_DYN_INST_HH__ 33 34#include <bitset> 35#include <list> 36#include <string> 37 38#include "arch/faults.hh" 39#include "base/fast_alloc.hh" 40#include "base/trace.hh" 41#include "config/full_system.hh" 42#include "cpu/o3/comm.hh" 43#include "cpu/exetrace.hh" 44#include "cpu/inst_seq.hh" 45#include "cpu/op_class.hh" 46#include "cpu/static_inst.hh" 47#include "mem/packet.hh" 48#include "sim/system.hh" 49 50/** 51 * @file 52 * Defines a dynamic instruction context. 53 */ 54 55// Forward declaration. 56class StaticInstPtr; 57 58template <class Impl> 59class BaseDynInst : public FastAlloc, public RefCounted 60{ 61 public: 62 // Typedef for the CPU. 63 typedef typename Impl::CPUType ImplCPU; 64 typedef typename ImplCPU::ImplState ImplState; 65 66 // Logical register index type. 67 typedef TheISA::RegIndex RegIndex; 68 // Integer register type. 69 typedef TheISA::IntReg IntReg; 70 // Floating point register type. 71 typedef TheISA::FloatReg FloatReg; 72 73 // The DynInstPtr type. 74 typedef typename Impl::DynInstPtr DynInstPtr; 75 76 // The list of instructions iterator type. 77 typedef typename std::list<DynInstPtr>::iterator ListIt; 78 79 enum { 80 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, /// Max source regs 81 MaxInstDestRegs = TheISA::MaxInstDestRegs, /// Max dest regs 82 }; 83 84 /** The StaticInst used by this BaseDynInst. */ 85 StaticInstPtr staticInst; 86 87 //////////////////////////////////////////// 88 // 89 // INSTRUCTION EXECUTION 90 // 91 //////////////////////////////////////////// 92 /** InstRecord that tracks this instructions. */ 93 Trace::InstRecord *traceData; 94 95 /** 96 * Does a read to a given address. 97 * @param addr The address to read. 98 * @param data The read's data is written into this parameter. 99 * @param flags The request's flags. 100 * @return Returns any fault due to the read. 101 */ 102 template <class T> 103 Fault read(Addr addr, T &data, unsigned flags); 104 105 /** 106 * Does a write to a given address. 107 * @param data The data to be written. 108 * @param addr The address to write to. 109 * @param flags The request's flags. 110 * @param res The result of the write (for load locked/store conditionals). 111 * @return Returns any fault due to the write. 112 */ 113 template <class T> 114 Fault write(T data, Addr addr, unsigned flags, 115 uint64_t *res); 116 117 void prefetch(Addr addr, unsigned flags); 118 void writeHint(Addr addr, int size, unsigned flags); 119 Fault copySrcTranslate(Addr src); 120 Fault copy(Addr dest); 121 122 /** @todo: Consider making this private. */ 123 public: 124 /** The sequence number of the instruction. */ 125 InstSeqNum seqNum; 126 127 enum Status { 128 IqEntry, /// Instruction is in the IQ 129 RobEntry, /// Instruction is in the ROB 130 LsqEntry, /// Instruction is in the LSQ 131 Completed, /// Instruction has completed 132 ResultReady, /// Instruction has its result 133 CanIssue, /// Instruction can issue and execute 134 Issued, /// Instruction has issued 135 Executed, /// Instruction has executed 136 CanCommit, /// Instruction can commit 137 AtCommit, /// Instruction has reached commit 138 Committed, /// Instruction has committed 139 Squashed, /// Instruction is squashed 140 SquashedInIQ, /// Instruction is squashed in the IQ 141 SquashedInLSQ, /// Instruction is squashed in the LSQ 142 SquashedInROB, /// Instruction is squashed in the ROB 143 RecoverInst, /// Is a recover instruction 144 BlockingInst, /// Is a blocking instruction 145 ThreadsyncWait, /// Is a thread synchronization instruction 146 SerializeBefore, /// Needs to serialize on 147 /// instructions ahead of it 148 SerializeAfter, /// Needs to serialize instructions behind it 149 SerializeHandled, /// Serialization has been handled 150 NumStatus 151 }; 152 153 /** The status of this BaseDynInst. Several bits can be set. */ 154 std::bitset<NumStatus> status; 155 156 /** The thread this instruction is from. */ 157 short threadNumber; 158 159 /** data address space ID, for loads & stores. */ 160 short asid; 161 162 /** How many source registers are ready. */ 163 unsigned readyRegs; 164 165 /** Pointer to the Impl's CPU object. */ 166 ImplCPU *cpu; 167 168 /** Pointer to the thread state. */ 169 ImplState *thread; 170 171 /** The kind of fault this instruction has generated. */ 172 Fault fault; 173 174 /** The memory request. */ 175 Request *req; 176 177 /** Pointer to the data for the memory access. */ 178 uint8_t *memData; 179 180 /** The effective virtual address (lds & stores only). */ 181 Addr effAddr; 182 183 /** The effective physical address. */ 184 Addr physEffAddr; 185 186 /** Effective virtual address for a copy source. */ 187 Addr copySrcEffAddr; 188 189 /** Effective physical address for a copy source. */ 190 Addr copySrcPhysEffAddr; 191 192 /** The memory request flags (from translation). */ 193 unsigned memReqFlags; 194 195 union Result { 196 uint64_t integer; 197// float fp; 198 double dbl; 199 }; 200 201 /** The result of the instruction; assumes for now that there's only one 202 * destination register. 203 */ 204 Result instResult; 205 206 /** Records changes to result? */ 207 bool recordResult; 208 209 /** PC of this instruction. */ 210 Addr PC; 211 212 /** Next non-speculative PC. It is not filled in at fetch, but rather 213 * once the target of the branch is truly known (either decode or 214 * execute). 215 */ 216 Addr nextPC; 217 218 /** Next non-speculative NPC. Target PC for Mips or Sparc. */ 219 Addr nextNPC; 220 221 /** Predicted next PC. */ 222 Addr predPC; 223 224 /** Count of total number of dynamic instructions. */ 225 static int instcount; 226 227#ifdef DEBUG 228 void dumpSNList(); 229#endif 230 231 /** Whether or not the source register is ready. 232 * @todo: Not sure this should be here vs the derived class. 233 */ 234 bool _readySrcRegIdx[MaxInstSrcRegs]; 235 236 protected: 237 /** Flattened register index of the destination registers of this 238 * instruction. 239 */ 240 TheISA::RegIndex _flatDestRegIdx[TheISA::MaxInstDestRegs]; 241 242 /** Flattened register index of the source registers of this 243 * instruction. 244 */ 245 TheISA::RegIndex _flatSrcRegIdx[TheISA::MaxInstSrcRegs]; 246 247 /** Physical register index of the destination registers of this 248 * instruction. 249 */ 250 PhysRegIndex _destRegIdx[TheISA::MaxInstDestRegs]; 251 252 /** Physical register index of the source registers of this 253 * instruction. 254 */ 255 PhysRegIndex _srcRegIdx[TheISA::MaxInstSrcRegs]; 256 257 /** Physical register index of the previous producers of the 258 * architected destinations. 259 */ 260 PhysRegIndex _prevDestRegIdx[TheISA::MaxInstDestRegs]; 261 262 public: 263 264 /** Returns the physical register index of the i'th destination 265 * register. 266 */ 267 PhysRegIndex renamedDestRegIdx(int idx) const 268 { 269 return _destRegIdx[idx]; 270 } 271 272 /** Returns the physical register index of the i'th source register. */ 273 PhysRegIndex renamedSrcRegIdx(int idx) const 274 { 275 return _srcRegIdx[idx]; 276 } 277 278 /** Returns the flattened register index of the i'th destination 279 * register. 280 */ 281 TheISA::RegIndex flattenedDestRegIdx(int idx) const 282 { 283 return _flatDestRegIdx[idx]; 284 } 285 286 /** Returns the flattened register index of the i'th source register */ 287 TheISA::RegIndex flattenedSrcRegIdx(int idx) const 288 { 289 return _flatSrcRegIdx[idx]; 290 } 291 292 /** Returns the physical register index of the previous physical register 293 * that remapped to the same logical register index. 294 */ 295 PhysRegIndex prevDestRegIdx(int idx) const 296 { 297 return _prevDestRegIdx[idx]; 298 } 299 300 /** Renames a destination register to a physical register. Also records 301 * the previous physical register that the logical register mapped to. 302 */ 303 void renameDestReg(int idx, 304 PhysRegIndex renamed_dest, 305 PhysRegIndex previous_rename) 306 { 307 _destRegIdx[idx] = renamed_dest; 308 _prevDestRegIdx[idx] = previous_rename; 309 } 310 311 /** Renames a source logical register to the physical register which 312 * has/will produce that logical register's result. 313 * @todo: add in whether or not the source register is ready. 314 */ 315 void renameSrcReg(int idx, PhysRegIndex renamed_src) 316 { 317 _srcRegIdx[idx] = renamed_src; 318 } 319 320 /** Flattens a source architectural register index into a logical index. 321 */ 322 void flattenSrcReg(int idx, TheISA::RegIndex flattened_src) 323 { 324 _flatSrcRegIdx[idx] = flattened_src; 325 } 326 327 /** Flattens a destination architectural register index into a logical 328 * index. 329 */ 330 void flattenDestReg(int idx, TheISA::RegIndex flattened_dest) 331 { 332 _flatDestRegIdx[idx] = flattened_dest; 333 } 334 335 /** BaseDynInst constructor given a binary instruction. 336 * @param inst The binary instruction. 337 * @param PC The PC of the instruction. 338 * @param pred_PC The predicted next PC. 339 * @param seq_num The sequence number of the instruction. 340 * @param cpu Pointer to the instruction's CPU. 341 */ 342 BaseDynInst(TheISA::ExtMachInst inst, Addr PC, Addr pred_PC, 343 InstSeqNum seq_num, ImplCPU *cpu); 344 345 /** BaseDynInst constructor given a StaticInst pointer. 346 * @param _staticInst The StaticInst for this BaseDynInst. 347 */ 348 BaseDynInst(StaticInstPtr &_staticInst); 349 350 /** BaseDynInst destructor. */ 351 ~BaseDynInst(); 352 353 private: 354 /** Function to initialize variables in the constructors. */ 355 void initVars(); 356 357 public: 358 /** Dumps out contents of this BaseDynInst. */ 359 void dump(); 360 361 /** Dumps out contents of this BaseDynInst into given string. */ 362 void dump(std::string &outstring); 363 364 /** Read this CPU's ID. */ 365 int readCpuId() { return cpu->readCpuId(); } 366 367 /** Returns the fault type. */ 368 Fault getFault() { return fault; } 369 370 /** Checks whether or not this instruction has had its branch target 371 * calculated yet. For now it is not utilized and is hacked to be 372 * always false. 373 * @todo: Actually use this instruction. 374 */ 375 bool doneTargCalc() { return false; } 376 377 /** Returns the next PC. This could be the speculative next PC if it is 378 * called prior to the actual branch target being calculated. 379 */ 380 Addr readNextPC() { return nextPC; } 381 382 /** Returns the next NPC. This could be the speculative next NPC if it is 383 * called prior to the actual branch target being calculated. 384 */ 385 Addr readNextNPC() { return nextNPC; } 386 387 /** Set the predicted target of this current instruction. */ 388 void setPredTarg(Addr predicted_PC) { predPC = predicted_PC; } 389 390 /** Returns the predicted target of the branch. */ 391 Addr readPredTarg() { return predPC; } 392 393 /** Returns whether the instruction was predicted taken or not. */ 394 bool predTaken() 395#if ISA_HAS_DELAY_SLOT 396 { return predPC != (nextPC + sizeof(TheISA::MachInst)); } 397#else 398 { return predPC != (PC + sizeof(TheISA::MachInst)); } 399#endif 400 401 /** Returns whether the instruction mispredicted. */ 402 bool mispredicted() 403#if ISA_HAS_DELAY_SLOT 404 { return predPC != nextNPC; } 405#else 406 { return predPC != nextPC; } 407#endif 408 // 409 // Instruction types. Forward checks to StaticInst object. 410 // 411 bool isNop() const { return staticInst->isNop(); } 412 bool isMemRef() const { return staticInst->isMemRef(); } 413 bool isLoad() const { return staticInst->isLoad(); } 414 bool isStore() const { return staticInst->isStore(); } 415 bool isStoreConditional() const 416 { return staticInst->isStoreConditional(); } 417 bool isInstPrefetch() const { return staticInst->isInstPrefetch(); } 418 bool isDataPrefetch() const { return staticInst->isDataPrefetch(); } 419 bool isCopy() const { return staticInst->isCopy(); } 420 bool isInteger() const { return staticInst->isInteger(); } 421 bool isFloating() const { return staticInst->isFloating(); } 422 bool isControl() const { return staticInst->isControl(); } 423 bool isCall() const { return staticInst->isCall(); } 424 bool isReturn() const { return staticInst->isReturn(); } 425 bool isDirectCtrl() const { return staticInst->isDirectCtrl(); } 426 bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); } 427 bool isCondCtrl() const { return staticInst->isCondCtrl(); } 428 bool isUncondCtrl() const { return staticInst->isUncondCtrl(); } 429 bool isCondDelaySlot() const { return staticInst->isCondDelaySlot(); } 430 bool isThreadSync() const { return staticInst->isThreadSync(); } 431 bool isSerializing() const { return staticInst->isSerializing(); } 432 bool isSerializeBefore() const 433 { return staticInst->isSerializeBefore() || status[SerializeBefore]; } 434 bool isSerializeAfter() const 435 { return staticInst->isSerializeAfter() || status[SerializeAfter]; } 436 bool isMemBarrier() const { return staticInst->isMemBarrier(); } 437 bool isWriteBarrier() const { return staticInst->isWriteBarrier(); } 438 bool isNonSpeculative() const { return staticInst->isNonSpeculative(); } 439 bool isQuiesce() const { return staticInst->isQuiesce(); } 440 bool isIprAccess() const { return staticInst->isIprAccess(); } 441 bool isUnverifiable() const { return staticInst->isUnverifiable(); } 442 443 /** Temporarily sets this instruction as a serialize before instruction. */ 444 void setSerializeBefore() { status.set(SerializeBefore); } 445 446 /** Clears the serializeBefore part of this instruction. */ 447 void clearSerializeBefore() { status.reset(SerializeBefore); } 448 449 /** Checks if this serializeBefore is only temporarily set. */ 450 bool isTempSerializeBefore() { return status[SerializeBefore]; } 451 452 /** Temporarily sets this instruction as a serialize after instruction. */ 453 void setSerializeAfter() { status.set(SerializeAfter); } 454 455 /** Clears the serializeAfter part of this instruction.*/ 456 void clearSerializeAfter() { status.reset(SerializeAfter); } 457 458 /** Checks if this serializeAfter is only temporarily set. */ 459 bool isTempSerializeAfter() { return status[SerializeAfter]; } 460 461 /** Sets the serialization part of this instruction as handled. */ 462 void setSerializeHandled() { status.set(SerializeHandled); } 463 464 /** Checks if the serialization part of this instruction has been 465 * handled. This does not apply to the temporary serializing 466 * state; it only applies to this instruction's own permanent 467 * serializing state. 468 */ 469 bool isSerializeHandled() { return status[SerializeHandled]; } 470 471 /** Returns the opclass of this instruction. */ 472 OpClass opClass() const { return staticInst->opClass(); } 473 474 /** Returns the branch target address. */ 475 Addr branchTarget() const { return staticInst->branchTarget(PC); } 476 477 /** Returns the number of source registers. */ 478 int8_t numSrcRegs() const { return staticInst->numSrcRegs(); } 479 480 /** Returns the number of destination registers. */ 481 int8_t numDestRegs() const { return staticInst->numDestRegs(); } 482 483 // the following are used to track physical register usage 484 // for machines with separate int & FP reg files 485 int8_t numFPDestRegs() const { return staticInst->numFPDestRegs(); } 486 int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); } 487 488 /** Returns the logical register index of the i'th destination register. */ 489 RegIndex destRegIdx(int i) const { return staticInst->destRegIdx(i); } 490 491 /** Returns the logical register index of the i'th source register. */ 492 RegIndex srcRegIdx(int i) const { return staticInst->srcRegIdx(i); } 493 494 /** Returns the result of an integer instruction. */ 495 uint64_t readIntResult() { return instResult.integer; } 496 497 /** Returns the result of a floating point instruction. */ 498 float readFloatResult() { return (float)instResult.dbl; } 499 500 /** Returns the result of a floating point (double) instruction. */ 501 double readDoubleResult() { return instResult.dbl; } 502 503 /** Records an integer register being set to a value. */ 504 void setIntRegOperand(const StaticInst *si, int idx, uint64_t val) 505 { 506 if (recordResult) 507 instResult.integer = val; 508 } 509 510 /** Records an fp register being set to a value. */ 511 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val, 512 int width) 513 { 514 if (recordResult) { 515 if (width == 32) 516 instResult.dbl = (double)val; 517 else if (width == 64) 518 instResult.dbl = val; 519 else 520 panic("Unsupported width!"); 521 } 522 } 523 524 /** Records an fp register being set to a value. */ 525 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val) 526 { 527 if (recordResult) 528 instResult.dbl = (double)val; 529 } 530 531 /** Records an fp register being set to an integer value. */ 532 void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val, 533 int width) 534 { 535 if (recordResult) 536 instResult.integer = val; 537 } 538 539 /** Records an fp register being set to an integer value. */ 540 void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val) 541 { 542 if (recordResult) 543 instResult.integer = val; 544 } 545 546 /** Records that one of the source registers is ready. */ 547 void markSrcRegReady(); 548 549 /** Marks a specific register as ready. */ 550 void markSrcRegReady(RegIndex src_idx); 551 552 /** Returns if a source register is ready. */ 553 bool isReadySrcRegIdx(int idx) const 554 { 555 return this->_readySrcRegIdx[idx]; 556 } 557 558 /** Sets this instruction as completed. */ 559 void setCompleted() { status.set(Completed); } 560 561 /** Returns whether or not this instruction is completed. */ 562 bool isCompleted() const { return status[Completed]; } 563 564 /** Marks the result as ready. */ 565 void setResultReady() { status.set(ResultReady); } 566 567 /** Returns whether or not the result is ready. */ 568 bool isResultReady() const { return status[ResultReady]; } 569 570 /** Sets this instruction as ready to issue. */ 571 void setCanIssue() { status.set(CanIssue); } 572 573 /** Returns whether or not this instruction is ready to issue. */ 574 bool readyToIssue() const { return status[CanIssue]; } 575 576 /** Sets this instruction as issued from the IQ. */ 577 void setIssued() { status.set(Issued); } 578 579 /** Returns whether or not this instruction has issued. */ 580 bool isIssued() const { return status[Issued]; } 581 582 /** Sets this instruction as executed. */ 583 void setExecuted() { status.set(Executed); } 584 585 /** Returns whether or not this instruction has executed. */ 586 bool isExecuted() const { return status[Executed]; } 587 588 /** Sets this instruction as ready to commit. */ 589 void setCanCommit() { status.set(CanCommit); } 590 591 /** Clears this instruction as being ready to commit. */ 592 void clearCanCommit() { status.reset(CanCommit); } 593 594 /** Returns whether or not this instruction is ready to commit. */ 595 bool readyToCommit() const { return status[CanCommit]; } 596 597 void setAtCommit() { status.set(AtCommit); } 598 599 bool isAtCommit() { return status[AtCommit]; } 600 601 /** Sets this instruction as committed. */ 602 void setCommitted() { status.set(Committed); } 603 604 /** Returns whether or not this instruction is committed. */ 605 bool isCommitted() const { return status[Committed]; } 606 607 /** Sets this instruction as squashed. */ 608 void setSquashed() { status.set(Squashed); } 609 610 /** Returns whether or not this instruction is squashed. */ 611 bool isSquashed() const { return status[Squashed]; } 612 613 //Instruction Queue Entry 614 //----------------------- 615 /** Sets this instruction as a entry the IQ. */ 616 void setInIQ() { status.set(IqEntry); } 617 618 /** Sets this instruction as a entry the IQ. */ 619 void clearInIQ() { status.reset(IqEntry); } 620 621 /** Returns whether or not this instruction has issued. */ 622 bool isInIQ() const { return status[IqEntry]; } 623 624 /** Sets this instruction as squashed in the IQ. */ 625 void setSquashedInIQ() { status.set(SquashedInIQ); status.set(Squashed);} 626 627 /** Returns whether or not this instruction is squashed in the IQ. */ 628 bool isSquashedInIQ() const { return status[SquashedInIQ]; } 629 630 631 //Load / Store Queue Functions 632 //----------------------- 633 /** Sets this instruction as a entry the LSQ. */ 634 void setInLSQ() { status.set(LsqEntry); } 635 636 /** Sets this instruction as a entry the LSQ. */ 637 void removeInLSQ() { status.reset(LsqEntry); } 638 639 /** Returns whether or not this instruction is in the LSQ. */ 640 bool isInLSQ() const { return status[LsqEntry]; } 641 642 /** Sets this instruction as squashed in the LSQ. */ 643 void setSquashedInLSQ() { status.set(SquashedInLSQ);} 644 645 /** Returns whether or not this instruction is squashed in the LSQ. */ 646 bool isSquashedInLSQ() const { return status[SquashedInLSQ]; } 647 648 649 //Reorder Buffer Functions 650 //----------------------- 651 /** Sets this instruction as a entry the ROB. */ 652 void setInROB() { status.set(RobEntry); } 653 654 /** Sets this instruction as a entry the ROB. */ 655 void clearInROB() { status.reset(RobEntry); } 656 657 /** Returns whether or not this instruction is in the ROB. */ 658 bool isInROB() const { return status[RobEntry]; } 659 660 /** Sets this instruction as squashed in the ROB. */ 661 void setSquashedInROB() { status.set(SquashedInROB); } 662 663 /** Returns whether or not this instruction is squashed in the ROB. */ 664 bool isSquashedInROB() const { return status[SquashedInROB]; } 665 666 /** Read the PC of this instruction. */ 667 const Addr readPC() const { return PC; } 668 669 /** Set the next PC of this instruction (its actual target). */ 670 void setNextPC(uint64_t val) 671 { 672 nextPC = val; 673 } 674 675 /** Set the next NPC of this instruction (the target in Mips or Sparc).*/ 676 void setNextNPC(uint64_t val) 677 { 678 nextNPC = val; 679 } 680 681 /** Sets the ASID. */ 682 void setASID(short addr_space_id) { asid = addr_space_id; } 683 684 /** Sets the thread id. */ 685 void setTid(unsigned tid) { threadNumber = tid; } 686 687 /** Sets the pointer to the thread state. */ 688 void setThreadState(ImplState *state) { thread = state; } 689 690 /** Returns the thread context. */ 691 ThreadContext *tcBase() { return thread->getTC(); } 692 693 private: 694 /** Instruction effective address. 695 * @todo: Consider if this is necessary or not. 696 */ 697 Addr instEffAddr; 698 699 /** Whether or not the effective address calculation is completed. 700 * @todo: Consider if this is necessary or not. 701 */ 702 bool eaCalcDone; 703 704 public: 705 /** Sets the effective address. */ 706 void setEA(Addr &ea) { instEffAddr = ea; eaCalcDone = true; } 707 708 /** Returns the effective address. */ 709 const Addr &getEA() const { return instEffAddr; } 710 711 /** Returns whether or not the eff. addr. calculation has been completed. */ 712 bool doneEACalc() { return eaCalcDone; } 713 714 /** Returns whether or not the eff. addr. source registers are ready. */ 715 bool eaSrcsReady(); 716 717 /** Whether or not the memory operation is done. */ 718 bool memOpDone; 719 720 public: 721 /** Load queue index. */ 722 int16_t lqIdx; 723 724 /** Store queue index. */ 725 int16_t sqIdx; 726 727 /** Iterator pointing to this BaseDynInst in the list of all insts. */ 728 ListIt instListIt; 729 730 /** Returns iterator to this instruction in the list of all insts. */ 731 ListIt &getInstListIt() { return instListIt; } 732 733 /** Sets iterator for this instruction in the list of all insts. */ 734 void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; } 735 736 public: 737 /** Returns the number of consecutive store conditional failures. */ 738 unsigned readStCondFailures() 739 { return thread->storeCondFailures; } 740 741 /** Sets the number of consecutive store conditional failures. */ 742 void setStCondFailures(unsigned sc_failures) 743 { thread->storeCondFailures = sc_failures; } 744}; 745 746template<class Impl> 747template<class T> 748inline Fault 749BaseDynInst<Impl>::read(Addr addr, T &data, unsigned flags) 750{ 751 // Sometimes reads will get retried, so they may come through here 752 // twice. 753 if (!req) { 754 req = new Request(); 755 req->setVirt(asid, addr, sizeof(T), flags, this->PC); 756 req->setThreadContext(thread->readCpuId(), threadNumber); 757 } else { 758 assert(addr == req->getVaddr()); 759 } 760 761 if ((req->getVaddr() & (TheISA::VMPageSize - 1)) + req->getSize() > 762 TheISA::VMPageSize) { 763 return TheISA::genAlignmentFault(); 764 } 765 766 fault = cpu->translateDataReadReq(req, thread); 767 768 if (fault == NoFault) { 769 effAddr = req->getVaddr(); 770 physEffAddr = req->getPaddr(); 771 memReqFlags = req->getFlags(); 772 773#if 0 774 if (cpu->system->memctrl->badaddr(physEffAddr)) { 775 fault = TheISA::genMachineCheckFault(); 776 data = (T)-1; 777 this->setExecuted(); 778 } else { 779 fault = cpu->read(req, data, lqIdx); 780 } 781#else 782 fault = cpu->read(req, data, lqIdx); 783#endif 784 } else { 785 // Return a fixed value to keep simulation deterministic even 786 // along misspeculated paths. 787 data = (T)-1; 788 789 // Commit will have to clean up whatever happened. Set this 790 // instruction as executed. 791 this->setExecuted(); 792 } 793 794 if (traceData) { 795 traceData->setAddr(addr); 796 traceData->setData(data); 797 } 798 799 return fault; 800} 801 802template<class Impl> 803template<class T> 804inline Fault 805BaseDynInst<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res) 806{ 807 if (traceData) { 808 traceData->setAddr(addr); 809 traceData->setData(data); 810 } 811 812 assert(req == NULL); 813 814 req = new Request(); 815 req->setVirt(asid, addr, sizeof(T), flags, this->PC); 816 req->setThreadContext(thread->readCpuId(), threadNumber); 817 818 if ((req->getVaddr() & (TheISA::VMPageSize - 1)) + req->getSize() > 819 TheISA::VMPageSize) { 820 return TheISA::genAlignmentFault(); 821 } 822 823 fault = cpu->translateDataWriteReq(req, thread); 824 825 if (fault == NoFault) { 826 effAddr = req->getVaddr(); 827 physEffAddr = req->getPaddr(); 828 memReqFlags = req->getFlags(); 829#if 0 830 if (cpu->system->memctrl->badaddr(physEffAddr)) { 831 fault = TheISA::genMachineCheckFault(); 832 } else { 833 fault = cpu->write(req, data, sqIdx); 834 } 835#else 836 fault = cpu->write(req, data, sqIdx); 837#endif 838 } 839 840 if (res) { 841 // always return some result to keep misspeculated paths 842 // (which will ignore faults) deterministic 843 *res = (fault == NoFault) ? req->getScResult() : 0; 844 } 845 846 return fault; 847} 848 849#endif // __CPU_BASE_DYN_INST_HH__ 850