base_dyn_inst.hh revision 3326:d9cc6bae9d77
1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim 29 */ 30 31#ifndef __CPU_BASE_DYN_INST_HH__ 32#define __CPU_BASE_DYN_INST_HH__ 33 34#include <bitset> 35#include <list> 36#include <string> 37 38#include "arch/faults.hh" 39#include "base/fast_alloc.hh" 40#include "base/trace.hh" 41#include "config/full_system.hh" 42#include "cpu/exetrace.hh" 43#include "cpu/inst_seq.hh" 44#include "cpu/op_class.hh" 45#include "cpu/static_inst.hh" 46#include "mem/packet.hh" 47#include "sim/system.hh" 48 49/** 50 * @file 51 * Defines a dynamic instruction context. 52 */ 53 54// Forward declaration. 55class StaticInstPtr; 56 57template <class Impl> 58class BaseDynInst : public FastAlloc, public RefCounted 59{ 60 public: 61 // Typedef for the CPU. 62 typedef typename Impl::CPUType ImplCPU; 63 typedef typename ImplCPU::ImplState ImplState; 64 65 // Binary machine instruction type. 66 typedef TheISA::MachInst MachInst; 67 // Extended machine instruction type 68 typedef TheISA::ExtMachInst ExtMachInst; 69 // Logical register index type. 70 typedef TheISA::RegIndex RegIndex; 71 // Integer register type. 72 typedef TheISA::IntReg IntReg; 73 // Floating point register type. 74 typedef TheISA::FloatReg FloatReg; 75 76 // The DynInstPtr type. 77 typedef typename Impl::DynInstPtr DynInstPtr; 78 79 // The list of instructions iterator type. 80 typedef typename std::list<DynInstPtr>::iterator ListIt; 81 82 enum { 83 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, /// Max source regs 84 MaxInstDestRegs = TheISA::MaxInstDestRegs, /// Max dest regs 85 }; 86 87 /** The StaticInst used by this BaseDynInst. */ 88 StaticInstPtr staticInst; 89 90 //////////////////////////////////////////// 91 // 92 // INSTRUCTION EXECUTION 93 // 94 //////////////////////////////////////////// 95 /** InstRecord that tracks this instructions. */ 96 Trace::InstRecord *traceData; 97 98 /** 99 * Does a read to a given address. 100 * @param addr The address to read. 101 * @param data The read's data is written into this parameter. 102 * @param flags The request's flags. 103 * @return Returns any fault due to the read. 104 */ 105 template <class T> 106 Fault read(Addr addr, T &data, unsigned flags); 107 108 /** 109 * Does a write to a given address. 110 * @param data The data to be written. 111 * @param addr The address to write to. 112 * @param flags The request's flags. 113 * @param res The result of the write (for load locked/store conditionals). 114 * @return Returns any fault due to the write. 115 */ 116 template <class T> 117 Fault write(T data, Addr addr, unsigned flags, 118 uint64_t *res); 119 120 void prefetch(Addr addr, unsigned flags); 121 void writeHint(Addr addr, int size, unsigned flags); 122 Fault copySrcTranslate(Addr src); 123 Fault copy(Addr dest); 124 125 /** @todo: Consider making this private. */ 126 public: 127 /** The sequence number of the instruction. */ 128 InstSeqNum seqNum; 129 130 enum Status { 131 IqEntry, /// Instruction is in the IQ 132 RobEntry, /// Instruction is in the ROB 133 LsqEntry, /// Instruction is in the LSQ 134 Completed, /// Instruction has completed 135 ResultReady, /// Instruction has its result 136 CanIssue, /// Instruction can issue and execute 137 Issued, /// Instruction has issued 138 Executed, /// Instruction has executed 139 CanCommit, /// Instruction can commit 140 AtCommit, /// Instruction has reached commit 141 Committed, /// Instruction has committed 142 Squashed, /// Instruction is squashed 143 SquashedInIQ, /// Instruction is squashed in the IQ 144 SquashedInLSQ, /// Instruction is squashed in the LSQ 145 SquashedInROB, /// Instruction is squashed in the ROB 146 RecoverInst, /// Is a recover instruction 147 BlockingInst, /// Is a blocking instruction 148 ThreadsyncWait, /// Is a thread synchronization instruction 149 SerializeBefore, /// Needs to serialize on 150 /// instructions ahead of it 151 SerializeAfter, /// Needs to serialize instructions behind it 152 SerializeHandled, /// Serialization has been handled 153 NumStatus 154 }; 155 156 /** The status of this BaseDynInst. Several bits can be set. */ 157 std::bitset<NumStatus> status; 158 159 /** The thread this instruction is from. */ 160 short threadNumber; 161 162 /** data address space ID, for loads & stores. */ 163 short asid; 164 165 /** How many source registers are ready. */ 166 unsigned readyRegs; 167 168 /** Pointer to the Impl's CPU object. */ 169 ImplCPU *cpu; 170 171 /** Pointer to the thread state. */ 172 ImplState *thread; 173 174 /** The kind of fault this instruction has generated. */ 175 Fault fault; 176 177 /** The memory request. */ 178 Request *req; 179 180 /** Pointer to the data for the memory access. */ 181 uint8_t *memData; 182 183 /** The effective virtual address (lds & stores only). */ 184 Addr effAddr; 185 186 /** The effective physical address. */ 187 Addr physEffAddr; 188 189 /** Effective virtual address for a copy source. */ 190 Addr copySrcEffAddr; 191 192 /** Effective physical address for a copy source. */ 193 Addr copySrcPhysEffAddr; 194 195 /** The memory request flags (from translation). */ 196 unsigned memReqFlags; 197 198 union Result { 199 uint64_t integer; 200// float fp; 201 double dbl; 202 }; 203 204 /** The result of the instruction; assumes for now that there's only one 205 * destination register. 206 */ 207 Result instResult; 208 209 /** Records changes to result? */ 210 bool recordResult; 211 212 /** PC of this instruction. */ 213 Addr PC; 214 215 /** Next non-speculative PC. It is not filled in at fetch, but rather 216 * once the target of the branch is truly known (either decode or 217 * execute). 218 */ 219 Addr nextPC; 220 221 /** Next non-speculative NPC. Target PC for Mips or Sparc. */ 222 Addr nextNPC; 223 224 /** Predicted next PC. */ 225 Addr predPC; 226 227 /** Count of total number of dynamic instructions. */ 228 static int instcount; 229 230#ifdef DEBUG 231 void dumpSNList(); 232#endif 233 234 /** Whether or not the source register is ready. 235 * @todo: Not sure this should be here vs the derived class. 236 */ 237 bool _readySrcRegIdx[MaxInstSrcRegs]; 238 239 public: 240 /** BaseDynInst constructor given a binary instruction. 241 * @param inst The binary instruction. 242 * @param PC The PC of the instruction. 243 * @param pred_PC The predicted next PC. 244 * @param seq_num The sequence number of the instruction. 245 * @param cpu Pointer to the instruction's CPU. 246 */ 247 BaseDynInst(ExtMachInst inst, Addr PC, Addr pred_PC, InstSeqNum seq_num, 248 ImplCPU *cpu); 249 250 /** BaseDynInst constructor given a StaticInst pointer. 251 * @param _staticInst The StaticInst for this BaseDynInst. 252 */ 253 BaseDynInst(StaticInstPtr &_staticInst); 254 255 /** BaseDynInst destructor. */ 256 ~BaseDynInst(); 257 258 private: 259 /** Function to initialize variables in the constructors. */ 260 void initVars(); 261 262 public: 263 /** Dumps out contents of this BaseDynInst. */ 264 void dump(); 265 266 /** Dumps out contents of this BaseDynInst into given string. */ 267 void dump(std::string &outstring); 268 269 /** Read this CPU's ID. */ 270 int readCpuId() { return cpu->readCpuId(); } 271 272 /** Returns the fault type. */ 273 Fault getFault() { return fault; } 274 275 /** Checks whether or not this instruction has had its branch target 276 * calculated yet. For now it is not utilized and is hacked to be 277 * always false. 278 * @todo: Actually use this instruction. 279 */ 280 bool doneTargCalc() { return false; } 281 282 /** Returns the next PC. This could be the speculative next PC if it is 283 * called prior to the actual branch target being calculated. 284 */ 285 Addr readNextPC() { return nextPC; } 286 287 /** Returns the next NPC. This could be the speculative next NPC if it is 288 * called prior to the actual branch target being calculated. 289 */ 290 Addr readNextNPC() { return nextNPC; } 291 292 /** Set the predicted target of this current instruction. */ 293 void setPredTarg(Addr predicted_PC) { predPC = predicted_PC; } 294 295 /** Returns the predicted target of the branch. */ 296 Addr readPredTarg() { return predPC; } 297 298 /** Returns whether the instruction was predicted taken or not. */ 299 bool predTaken() 300#if ISA_HAS_DELAY_SLOT 301 { return predPC != (nextPC + sizeof(MachInst)); } 302#else 303 { return predPC != (PC + sizeof(MachInst)); } 304#endif 305 306 /** Returns whether the instruction mispredicted. */ 307 bool mispredicted() 308#if ISA_HAS_DELAY_SLOT 309 { return predPC != nextNPC; } 310#else 311 { return predPC != nextPC; } 312#endif 313 // 314 // Instruction types. Forward checks to StaticInst object. 315 // 316 bool isNop() const { return staticInst->isNop(); } 317 bool isMemRef() const { return staticInst->isMemRef(); } 318 bool isLoad() const { return staticInst->isLoad(); } 319 bool isStore() const { return staticInst->isStore(); } 320 bool isStoreConditional() const 321 { return staticInst->isStoreConditional(); } 322 bool isInstPrefetch() const { return staticInst->isInstPrefetch(); } 323 bool isDataPrefetch() const { return staticInst->isDataPrefetch(); } 324 bool isCopy() const { return staticInst->isCopy(); } 325 bool isInteger() const { return staticInst->isInteger(); } 326 bool isFloating() const { return staticInst->isFloating(); } 327 bool isControl() const { return staticInst->isControl(); } 328 bool isCall() const { return staticInst->isCall(); } 329 bool isReturn() const { return staticInst->isReturn(); } 330 bool isDirectCtrl() const { return staticInst->isDirectCtrl(); } 331 bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); } 332 bool isCondCtrl() const { return staticInst->isCondCtrl(); } 333 bool isUncondCtrl() const { return staticInst->isUncondCtrl(); } 334 bool isCondDelaySlot() const { return staticInst->isCondDelaySlot(); } 335 bool isThreadSync() const { return staticInst->isThreadSync(); } 336 bool isSerializing() const { return staticInst->isSerializing(); } 337 bool isSerializeBefore() const 338 { return staticInst->isSerializeBefore() || status[SerializeBefore]; } 339 bool isSerializeAfter() const 340 { return staticInst->isSerializeAfter() || status[SerializeAfter]; } 341 bool isMemBarrier() const { return staticInst->isMemBarrier(); } 342 bool isWriteBarrier() const { return staticInst->isWriteBarrier(); } 343 bool isNonSpeculative() const { return staticInst->isNonSpeculative(); } 344 bool isQuiesce() const { return staticInst->isQuiesce(); } 345 bool isIprAccess() const { return staticInst->isIprAccess(); } 346 bool isUnverifiable() const { return staticInst->isUnverifiable(); } 347 348 /** Temporarily sets this instruction as a serialize before instruction. */ 349 void setSerializeBefore() { status.set(SerializeBefore); } 350 351 /** Clears the serializeBefore part of this instruction. */ 352 void clearSerializeBefore() { status.reset(SerializeBefore); } 353 354 /** Checks if this serializeBefore is only temporarily set. */ 355 bool isTempSerializeBefore() { return status[SerializeBefore]; } 356 357 /** Temporarily sets this instruction as a serialize after instruction. */ 358 void setSerializeAfter() { status.set(SerializeAfter); } 359 360 /** Clears the serializeAfter part of this instruction.*/ 361 void clearSerializeAfter() { status.reset(SerializeAfter); } 362 363 /** Checks if this serializeAfter is only temporarily set. */ 364 bool isTempSerializeAfter() { return status[SerializeAfter]; } 365 366 /** Sets the serialization part of this instruction as handled. */ 367 void setSerializeHandled() { status.set(SerializeHandled); } 368 369 /** Checks if the serialization part of this instruction has been 370 * handled. This does not apply to the temporary serializing 371 * state; it only applies to this instruction's own permanent 372 * serializing state. 373 */ 374 bool isSerializeHandled() { return status[SerializeHandled]; } 375 376 /** Returns the opclass of this instruction. */ 377 OpClass opClass() const { return staticInst->opClass(); } 378 379 /** Returns the branch target address. */ 380 Addr branchTarget() const { return staticInst->branchTarget(PC); } 381 382 /** Returns the number of source registers. */ 383 int8_t numSrcRegs() const { return staticInst->numSrcRegs(); } 384 385 /** Returns the number of destination registers. */ 386 int8_t numDestRegs() const { return staticInst->numDestRegs(); } 387 388 // the following are used to track physical register usage 389 // for machines with separate int & FP reg files 390 int8_t numFPDestRegs() const { return staticInst->numFPDestRegs(); } 391 int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); } 392 393 /** Returns the logical register index of the i'th destination register. */ 394 RegIndex destRegIdx(int i) const { return staticInst->destRegIdx(i); } 395 396 /** Returns the logical register index of the i'th source register. */ 397 RegIndex srcRegIdx(int i) const { return staticInst->srcRegIdx(i); } 398 399 /** Returns the result of an integer instruction. */ 400 uint64_t readIntResult() { return instResult.integer; } 401 402 /** Returns the result of a floating point instruction. */ 403 float readFloatResult() { return (float)instResult.dbl; } 404 405 /** Returns the result of a floating point (double) instruction. */ 406 double readDoubleResult() { return instResult.dbl; } 407 408 /** Records an integer register being set to a value. */ 409 void setIntReg(const StaticInst *si, int idx, uint64_t val) 410 { 411 if (recordResult) 412 instResult.integer = val; 413 } 414 415 /** Records an fp register being set to a value. */ 416 void setFloatReg(const StaticInst *si, int idx, FloatReg val, int width) 417 { 418 if (recordResult) { 419 if (width == 32) 420 instResult.dbl = (double)val; 421 else if (width == 64) 422 instResult.dbl = val; 423 else 424 panic("Unsupported width!"); 425 } 426 } 427 428 /** Records an fp register being set to a value. */ 429 void setFloatReg(const StaticInst *si, int idx, FloatReg val) 430 { 431 if (recordResult) 432 instResult.dbl = (double)val; 433 } 434 435 /** Records an fp register being set to an integer value. */ 436 void setFloatRegBits(const StaticInst *si, int idx, uint64_t val, int width) 437 { 438 if (recordResult) 439 instResult.integer = val; 440 } 441 442 /** Records an fp register being set to an integer value. */ 443 void setFloatRegBits(const StaticInst *si, int idx, uint64_t val) 444 { 445 if (recordResult) 446 instResult.integer = val; 447 } 448 449 /** Records that one of the source registers is ready. */ 450 void markSrcRegReady(); 451 452 /** Marks a specific register as ready. */ 453 void markSrcRegReady(RegIndex src_idx); 454 455 /** Returns if a source register is ready. */ 456 bool isReadySrcRegIdx(int idx) const 457 { 458 return this->_readySrcRegIdx[idx]; 459 } 460 461 /** Sets this instruction as completed. */ 462 void setCompleted() { status.set(Completed); } 463 464 /** Returns whether or not this instruction is completed. */ 465 bool isCompleted() const { return status[Completed]; } 466 467 /** Marks the result as ready. */ 468 void setResultReady() { status.set(ResultReady); } 469 470 /** Returns whether or not the result is ready. */ 471 bool isResultReady() const { return status[ResultReady]; } 472 473 /** Sets this instruction as ready to issue. */ 474 void setCanIssue() { status.set(CanIssue); } 475 476 /** Returns whether or not this instruction is ready to issue. */ 477 bool readyToIssue() const { return status[CanIssue]; } 478 479 /** Sets this instruction as issued from the IQ. */ 480 void setIssued() { status.set(Issued); } 481 482 /** Returns whether or not this instruction has issued. */ 483 bool isIssued() const { return status[Issued]; } 484 485 /** Sets this instruction as executed. */ 486 void setExecuted() { status.set(Executed); } 487 488 /** Returns whether or not this instruction has executed. */ 489 bool isExecuted() const { return status[Executed]; } 490 491 /** Sets this instruction as ready to commit. */ 492 void setCanCommit() { status.set(CanCommit); } 493 494 /** Clears this instruction as being ready to commit. */ 495 void clearCanCommit() { status.reset(CanCommit); } 496 497 /** Returns whether or not this instruction is ready to commit. */ 498 bool readyToCommit() const { return status[CanCommit]; } 499 500 void setAtCommit() { status.set(AtCommit); } 501 502 bool isAtCommit() { return status[AtCommit]; } 503 504 /** Sets this instruction as committed. */ 505 void setCommitted() { status.set(Committed); } 506 507 /** Returns whether or not this instruction is committed. */ 508 bool isCommitted() const { return status[Committed]; } 509 510 /** Sets this instruction as squashed. */ 511 void setSquashed() { status.set(Squashed); } 512 513 /** Returns whether or not this instruction is squashed. */ 514 bool isSquashed() const { return status[Squashed]; } 515 516 //Instruction Queue Entry 517 //----------------------- 518 /** Sets this instruction as a entry the IQ. */ 519 void setInIQ() { status.set(IqEntry); } 520 521 /** Sets this instruction as a entry the IQ. */ 522 void clearInIQ() { status.reset(IqEntry); } 523 524 /** Returns whether or not this instruction has issued. */ 525 bool isInIQ() const { return status[IqEntry]; } 526 527 /** Sets this instruction as squashed in the IQ. */ 528 void setSquashedInIQ() { status.set(SquashedInIQ); status.set(Squashed);} 529 530 /** Returns whether or not this instruction is squashed in the IQ. */ 531 bool isSquashedInIQ() const { return status[SquashedInIQ]; } 532 533 534 //Load / Store Queue Functions 535 //----------------------- 536 /** Sets this instruction as a entry the LSQ. */ 537 void setInLSQ() { status.set(LsqEntry); } 538 539 /** Sets this instruction as a entry the LSQ. */ 540 void removeInLSQ() { status.reset(LsqEntry); } 541 542 /** Returns whether or not this instruction is in the LSQ. */ 543 bool isInLSQ() const { return status[LsqEntry]; } 544 545 /** Sets this instruction as squashed in the LSQ. */ 546 void setSquashedInLSQ() { status.set(SquashedInLSQ);} 547 548 /** Returns whether or not this instruction is squashed in the LSQ. */ 549 bool isSquashedInLSQ() const { return status[SquashedInLSQ]; } 550 551 552 //Reorder Buffer Functions 553 //----------------------- 554 /** Sets this instruction as a entry the ROB. */ 555 void setInROB() { status.set(RobEntry); } 556 557 /** Sets this instruction as a entry the ROB. */ 558 void clearInROB() { status.reset(RobEntry); } 559 560 /** Returns whether or not this instruction is in the ROB. */ 561 bool isInROB() const { return status[RobEntry]; } 562 563 /** Sets this instruction as squashed in the ROB. */ 564 void setSquashedInROB() { status.set(SquashedInROB); } 565 566 /** Returns whether or not this instruction is squashed in the ROB. */ 567 bool isSquashedInROB() const { return status[SquashedInROB]; } 568 569 /** Read the PC of this instruction. */ 570 const Addr readPC() const { return PC; } 571 572 /** Set the next PC of this instruction (its actual target). */ 573 void setNextPC(uint64_t val) 574 { 575 nextPC = val; 576 } 577 578 /** Set the next NPC of this instruction (the target in Mips or Sparc).*/ 579 void setNextNPC(uint64_t val) 580 { 581 nextNPC = val; 582 } 583 584 /** Sets the ASID. */ 585 void setASID(short addr_space_id) { asid = addr_space_id; } 586 587 /** Sets the thread id. */ 588 void setTid(unsigned tid) { threadNumber = tid; } 589 590 /** Sets the pointer to the thread state. */ 591 void setThreadState(ImplState *state) { thread = state; } 592 593 /** Returns the thread context. */ 594 ThreadContext *tcBase() { return thread->getTC(); } 595 596 private: 597 /** Instruction effective address. 598 * @todo: Consider if this is necessary or not. 599 */ 600 Addr instEffAddr; 601 602 /** Whether or not the effective address calculation is completed. 603 * @todo: Consider if this is necessary or not. 604 */ 605 bool eaCalcDone; 606 607 public: 608 /** Sets the effective address. */ 609 void setEA(Addr &ea) { instEffAddr = ea; eaCalcDone = true; } 610 611 /** Returns the effective address. */ 612 const Addr &getEA() const { return instEffAddr; } 613 614 /** Returns whether or not the eff. addr. calculation has been completed. */ 615 bool doneEACalc() { return eaCalcDone; } 616 617 /** Returns whether or not the eff. addr. source registers are ready. */ 618 bool eaSrcsReady(); 619 620 /** Whether or not the memory operation is done. */ 621 bool memOpDone; 622 623 public: 624 /** Load queue index. */ 625 int16_t lqIdx; 626 627 /** Store queue index. */ 628 int16_t sqIdx; 629 630 /** Iterator pointing to this BaseDynInst in the list of all insts. */ 631 ListIt instListIt; 632 633 /** Returns iterator to this instruction in the list of all insts. */ 634 ListIt &getInstListIt() { return instListIt; } 635 636 /** Sets iterator for this instruction in the list of all insts. */ 637 void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; } 638 639 public: 640 /** Returns the number of consecutive store conditional failures. */ 641 unsigned readStCondFailures() 642 { return thread->storeCondFailures; } 643 644 /** Sets the number of consecutive store conditional failures. */ 645 void setStCondFailures(unsigned sc_failures) 646 { thread->storeCondFailures = sc_failures; } 647}; 648 649template<class Impl> 650template<class T> 651inline Fault 652BaseDynInst<Impl>::read(Addr addr, T &data, unsigned flags) 653{ 654 // Sometimes reads will get retried, so they may come through here 655 // twice. 656 if (!req) { 657 req = new Request(); 658 req->setVirt(asid, addr, sizeof(T), flags, this->PC); 659 req->setThreadContext(thread->readCpuId(), threadNumber); 660 } else { 661 assert(addr == req->getVaddr()); 662 } 663 664 if ((req->getVaddr() & (TheISA::VMPageSize - 1)) + req->getSize() > 665 TheISA::VMPageSize) { 666 return TheISA::genAlignmentFault(); 667 } 668 669 fault = cpu->translateDataReadReq(req, thread); 670 671 if (fault == NoFault) { 672 effAddr = req->getVaddr(); 673 physEffAddr = req->getPaddr(); 674 memReqFlags = req->getFlags(); 675 676#if 0 677 if (cpu->system->memctrl->badaddr(physEffAddr)) { 678 fault = TheISA::genMachineCheckFault(); 679 data = (T)-1; 680 this->setExecuted(); 681 } else { 682 fault = cpu->read(req, data, lqIdx); 683 } 684#else 685 fault = cpu->read(req, data, lqIdx); 686#endif 687 } else { 688 // Return a fixed value to keep simulation deterministic even 689 // along misspeculated paths. 690 data = (T)-1; 691 692 // Commit will have to clean up whatever happened. Set this 693 // instruction as executed. 694 this->setExecuted(); 695 } 696 697 if (traceData) { 698 traceData->setAddr(addr); 699 traceData->setData(data); 700 } 701 702 return fault; 703} 704 705template<class Impl> 706template<class T> 707inline Fault 708BaseDynInst<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res) 709{ 710 if (traceData) { 711 traceData->setAddr(addr); 712 traceData->setData(data); 713 } 714 715 assert(req == NULL); 716 717 req = new Request(); 718 req->setVirt(asid, addr, sizeof(T), flags, this->PC); 719 req->setThreadContext(thread->readCpuId(), threadNumber); 720 721 if ((req->getVaddr() & (TheISA::VMPageSize - 1)) + req->getSize() > 722 TheISA::VMPageSize) { 723 return TheISA::genAlignmentFault(); 724 } 725 726 fault = cpu->translateDataWriteReq(req, thread); 727 728 if (fault == NoFault) { 729 effAddr = req->getVaddr(); 730 physEffAddr = req->getPaddr(); 731 memReqFlags = req->getFlags(); 732#if 0 733 if (cpu->system->memctrl->badaddr(physEffAddr)) { 734 fault = TheISA::genMachineCheckFault(); 735 } else { 736 fault = cpu->write(req, data, sqIdx); 737 } 738#else 739 fault = cpu->write(req, data, sqIdx); 740#endif 741 } 742 743 if (res) { 744 // always return some result to keep misspeculated paths 745 // (which will ignore faults) deterministic 746 *res = (fault == NoFault) ? req->getScResult() : 0; 747 } 748 749 return fault; 750} 751 752#endif // __CPU_BASE_DYN_INST_HH__ 753