base_dyn_inst.hh revision 1464
13900Ssaidi@eecs.umich.edu/* 22632Sstever@eecs.umich.edu * Copyright (c) 2001-2004 The Regents of The University of Michigan 32632Sstever@eecs.umich.edu * All rights reserved. 42632Sstever@eecs.umich.edu * 52632Sstever@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 62632Sstever@eecs.umich.edu * modification, are permitted provided that the following conditions are 72632Sstever@eecs.umich.edu * met: redistributions of source code must retain the above copyright 82632Sstever@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 92632Sstever@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 102632Sstever@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 112632Sstever@eecs.umich.edu * documentation and/or other materials provided with the distribution; 122632Sstever@eecs.umich.edu * neither the name of the copyright holders nor the names of its 132632Sstever@eecs.umich.edu * contributors may be used to endorse or promote products derived from 142632Sstever@eecs.umich.edu * this software without specific prior written permission. 152632Sstever@eecs.umich.edu * 162632Sstever@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172632Sstever@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182632Sstever@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192632Sstever@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202632Sstever@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212632Sstever@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222632Sstever@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232632Sstever@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242632Sstever@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252632Sstever@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262632Sstever@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272632Sstever@eecs.umich.edu */ 282632Sstever@eecs.umich.edu 292632Sstever@eecs.umich.edu#ifndef __CPU_BASE_DYN_INST_HH__ 302632Sstever@eecs.umich.edu#define __CPU_BASE_DYN_INST_HH__ 312022SN/A 322022SN/A#include <string> 332022SN/A#include <vector> 342022SN/A 352022SN/A#include "base/fast_alloc.hh" 362469SN/A#include "base/trace.hh" 372469SN/A 382469SN/A#include "cpu/beta_cpu/comm.hh" 392469SN/A#include "cpu/exetrace.hh" 402516SN/A#include "cpu/full_cpu/bpred_update.hh" 412516SN/A#include "cpu/full_cpu/op_class.hh" 422944Sgblack@eecs.umich.edu#include "cpu/full_cpu/spec_memory.hh" 432482SN/A#include "cpu/full_cpu/spec_state.hh" 443598Sgblack@eecs.umich.edu#include "cpu/inst_seq.hh" 453056Sgblack@eecs.umich.edu#include "cpu/static_inst.hh" 462469SN/A#include "mem/functional_mem/main_memory.hh" 473056Sgblack@eecs.umich.edu 485091Sgblack@eecs.umich.edu/** 495091Sgblack@eecs.umich.edu * @file 505091Sgblack@eecs.umich.edu * Defines a dynamic instruction context. 515091Sgblack@eecs.umich.edu */ 523056Sgblack@eecs.umich.edu 535091Sgblack@eecs.umich.edu// Forward declaration. 545091Sgblack@eecs.umich.edutemplate <class ISA> 555091Sgblack@eecs.umich.educlass StaticInstPtr; 565091Sgblack@eecs.umich.edu 575091Sgblack@eecs.umich.edutemplate <class Impl> 583056Sgblack@eecs.umich.educlass BaseDynInst : public FastAlloc, public RefCounted 593056Sgblack@eecs.umich.edu{ 605091Sgblack@eecs.umich.edu public: 615091Sgblack@eecs.umich.edu // Typedef for the CPU. 623056Sgblack@eecs.umich.edu typedef typename Impl::FullCPU FullCPU; 632482SN/A 643598Sgblack@eecs.umich.edu //Typedef to get the ISA. 653598Sgblack@eecs.umich.edu typedef typename Impl::ISA ISA; 663598Sgblack@eecs.umich.edu 673598Sgblack@eecs.umich.edu /// Binary machine instruction type. 685091Sgblack@eecs.umich.edu typedef typename ISA::MachInst MachInst; 695091Sgblack@eecs.umich.edu /// Memory address type. 705091Sgblack@eecs.umich.edu typedef typename ISA::Addr Addr; 715091Sgblack@eecs.umich.edu /// Logical register index type. 723598Sgblack@eecs.umich.edu typedef typename ISA::RegIndex RegIndex; 735091Sgblack@eecs.umich.edu /// Integer register index type. 745091Sgblack@eecs.umich.edu typedef typename ISA::IntReg IntReg; 755091Sgblack@eecs.umich.edu 765091Sgblack@eecs.umich.edu enum { 775091Sgblack@eecs.umich.edu MaxInstSrcRegs = ISA::MaxInstSrcRegs, //< Max source regs 785091Sgblack@eecs.umich.edu MaxInstDestRegs = ISA::MaxInstDestRegs, //< Max dest regs 793598Sgblack@eecs.umich.edu }; 802516SN/A 812516SN/A StaticInstPtr<ISA> staticInst; 822516SN/A 832516SN/A //////////////////////////////////////////// 842482SN/A // 855091Sgblack@eecs.umich.edu // INSTRUCTION EXECUTION 865091Sgblack@eecs.umich.edu // 875091Sgblack@eecs.umich.edu //////////////////////////////////////////// 885091Sgblack@eecs.umich.edu Trace::InstRecord *traceData; 895091Sgblack@eecs.umich.edu 905091Sgblack@eecs.umich.edu template <class T> 912469SN/A Fault read(Addr addr, T &data, unsigned flags); 922482SN/A 932516SN/A template <class T> 943042Sgblack@eecs.umich.edu Fault write(T data, Addr addr, unsigned flags, 954004Sgblack@eecs.umich.edu uint64_t *res); 964004Sgblack@eecs.umich.edu 974004Sgblack@eecs.umich.edu void prefetch(Addr addr, unsigned flags); 984004Sgblack@eecs.umich.edu void writeHint(Addr addr, int size, unsigned flags); 995091Sgblack@eecs.umich.edu Fault copySrcTranslate(Addr src); 1005091Sgblack@eecs.umich.edu Fault copy(Addr dest); 1015091Sgblack@eecs.umich.edu 1025091Sgblack@eecs.umich.edu // Probably should be private... 1034004Sgblack@eecs.umich.edu public: 1045091Sgblack@eecs.umich.edu /** Is this instruction valid. */ 1055091Sgblack@eecs.umich.edu bool valid; 1065091Sgblack@eecs.umich.edu 1075091Sgblack@eecs.umich.edu /** The sequence number of the instruction. */ 1085091Sgblack@eecs.umich.edu InstSeqNum seqNum; 1094004Sgblack@eecs.umich.edu 1105091Sgblack@eecs.umich.edu /** How many source registers are ready. */ 1115091Sgblack@eecs.umich.edu unsigned readyRegs; 1125091Sgblack@eecs.umich.edu 1135091Sgblack@eecs.umich.edu /** Is the instruction completed. */ 1145091Sgblack@eecs.umich.edu bool completed; 1155091Sgblack@eecs.umich.edu 1165091Sgblack@eecs.umich.edu /** Can this instruction issue. */ 1175091Sgblack@eecs.umich.edu bool canIssue; 1184004Sgblack@eecs.umich.edu 1194004Sgblack@eecs.umich.edu /** Has this instruction issued. */ 1204004Sgblack@eecs.umich.edu bool issued; 1214004Sgblack@eecs.umich.edu 1224004Sgblack@eecs.umich.edu /** Has this instruction executed (or made it through execute) yet. */ 1234004Sgblack@eecs.umich.edu bool executed; 1244004Sgblack@eecs.umich.edu 1255091Sgblack@eecs.umich.edu /** Can this instruction commit. */ 1265091Sgblack@eecs.umich.edu bool canCommit; 1275091Sgblack@eecs.umich.edu 1285091Sgblack@eecs.umich.edu /** Is this instruction squashed. */ 1294004Sgblack@eecs.umich.edu bool squashed; 1305091Sgblack@eecs.umich.edu 1315091Sgblack@eecs.umich.edu /** Is this instruction squashed in the instruction queue. */ 1325091Sgblack@eecs.umich.edu bool squashedInIQ; 1335091Sgblack@eecs.umich.edu 1345091Sgblack@eecs.umich.edu /** Is this a recover instruction. */ 1355091Sgblack@eecs.umich.edu bool recoverInst; 1365091Sgblack@eecs.umich.edu 1374004Sgblack@eecs.umich.edu /** Is this a thread blocking instruction. */ 1384004Sgblack@eecs.umich.edu bool blockingInst; /* this inst has called thread_block() */ 1392469SN/A 1402944Sgblack@eecs.umich.edu /** Is this a thread syncrhonization instruction. */ 1413928Ssaidi@eecs.umich.edu bool threadsyncWait; 1423928Ssaidi@eecs.umich.edu 1433928Ssaidi@eecs.umich.edu /** The thread this instruction is from. */ 1443928Ssaidi@eecs.umich.edu short threadNumber; 1452516SN/A 1462469SN/A /** data address space ID, for loads & stores. */ 1472469SN/A short asid; 1482482SN/A 1492482SN/A /** Pointer to the FullCPU object. */ 1502974Sgblack@eecs.umich.edu FullCPU *cpu; 1512974Sgblack@eecs.umich.edu 1522974Sgblack@eecs.umich.edu /** Pointer to the exec context. Will not exist in the final version. */ 1532526SN/A ExecContext *xc; 1542974Sgblack@eecs.umich.edu 1552974Sgblack@eecs.umich.edu /** The kind of fault this instruction has generated. */ 1562974Sgblack@eecs.umich.edu Fault fault; 1572646Ssaidi@eecs.umich.edu 1582974Sgblack@eecs.umich.edu /** The effective virtual address (lds & stores only). */ 1592469SN/A Addr effAddr; 1602516SN/A 1612646Ssaidi@eecs.umich.edu /** The effective physical address. */ 1622482SN/A Addr physEffAddr; 1632469SN/A 1643931Ssaidi@eecs.umich.edu /** Effective virtual address for a copy source. */ 1653900Ssaidi@eecs.umich.edu Addr copySrcEffAddr; 1662482SN/A 1672954Sgblack@eecs.umich.edu /** Effective physical address for a copy source. */ 1682469SN/A Addr copySrcPhysEffAddr; 1692516SN/A 1702516SN/A /** The memory request flags (from translation). */ 1712482SN/A unsigned memReqFlags; 1722469SN/A 1732516SN/A /** The size of the data to be stored. */ 1742482SN/A int storeSize; 1752482SN/A 1762646Ssaidi@eecs.umich.edu /** The data to be stored. */ 1772482SN/A IntReg storeData; 1782482SN/A 1792482SN/A union Result { 1802482SN/A uint64_t integer; 1812482SN/A float fp; 1822615SN/A double dbl; 1832469SN/A }; 1842469SN/A 1852482SN/A /** The result of the instruction; assumes for now that there's only one 1862646Ssaidi@eecs.umich.edu * destination register. 1873929Ssaidi@eecs.umich.edu */ 1882482SN/A Result instResult; 1893929Ssaidi@eecs.umich.edu 1903929Ssaidi@eecs.umich.edu /** PC of this instruction. */ 1912482SN/A Addr PC; 1922526SN/A 1932469SN/A /** Next non-speculative PC. It is not filled in at fetch, but rather 1942482SN/A * once the target of the branch is truly known (either decode or 1952469SN/A * execute). 1965093Sgblack@eecs.umich.edu */ 1975093Sgblack@eecs.umich.edu Addr nextPC; 1985093Sgblack@eecs.umich.edu 1992482SN/A /** Predicted next PC. */ 2002482SN/A Addr predPC; 2012482SN/A 2022469SN/A /** Count of total number of dynamic instructions. */ 2035093Sgblack@eecs.umich.edu static int instcount; 2045093Sgblack@eecs.umich.edu 2055093Sgblack@eecs.umich.edu /** Whether or not the source register is ready. Not sure this should be 2062482SN/A * here vs. the derived class. 2072482SN/A */ 2082482SN/A bool _readySrcRegIdx[MaxInstSrcRegs]; 2092469SN/A 2105093Sgblack@eecs.umich.edu public: 2115093Sgblack@eecs.umich.edu /** BaseDynInst constructor given a binary instruction. */ 2125093Sgblack@eecs.umich.edu BaseDynInst(MachInst inst, Addr PC, Addr Pred_PC, InstSeqNum seq_num, 2133765Sgblack@eecs.umich.edu FullCPU *cpu); 2142615SN/A 2152615SN/A /** BaseDynInst constructor given a static inst pointer. */ 2163765Sgblack@eecs.umich.edu BaseDynInst(StaticInstPtr<ISA> &_staticInst); 2173765Sgblack@eecs.umich.edu 2182615SN/A /** BaseDynInst destructor. */ 2193931Ssaidi@eecs.umich.edu ~BaseDynInst(); 2203765Sgblack@eecs.umich.edu 2212469SN/A private: 2225093Sgblack@eecs.umich.edu void initVars(); 2235093Sgblack@eecs.umich.edu 2245093Sgblack@eecs.umich.edu public: 2253765Sgblack@eecs.umich.edu void 2262615SN/A trace_mem(Fault fault, // last fault 2273765Sgblack@eecs.umich.edu MemCmd cmd, // last command 2285093Sgblack@eecs.umich.edu Addr addr, // virtual address of access 2295093Sgblack@eecs.umich.edu void *p, // memory accessed 2305093Sgblack@eecs.umich.edu int nbytes); // access size 2315093Sgblack@eecs.umich.edu 2325093Sgblack@eecs.umich.edu /** Dumps out contents of this BaseDynInst. */ 2335093Sgblack@eecs.umich.edu void dump(); 2345093Sgblack@eecs.umich.edu 2355093Sgblack@eecs.umich.edu /** Dumps out contents of this BaseDynInst into given string. */ 2365093Sgblack@eecs.umich.edu void dump(std::string &outstring); 2375093Sgblack@eecs.umich.edu 2385093Sgblack@eecs.umich.edu /** Returns the fault type. */ 2395093Sgblack@eecs.umich.edu Fault getFault() { return fault; } 2405093Sgblack@eecs.umich.edu 2415093Sgblack@eecs.umich.edu /** Checks whether or not this instruction has had its branch target 2425093Sgblack@eecs.umich.edu * calculated yet. For now it is not utilized and is hacked to be 2435093Sgblack@eecs.umich.edu * always false. 2445093Sgblack@eecs.umich.edu */ 2455093Sgblack@eecs.umich.edu bool doneTargCalc() { return false; } 2465093Sgblack@eecs.umich.edu 2475093Sgblack@eecs.umich.edu /** Returns the calculated target of the branch. */ 2485093Sgblack@eecs.umich.edu// Addr readCalcTarg() { return nextPC; } 2495093Sgblack@eecs.umich.edu 2505093Sgblack@eecs.umich.edu Addr readNextPC() { return nextPC; } 2515093Sgblack@eecs.umich.edu 2525093Sgblack@eecs.umich.edu /** Set the predicted target of this current instruction. */ 2532469SN/A void setPredTarg(Addr predicted_PC) { predPC = predicted_PC; } 2545093Sgblack@eecs.umich.edu 2555093Sgblack@eecs.umich.edu /** Returns the predicted target of the branch. */ 2565093Sgblack@eecs.umich.edu Addr readPredTarg() { return predPC; } 2575093Sgblack@eecs.umich.edu 2585093Sgblack@eecs.umich.edu /** Returns whether the instruction was predicted taken or not. */ 2595093Sgblack@eecs.umich.edu bool predTaken() { 2602469SN/A return( predPC != (PC + sizeof(MachInst) ) ); 2615093Sgblack@eecs.umich.edu } 2625093Sgblack@eecs.umich.edu 2635093Sgblack@eecs.umich.edu /** Returns whether the instruction mispredicted. */ 2645093Sgblack@eecs.umich.edu bool mispredicted() { return (predPC != nextPC); } 2655093Sgblack@eecs.umich.edu 2665093Sgblack@eecs.umich.edu // 2672469SN/A // Instruction types. Forward checks to StaticInst object. 2685093Sgblack@eecs.umich.edu // 2695093Sgblack@eecs.umich.edu bool isNop() const { return staticInst->isNop(); } 2705093Sgblack@eecs.umich.edu bool isMemRef() const { return staticInst->isMemRef(); } 2715093Sgblack@eecs.umich.edu bool isLoad() const { return staticInst->isLoad(); } 2725093Sgblack@eecs.umich.edu bool isStore() const { return staticInst->isStore(); } 2735093Sgblack@eecs.umich.edu bool isInstPrefetch() const { return staticInst->isInstPrefetch(); } 2742469SN/A bool isDataPrefetch() const { return staticInst->isDataPrefetch(); } 2755093Sgblack@eecs.umich.edu bool isCopy() const { return staticInst->isCopy(); } 2765093Sgblack@eecs.umich.edu bool isInteger() const { return staticInst->isInteger(); } 2775093Sgblack@eecs.umich.edu bool isFloating() const { return staticInst->isFloating(); } 2785093Sgblack@eecs.umich.edu bool isControl() const { return staticInst->isControl(); } 2795093Sgblack@eecs.umich.edu bool isCall() const { return staticInst->isCall(); } 2805093Sgblack@eecs.umich.edu bool isReturn() const { return staticInst->isReturn(); } 2812469SN/A bool isDirectCtrl() const { return staticInst->isDirectCtrl(); } 2825093Sgblack@eecs.umich.edu bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); } 2834237Sgblack@eecs.umich.edu bool isCondCtrl() const { return staticInst->isCondCtrl(); } 2845093Sgblack@eecs.umich.edu bool isUncondCtrl() const { return staticInst->isUncondCtrl(); } 2855093Sgblack@eecs.umich.edu bool isThreadSync() const { return staticInst->isThreadSync(); } 2865093Sgblack@eecs.umich.edu bool isSerializing() const { return staticInst->isSerializing(); } 2875093Sgblack@eecs.umich.edu bool isMemBarrier() const { return staticInst->isMemBarrier(); } 2885093Sgblack@eecs.umich.edu bool isWriteBarrier() const { return staticInst->isWriteBarrier(); } 2895093Sgblack@eecs.umich.edu bool isNonSpeculative() const { return staticInst->isNonSpeculative(); } 2905093Sgblack@eecs.umich.edu 2915093Sgblack@eecs.umich.edu /** Returns the opclass of this instruction. */ 2925093Sgblack@eecs.umich.edu OpClass opClass() const { return staticInst->opClass(); } 2935093Sgblack@eecs.umich.edu 2945093Sgblack@eecs.umich.edu /** Returns the branch target address. */ 2955093Sgblack@eecs.umich.edu Addr branchTarget() const { return staticInst->branchTarget(PC); } 2962526SN/A 2972526SN/A int8_t numSrcRegs() const { return staticInst->numSrcRegs(); } 2982526SN/A int8_t numDestRegs() const { return staticInst->numDestRegs(); } 2992526SN/A 3002526SN/A // the following are used to track physical register usage 3012526SN/A // for machines with separate int & FP reg files 3022469SN/A int8_t numFPDestRegs() const { return staticInst->numFPDestRegs(); } 3032526SN/A int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); } 3042526SN/A 3052526SN/A /** Returns the logical register index of the i'th destination register. */ 3062526SN/A RegIndex destRegIdx(int i) const 3072526SN/A { 3082526SN/A return staticInst->destRegIdx(i); 3092526SN/A } 3102526SN/A 3112954Sgblack@eecs.umich.edu /** Returns the logical register index of the i'th source register. */ 3123929Ssaidi@eecs.umich.edu RegIndex srcRegIdx(int i) const 3133587Sgblack@eecs.umich.edu { 3143587Sgblack@eecs.umich.edu return staticInst->srcRegIdx(i); 3153587Sgblack@eecs.umich.edu } 3163823Ssaidi@eecs.umich.edu 3173587Sgblack@eecs.umich.edu uint64_t readIntResult() { return instResult.integer; } 3183587Sgblack@eecs.umich.edu float readFloatResult() { return instResult.fp; } 3193587Sgblack@eecs.umich.edu double readDoubleResult() { return instResult.dbl; } 3203587Sgblack@eecs.umich.edu 3213587Sgblack@eecs.umich.edu //Push to .cc file. 3223587Sgblack@eecs.umich.edu /** Records that one of the source registers is ready. */ 3233587Sgblack@eecs.umich.edu void markSrcRegReady() 3243587Sgblack@eecs.umich.edu { 3253587Sgblack@eecs.umich.edu ++readyRegs; 3263587Sgblack@eecs.umich.edu if(readyRegs == numSrcRegs()) { 3273587Sgblack@eecs.umich.edu canIssue = true; 3284040Ssaidi@eecs.umich.edu } 3294040Ssaidi@eecs.umich.edu } 3302954Sgblack@eecs.umich.edu 3313587Sgblack@eecs.umich.edu void markSrcRegReady(RegIndex src_idx) 3323587Sgblack@eecs.umich.edu { 3333587Sgblack@eecs.umich.edu ++readyRegs; 3343587Sgblack@eecs.umich.edu 3354010Ssaidi@eecs.umich.edu _readySrcRegIdx[src_idx] = 1; 3364010Ssaidi@eecs.umich.edu 3374010Ssaidi@eecs.umich.edu if(readyRegs == numSrcRegs()) { 3384010Ssaidi@eecs.umich.edu canIssue = true; 3392954Sgblack@eecs.umich.edu } 3403587Sgblack@eecs.umich.edu } 3413587Sgblack@eecs.umich.edu 3423823Ssaidi@eecs.umich.edu bool isReadySrcRegIdx(int idx) const 3433823Ssaidi@eecs.umich.edu { 3443823Ssaidi@eecs.umich.edu return this->_readySrcRegIdx[idx]; 3453598Sgblack@eecs.umich.edu } 3463598Sgblack@eecs.umich.edu 3473598Sgblack@eecs.umich.edu void setCompleted() { completed = true; } 3483598Sgblack@eecs.umich.edu 3493598Sgblack@eecs.umich.edu bool isCompleted() const { return completed; } 3503598Sgblack@eecs.umich.edu 3513598Sgblack@eecs.umich.edu /** Sets this instruction as ready to issue. */ 3523598Sgblack@eecs.umich.edu void setCanIssue() { canIssue = true; } 3533598Sgblack@eecs.umich.edu 3542954Sgblack@eecs.umich.edu /** Returns whether or not this instruction is ready to issue. */ 3553587Sgblack@eecs.umich.edu bool readyToIssue() const { return canIssue; } 3563587Sgblack@eecs.umich.edu 3573587Sgblack@eecs.umich.edu /** Sets this instruction as issued from the IQ. */ 3583587Sgblack@eecs.umich.edu void setIssued() { issued = true; } 3593587Sgblack@eecs.umich.edu 3603587Sgblack@eecs.umich.edu /** Returns whether or not this instruction has issued. */ 3613587Sgblack@eecs.umich.edu bool isIssued() const { return issued; } 3623587Sgblack@eecs.umich.edu 3633587Sgblack@eecs.umich.edu /** Sets this instruction as executed. */ 3643587Sgblack@eecs.umich.edu void setExecuted() { executed = true; } 3653587Sgblack@eecs.umich.edu 3663587Sgblack@eecs.umich.edu /** Returns whether or not this instruction has executed. */ 3673587Sgblack@eecs.umich.edu bool isExecuted() const { return executed; } 3683823Ssaidi@eecs.umich.edu 3693587Sgblack@eecs.umich.edu /** Sets this instruction as ready to commit. */ 3703587Sgblack@eecs.umich.edu void setCanCommit() { canCommit = true; } 3713587Sgblack@eecs.umich.edu 3723587Sgblack@eecs.umich.edu /** Clears this instruction as being ready to commit. */ 3733587Sgblack@eecs.umich.edu void clearCanCommit() { canCommit = false; } 3743587Sgblack@eecs.umich.edu 3753587Sgblack@eecs.umich.edu /** Returns whether or not this instruction is ready to commit. */ 3763587Sgblack@eecs.umich.edu bool readyToCommit() const { return canCommit; } 3773587Sgblack@eecs.umich.edu 3783587Sgblack@eecs.umich.edu /** Sets this instruction as squashed. */ 3793587Sgblack@eecs.umich.edu void setSquashed() { squashed = true; } 3803587Sgblack@eecs.umich.edu 3813587Sgblack@eecs.umich.edu /** Returns whether or not this instruction is squashed. */ 3823587Sgblack@eecs.umich.edu bool isSquashed() const { return squashed; } 3833587Sgblack@eecs.umich.edu 3843587Sgblack@eecs.umich.edu /** Sets this instruction as squashed in the IQ. */ 3853587Sgblack@eecs.umich.edu void setSquashedInIQ() { squashedInIQ = true; } 3863587Sgblack@eecs.umich.edu 3873587Sgblack@eecs.umich.edu /** Returns whether or not this instruction is squashed in the IQ. */ 3883587Sgblack@eecs.umich.edu bool isSquashedInIQ() const { return squashedInIQ; } 3893587Sgblack@eecs.umich.edu 3903587Sgblack@eecs.umich.edu /** Read the PC of this instruction. */ 3913823Ssaidi@eecs.umich.edu const Addr readPC() const { return PC; } 3923587Sgblack@eecs.umich.edu 3933587Sgblack@eecs.umich.edu /** Set the next PC of this instruction (its actual target). */ 3943587Sgblack@eecs.umich.edu void setNextPC(uint64_t val) { nextPC = val; } 3953587Sgblack@eecs.umich.edu 3963587Sgblack@eecs.umich.edu ExecContext *xcBase() { return xc; } 3973587Sgblack@eecs.umich.edu 3983587Sgblack@eecs.umich.edu private: 3993587Sgblack@eecs.umich.edu Addr instEffAddr; 4003587Sgblack@eecs.umich.edu bool eaCalcDone; 4013587Sgblack@eecs.umich.edu 4023587Sgblack@eecs.umich.edu public: 4033587Sgblack@eecs.umich.edu void setEA(Addr &ea) { instEffAddr = ea; eaCalcDone = true; } 4043587Sgblack@eecs.umich.edu const Addr &getEA() const { return instEffAddr; } 4053587Sgblack@eecs.umich.edu bool doneEACalc() { return eaCalcDone; } 4062526SN/A bool eaSrcsReady(); 4073911Ssaidi@eecs.umich.edu}; 4082526SN/A 4092526SN/Atemplate<class Impl> 4103909Ssaidi@eecs.umich.edutemplate<class T> 4112526SN/Ainline Fault 4123909Ssaidi@eecs.umich.eduBaseDynInst<Impl>::read(Addr addr, T &data, unsigned flags) 4132526SN/A{ 4142526SN/A MemReqPtr req = new MemReq(addr, xc, sizeof(T), flags); 4152526SN/A req->asid = asid; 4162469SN/A 4172526SN/A fault = cpu->translateDataReadReq(req); 4182526SN/A 4192526SN/A // Record key MemReq parameters so we can generate another one 4202526SN/A // just like it for the timing access without calling translate() 4212646Ssaidi@eecs.umich.edu // again (which might mess up the TLB). 4222591SN/A effAddr = req->vaddr; 4232591SN/A physEffAddr = req->paddr; 4242591SN/A memReqFlags = req->flags; 4252526SN/A 4262526SN/A /** 4272646Ssaidi@eecs.umich.edu * @todo 4282591SN/A * Replace the disjoint functional memory with a unified one and remove 4292591SN/A * this hack. 4302591SN/A */ 4312526SN/A#ifndef FULL_SYSTEM 4322224SN/A req->paddr = req->vaddr; 4332526SN/A#endif 4342526SN/A 4352615SN/A if (fault == No_Fault) { 4362615SN/A fault = cpu->read(req, data); 4372526SN/A } 4383941Ssaidi@eecs.umich.edu else { 4392526SN/A // Return a fixed value to keep simulation deterministic even 4402526SN/A // along misspeculated paths. 4412615SN/A data = (T)-1; 4422615SN/A } 4432615SN/A 4442615SN/A if (traceData) { 4452615SN/A traceData->setAddr(addr); 4462615SN/A traceData->setData(data); 4472526SN/A } 4483587Sgblack@eecs.umich.edu 4493929Ssaidi@eecs.umich.edu return fault; 4503587Sgblack@eecs.umich.edu} 4513587Sgblack@eecs.umich.edu 4523826Ssaidi@eecs.umich.edutemplate<class Impl> 4533587Sgblack@eecs.umich.edutemplate<class T> 4543587Sgblack@eecs.umich.eduinline Fault 4553587Sgblack@eecs.umich.eduBaseDynInst<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res) 4563587Sgblack@eecs.umich.edu{ 4573587Sgblack@eecs.umich.edu if (traceData) { 4583587Sgblack@eecs.umich.edu traceData->setAddr(addr); 4593587Sgblack@eecs.umich.edu traceData->setData(data); 4603587Sgblack@eecs.umich.edu } 4613587Sgblack@eecs.umich.edu 4623587Sgblack@eecs.umich.edu storeSize = sizeof(T); 4633587Sgblack@eecs.umich.edu storeData = data; 4643587Sgblack@eecs.umich.edu 4653587Sgblack@eecs.umich.edu MemReqPtr req = new MemReq(addr, xc, sizeof(T), flags); 4663587Sgblack@eecs.umich.edu 4673587Sgblack@eecs.umich.edu req->asid = asid; 4683823Ssaidi@eecs.umich.edu 4693587Sgblack@eecs.umich.edu fault = cpu->translateDataWriteReq(req); 4703587Sgblack@eecs.umich.edu 4713587Sgblack@eecs.umich.edu // Record key MemReq parameters so we can generate another one 4723823Ssaidi@eecs.umich.edu // just like it for the timing access without calling translate() 4733587Sgblack@eecs.umich.edu // again (which might mess up the TLB). 4743823Ssaidi@eecs.umich.edu effAddr = req->vaddr; 4753598Sgblack@eecs.umich.edu physEffAddr = req->paddr; 4763598Sgblack@eecs.umich.edu memReqFlags = req->flags; 4773598Sgblack@eecs.umich.edu 4783598Sgblack@eecs.umich.edu /** 4793598Sgblack@eecs.umich.edu * @todo 4803598Sgblack@eecs.umich.edu * Replace the disjoint functional memory with a unified one and remove 4813587Sgblack@eecs.umich.edu * this hack. 4822526SN/A */ 4833417Sgblack@eecs.umich.edu#ifndef FULL_SYSTEM 4843417Sgblack@eecs.umich.edu req->paddr = req->vaddr; 4853417Sgblack@eecs.umich.edu#endif 4863417Sgblack@eecs.umich.edu 4873417Sgblack@eecs.umich.edu if (fault == No_Fault) { 4883417Sgblack@eecs.umich.edu fault = cpu->write(req, data); 4893417Sgblack@eecs.umich.edu } 4903417Sgblack@eecs.umich.edu 4913417Sgblack@eecs.umich.edu if (res) { 4923598Sgblack@eecs.umich.edu // always return some result to keep misspeculated paths 4933417Sgblack@eecs.umich.edu // (which will ignore faults) deterministic 4943417Sgblack@eecs.umich.edu *res = (fault == No_Fault) ? req->result : 0; 4953417Sgblack@eecs.umich.edu } 4963417Sgblack@eecs.umich.edu 4973417Sgblack@eecs.umich.edu return fault; 4983417Sgblack@eecs.umich.edu} 4993417Sgblack@eecs.umich.edu 5003928Ssaidi@eecs.umich.edu#endif // __CPU_BASE_DYN_INST_HH__ 5013928Ssaidi@eecs.umich.edu