base_dyn_inst.hh revision 13954:2f400a5f2627
1/* 2 * Copyright (c) 2011, 2013, 2016-2018 ARM Limited 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved. 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating 9 * to a hardware implementation of the functionality of the software 10 * licensed hereunder. You may use the software subject to the license 11 * terms below provided that you ensure that this notice is replicated 12 * unmodified and in its entirety in all distributions of the software, 13 * modified or unmodified, in source code or in binary form. 14 * 15 * Copyright (c) 2004-2006 The Regents of The University of Michigan 16 * Copyright (c) 2009 The University of Edinburgh 17 * All rights reserved. 18 * 19 * Redistribution and use in source and binary forms, with or without 20 * modification, are permitted provided that the following conditions are 21 * met: redistributions of source code must retain the above copyright 22 * notice, this list of conditions and the following disclaimer; 23 * redistributions in binary form must reproduce the above copyright 24 * notice, this list of conditions and the following disclaimer in the 25 * documentation and/or other materials provided with the distribution; 26 * neither the name of the copyright holders nor the names of its 27 * contributors may be used to endorse or promote products derived from 28 * this software without specific prior written permission. 29 * 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 34 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 35 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 36 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 37 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 38 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 39 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 40 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 41 * 42 * Authors: Kevin Lim 43 * Timothy M. Jones 44 */ 45 46#ifndef __CPU_BASE_DYN_INST_HH__ 47#define __CPU_BASE_DYN_INST_HH__ 48 49#include <array> 50#include <bitset> 51#include <deque> 52#include <list> 53#include <string> 54 55#include "arch/generic/tlb.hh" 56#include "arch/utility.hh" 57#include "base/trace.hh" 58#include "config/the_isa.hh" 59#include "cpu/checker/cpu.hh" 60#include "cpu/exec_context.hh" 61#include "cpu/exetrace.hh" 62#include "cpu/inst_res.hh" 63#include "cpu/inst_seq.hh" 64#include "cpu/op_class.hh" 65#include "cpu/static_inst.hh" 66#include "cpu/translation.hh" 67#include "mem/packet.hh" 68#include "mem/request.hh" 69#include "sim/byteswap.hh" 70#include "sim/system.hh" 71 72/** 73 * @file 74 * Defines a dynamic instruction context. 75 */ 76 77template <class Impl> 78class BaseDynInst : public ExecContext, public RefCounted 79{ 80 public: 81 // Typedef for the CPU. 82 typedef typename Impl::CPUType ImplCPU; 83 typedef typename ImplCPU::ImplState ImplState; 84 using VecRegContainer = TheISA::VecRegContainer; 85 86 using LSQRequestPtr = typename Impl::CPUPol::LSQ::LSQRequest*; 87 using LQIterator = typename Impl::CPUPol::LSQUnit::LQIterator; 88 using SQIterator = typename Impl::CPUPol::LSQUnit::SQIterator; 89 90 // The DynInstPtr type. 91 typedef typename Impl::DynInstPtr DynInstPtr; 92 typedef RefCountingPtr<BaseDynInst<Impl> > BaseDynInstPtr; 93 94 // The list of instructions iterator type. 95 typedef typename std::list<DynInstPtr>::iterator ListIt; 96 97 enum { 98 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, /// Max source regs 99 MaxInstDestRegs = TheISA::MaxInstDestRegs /// Max dest regs 100 }; 101 102 protected: 103 enum Status { 104 IqEntry, /// Instruction is in the IQ 105 RobEntry, /// Instruction is in the ROB 106 LsqEntry, /// Instruction is in the LSQ 107 Completed, /// Instruction has completed 108 ResultReady, /// Instruction has its result 109 CanIssue, /// Instruction can issue and execute 110 Issued, /// Instruction has issued 111 Executed, /// Instruction has executed 112 CanCommit, /// Instruction can commit 113 AtCommit, /// Instruction has reached commit 114 Committed, /// Instruction has committed 115 Squashed, /// Instruction is squashed 116 SquashedInIQ, /// Instruction is squashed in the IQ 117 SquashedInLSQ, /// Instruction is squashed in the LSQ 118 SquashedInROB, /// Instruction is squashed in the ROB 119 RecoverInst, /// Is a recover instruction 120 BlockingInst, /// Is a blocking instruction 121 ThreadsyncWait, /// Is a thread synchronization instruction 122 SerializeBefore, /// Needs to serialize on 123 /// instructions ahead of it 124 SerializeAfter, /// Needs to serialize instructions behind it 125 SerializeHandled, /// Serialization has been handled 126 NumStatus 127 }; 128 129 enum Flags { 130 NotAnInst, 131 TranslationStarted, 132 TranslationCompleted, 133 PossibleLoadViolation, 134 HitExternalSnoop, 135 EffAddrValid, 136 RecordResult, 137 Predicate, 138 MemAccPredicate, 139 PredTaken, 140 IsStrictlyOrdered, 141 ReqMade, 142 MemOpDone, 143 MaxFlags 144 }; 145 146 public: 147 /** The sequence number of the instruction. */ 148 InstSeqNum seqNum; 149 150 /** The StaticInst used by this BaseDynInst. */ 151 const StaticInstPtr staticInst; 152 153 /** Pointer to the Impl's CPU object. */ 154 ImplCPU *cpu; 155 156 BaseCPU *getCpuPtr() { return cpu; } 157 158 /** Pointer to the thread state. */ 159 ImplState *thread; 160 161 /** The kind of fault this instruction has generated. */ 162 Fault fault; 163 164 /** InstRecord that tracks this instructions. */ 165 Trace::InstRecord *traceData; 166 167 protected: 168 /** The result of the instruction; assumes an instruction can have many 169 * destination registers. 170 */ 171 std::queue<InstResult> instResult; 172 173 /** PC state for this instruction. */ 174 TheISA::PCState pc; 175 176 /* An amalgamation of a lot of boolean values into one */ 177 std::bitset<MaxFlags> instFlags; 178 179 /** The status of this BaseDynInst. Several bits can be set. */ 180 std::bitset<NumStatus> status; 181 182 /** Whether or not the source register is ready. 183 * @todo: Not sure this should be here vs the derived class. 184 */ 185 std::bitset<MaxInstSrcRegs> _readySrcRegIdx; 186 187 public: 188 /** The thread this instruction is from. */ 189 ThreadID threadNumber; 190 191 /** Iterator pointing to this BaseDynInst in the list of all insts. */ 192 ListIt instListIt; 193 194 ////////////////////// Branch Data /////////////// 195 /** Predicted PC state after this instruction. */ 196 TheISA::PCState predPC; 197 198 /** The Macroop if one exists */ 199 const StaticInstPtr macroop; 200 201 /** How many source registers are ready. */ 202 uint8_t readyRegs; 203 204 public: 205 /////////////////////// Load Store Data ////////////////////// 206 /** The effective virtual address (lds & stores only). */ 207 Addr effAddr; 208 209 /** The effective physical address. */ 210 Addr physEffAddr; 211 212 /** The memory request flags (from translation). */ 213 unsigned memReqFlags; 214 215 /** data address space ID, for loads & stores. */ 216 short asid; 217 218 /** The size of the request */ 219 uint8_t effSize; 220 221 /** Pointer to the data for the memory access. */ 222 uint8_t *memData; 223 224 /** Load queue index. */ 225 int16_t lqIdx; 226 LQIterator lqIt; 227 228 /** Store queue index. */ 229 int16_t sqIdx; 230 SQIterator sqIt; 231 232 233 /////////////////////// TLB Miss ////////////////////// 234 /** 235 * Saved memory request (needed when the DTB address translation is 236 * delayed due to a hw page table walk). 237 */ 238 LSQRequestPtr savedReq; 239 240 /////////////////////// Checker ////////////////////// 241 // Need a copy of main request pointer to verify on writes. 242 RequestPtr reqToVerify; 243 244 protected: 245 /** Flattened register index of the destination registers of this 246 * instruction. 247 */ 248 std::array<RegId, TheISA::MaxInstDestRegs> _flatDestRegIdx; 249 250 /** Physical register index of the destination registers of this 251 * instruction. 252 */ 253 std::array<PhysRegIdPtr, TheISA::MaxInstDestRegs> _destRegIdx; 254 255 /** Physical register index of the source registers of this 256 * instruction. 257 */ 258 std::array<PhysRegIdPtr, TheISA::MaxInstSrcRegs> _srcRegIdx; 259 260 /** Physical register index of the previous producers of the 261 * architected destinations. 262 */ 263 std::array<PhysRegIdPtr, TheISA::MaxInstDestRegs> _prevDestRegIdx; 264 265 266 public: 267 /** Records changes to result? */ 268 void recordResult(bool f) { instFlags[RecordResult] = f; } 269 270 /** Is the effective virtual address valid. */ 271 bool effAddrValid() const { return instFlags[EffAddrValid]; } 272 void effAddrValid(bool b) { instFlags[EffAddrValid] = b; } 273 274 /** Whether or not the memory operation is done. */ 275 bool memOpDone() const { return instFlags[MemOpDone]; } 276 void memOpDone(bool f) { instFlags[MemOpDone] = f; } 277 278 bool notAnInst() const { return instFlags[NotAnInst]; } 279 void setNotAnInst() { instFlags[NotAnInst] = true; } 280 281 282 //////////////////////////////////////////// 283 // 284 // INSTRUCTION EXECUTION 285 // 286 //////////////////////////////////////////// 287 288 void demapPage(Addr vaddr, uint64_t asn) 289 { 290 cpu->demapPage(vaddr, asn); 291 } 292 void demapInstPage(Addr vaddr, uint64_t asn) 293 { 294 cpu->demapPage(vaddr, asn); 295 } 296 void demapDataPage(Addr vaddr, uint64_t asn) 297 { 298 cpu->demapPage(vaddr, asn); 299 } 300 301 Fault initiateMemRead(Addr addr, unsigned size, Request::Flags flags, 302 const std::vector<bool>& byteEnable = std::vector<bool>()); 303 304 Fault writeMem(uint8_t *data, unsigned size, Addr addr, 305 Request::Flags flags, uint64_t *res, 306 const std::vector<bool>& byteEnable = std::vector<bool>()); 307 308 Fault initiateMemAMO(Addr addr, unsigned size, Request::Flags flags, 309 AtomicOpFunctor *amo_op); 310 311 /** True if the DTB address translation has started. */ 312 bool translationStarted() const { return instFlags[TranslationStarted]; } 313 void translationStarted(bool f) { instFlags[TranslationStarted] = f; } 314 315 /** True if the DTB address translation has completed. */ 316 bool translationCompleted() const { return instFlags[TranslationCompleted]; } 317 void translationCompleted(bool f) { instFlags[TranslationCompleted] = f; } 318 319 /** True if this address was found to match a previous load and they issued 320 * out of order. If that happend, then it's only a problem if an incoming 321 * snoop invalidate modifies the line, in which case we need to squash. 322 * If nothing modified the line the order doesn't matter. 323 */ 324 bool possibleLoadViolation() const { return instFlags[PossibleLoadViolation]; } 325 void possibleLoadViolation(bool f) { instFlags[PossibleLoadViolation] = f; } 326 327 /** True if the address hit a external snoop while sitting in the LSQ. 328 * If this is true and a older instruction sees it, this instruction must 329 * reexecute 330 */ 331 bool hitExternalSnoop() const { return instFlags[HitExternalSnoop]; } 332 void hitExternalSnoop(bool f) { instFlags[HitExternalSnoop] = f; } 333 334 /** 335 * Returns true if the DTB address translation is being delayed due to a hw 336 * page table walk. 337 */ 338 bool isTranslationDelayed() const 339 { 340 return (translationStarted() && !translationCompleted()); 341 } 342 343 public: 344#ifdef DEBUG 345 void dumpSNList(); 346#endif 347 348 /** Returns the physical register index of the i'th destination 349 * register. 350 */ 351 PhysRegIdPtr renamedDestRegIdx(int idx) const 352 { 353 return _destRegIdx[idx]; 354 } 355 356 /** Returns the physical register index of the i'th source register. */ 357 PhysRegIdPtr renamedSrcRegIdx(int idx) const 358 { 359 assert(TheISA::MaxInstSrcRegs > idx); 360 return _srcRegIdx[idx]; 361 } 362 363 /** Returns the flattened register index of the i'th destination 364 * register. 365 */ 366 const RegId& flattenedDestRegIdx(int idx) const 367 { 368 return _flatDestRegIdx[idx]; 369 } 370 371 /** Returns the physical register index of the previous physical register 372 * that remapped to the same logical register index. 373 */ 374 PhysRegIdPtr prevDestRegIdx(int idx) const 375 { 376 return _prevDestRegIdx[idx]; 377 } 378 379 /** Renames a destination register to a physical register. Also records 380 * the previous physical register that the logical register mapped to. 381 */ 382 void renameDestReg(int idx, 383 PhysRegIdPtr renamed_dest, 384 PhysRegIdPtr previous_rename) 385 { 386 _destRegIdx[idx] = renamed_dest; 387 _prevDestRegIdx[idx] = previous_rename; 388 } 389 390 /** Renames a source logical register to the physical register which 391 * has/will produce that logical register's result. 392 * @todo: add in whether or not the source register is ready. 393 */ 394 void renameSrcReg(int idx, PhysRegIdPtr renamed_src) 395 { 396 _srcRegIdx[idx] = renamed_src; 397 } 398 399 /** Flattens a destination architectural register index into a logical 400 * index. 401 */ 402 void flattenDestReg(int idx, const RegId& flattened_dest) 403 { 404 _flatDestRegIdx[idx] = flattened_dest; 405 } 406 /** BaseDynInst constructor given a binary instruction. 407 * @param staticInst A StaticInstPtr to the underlying instruction. 408 * @param pc The PC state for the instruction. 409 * @param predPC The predicted next PC state for the instruction. 410 * @param seq_num The sequence number of the instruction. 411 * @param cpu Pointer to the instruction's CPU. 412 */ 413 BaseDynInst(const StaticInstPtr &staticInst, const StaticInstPtr ¯oop, 414 TheISA::PCState pc, TheISA::PCState predPC, 415 InstSeqNum seq_num, ImplCPU *cpu); 416 417 /** BaseDynInst constructor given a StaticInst pointer. 418 * @param _staticInst The StaticInst for this BaseDynInst. 419 */ 420 BaseDynInst(const StaticInstPtr &staticInst, const StaticInstPtr ¯oop); 421 422 /** BaseDynInst destructor. */ 423 ~BaseDynInst(); 424 425 private: 426 /** Function to initialize variables in the constructors. */ 427 void initVars(); 428 429 public: 430 /** Dumps out contents of this BaseDynInst. */ 431 void dump(); 432 433 /** Dumps out contents of this BaseDynInst into given string. */ 434 void dump(std::string &outstring); 435 436 /** Read this CPU's ID. */ 437 int cpuId() const { return cpu->cpuId(); } 438 439 /** Read this CPU's Socket ID. */ 440 uint32_t socketId() const { return cpu->socketId(); } 441 442 /** Read this CPU's data requestor ID */ 443 MasterID masterId() const { return cpu->dataMasterId(); } 444 445 /** Read this context's system-wide ID **/ 446 ContextID contextId() const { return thread->contextId(); } 447 448 /** Returns the fault type. */ 449 Fault getFault() const { return fault; } 450 /** TODO: This I added for the LSQRequest side to be able to modify the 451 * fault. There should be a better mechanism in place. */ 452 Fault& getFault() { return fault; } 453 454 /** Checks whether or not this instruction has had its branch target 455 * calculated yet. For now it is not utilized and is hacked to be 456 * always false. 457 * @todo: Actually use this instruction. 458 */ 459 bool doneTargCalc() { return false; } 460 461 /** Set the predicted target of this current instruction. */ 462 void setPredTarg(const TheISA::PCState &_predPC) 463 { 464 predPC = _predPC; 465 } 466 467 const TheISA::PCState &readPredTarg() { return predPC; } 468 469 /** Returns the predicted PC immediately after the branch. */ 470 Addr predInstAddr() { return predPC.instAddr(); } 471 472 /** Returns the predicted PC two instructions after the branch */ 473 Addr predNextInstAddr() { return predPC.nextInstAddr(); } 474 475 /** Returns the predicted micro PC after the branch */ 476 Addr predMicroPC() { return predPC.microPC(); } 477 478 /** Returns whether the instruction was predicted taken or not. */ 479 bool readPredTaken() 480 { 481 return instFlags[PredTaken]; 482 } 483 484 void setPredTaken(bool predicted_taken) 485 { 486 instFlags[PredTaken] = predicted_taken; 487 } 488 489 /** Returns whether the instruction mispredicted. */ 490 bool mispredicted() 491 { 492 TheISA::PCState tempPC = pc; 493 TheISA::advancePC(tempPC, staticInst); 494 return !(tempPC == predPC); 495 } 496 497 // 498 // Instruction types. Forward checks to StaticInst object. 499 // 500 bool isNop() const { return staticInst->isNop(); } 501 bool isMemRef() const { return staticInst->isMemRef(); } 502 bool isLoad() const { return staticInst->isLoad(); } 503 bool isStore() const { return staticInst->isStore(); } 504 bool isAtomic() const { return staticInst->isAtomic(); } 505 bool isStoreConditional() const 506 { return staticInst->isStoreConditional(); } 507 bool isInstPrefetch() const { return staticInst->isInstPrefetch(); } 508 bool isDataPrefetch() const { return staticInst->isDataPrefetch(); } 509 bool isInteger() const { return staticInst->isInteger(); } 510 bool isFloating() const { return staticInst->isFloating(); } 511 bool isVector() const { return staticInst->isVector(); } 512 bool isControl() const { return staticInst->isControl(); } 513 bool isCall() const { return staticInst->isCall(); } 514 bool isReturn() const { return staticInst->isReturn(); } 515 bool isDirectCtrl() const { return staticInst->isDirectCtrl(); } 516 bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); } 517 bool isCondCtrl() const { return staticInst->isCondCtrl(); } 518 bool isUncondCtrl() const { return staticInst->isUncondCtrl(); } 519 bool isCondDelaySlot() const { return staticInst->isCondDelaySlot(); } 520 bool isThreadSync() const { return staticInst->isThreadSync(); } 521 bool isSerializing() const { return staticInst->isSerializing(); } 522 bool isSerializeBefore() const 523 { return staticInst->isSerializeBefore() || status[SerializeBefore]; } 524 bool isSerializeAfter() const 525 { return staticInst->isSerializeAfter() || status[SerializeAfter]; } 526 bool isSquashAfter() const { return staticInst->isSquashAfter(); } 527 bool isMemBarrier() const { return staticInst->isMemBarrier(); } 528 bool isWriteBarrier() const { return staticInst->isWriteBarrier(); } 529 bool isNonSpeculative() const { return staticInst->isNonSpeculative(); } 530 bool isQuiesce() const { return staticInst->isQuiesce(); } 531 bool isIprAccess() const { return staticInst->isIprAccess(); } 532 bool isUnverifiable() const { return staticInst->isUnverifiable(); } 533 bool isSyscall() const { return staticInst->isSyscall(); } 534 bool isMacroop() const { return staticInst->isMacroop(); } 535 bool isMicroop() const { return staticInst->isMicroop(); } 536 bool isDelayedCommit() const { return staticInst->isDelayedCommit(); } 537 bool isLastMicroop() const { return staticInst->isLastMicroop(); } 538 bool isFirstMicroop() const { return staticInst->isFirstMicroop(); } 539 bool isMicroBranch() const { return staticInst->isMicroBranch(); } 540 541 /** Temporarily sets this instruction as a serialize before instruction. */ 542 void setSerializeBefore() { status.set(SerializeBefore); } 543 544 /** Clears the serializeBefore part of this instruction. */ 545 void clearSerializeBefore() { status.reset(SerializeBefore); } 546 547 /** Checks if this serializeBefore is only temporarily set. */ 548 bool isTempSerializeBefore() { return status[SerializeBefore]; } 549 550 /** Temporarily sets this instruction as a serialize after instruction. */ 551 void setSerializeAfter() { status.set(SerializeAfter); } 552 553 /** Clears the serializeAfter part of this instruction.*/ 554 void clearSerializeAfter() { status.reset(SerializeAfter); } 555 556 /** Checks if this serializeAfter is only temporarily set. */ 557 bool isTempSerializeAfter() { return status[SerializeAfter]; } 558 559 /** Sets the serialization part of this instruction as handled. */ 560 void setSerializeHandled() { status.set(SerializeHandled); } 561 562 /** Checks if the serialization part of this instruction has been 563 * handled. This does not apply to the temporary serializing 564 * state; it only applies to this instruction's own permanent 565 * serializing state. 566 */ 567 bool isSerializeHandled() { return status[SerializeHandled]; } 568 569 /** Returns the opclass of this instruction. */ 570 OpClass opClass() const { return staticInst->opClass(); } 571 572 /** Returns the branch target address. */ 573 TheISA::PCState branchTarget() const 574 { return staticInst->branchTarget(pc); } 575 576 /** Returns the number of source registers. */ 577 int8_t numSrcRegs() const { return staticInst->numSrcRegs(); } 578 579 /** Returns the number of destination registers. */ 580 int8_t numDestRegs() const { return staticInst->numDestRegs(); } 581 582 // the following are used to track physical register usage 583 // for machines with separate int & FP reg files 584 int8_t numFPDestRegs() const { return staticInst->numFPDestRegs(); } 585 int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); } 586 int8_t numCCDestRegs() const { return staticInst->numCCDestRegs(); } 587 int8_t numVecDestRegs() const { return staticInst->numVecDestRegs(); } 588 int8_t numVecElemDestRegs() const 589 { 590 return staticInst->numVecElemDestRegs(); 591 } 592 int8_t 593 numVecPredDestRegs() const 594 { 595 return staticInst->numVecPredDestRegs(); 596 } 597 598 /** Returns the logical register index of the i'th destination register. */ 599 const RegId& destRegIdx(int i) const { return staticInst->destRegIdx(i); } 600 601 /** Returns the logical register index of the i'th source register. */ 602 const RegId& srcRegIdx(int i) const { return staticInst->srcRegIdx(i); } 603 604 /** Return the size of the instResult queue. */ 605 uint8_t resultSize() { return instResult.size(); } 606 607 /** Pops a result off the instResult queue. 608 * If the result stack is empty, return the default value. 609 * */ 610 InstResult popResult(InstResult dflt = InstResult()) 611 { 612 if (!instResult.empty()) { 613 InstResult t = instResult.front(); 614 instResult.pop(); 615 return t; 616 } 617 return dflt; 618 } 619 620 /** Pushes a result onto the instResult queue. */ 621 /** @{ */ 622 /** Scalar result. */ 623 template<typename T> 624 void setScalarResult(T&& t) 625 { 626 if (instFlags[RecordResult]) { 627 instResult.push(InstResult(std::forward<T>(t), 628 InstResult::ResultType::Scalar)); 629 } 630 } 631 632 /** Full vector result. */ 633 template<typename T> 634 void setVecResult(T&& t) 635 { 636 if (instFlags[RecordResult]) { 637 instResult.push(InstResult(std::forward<T>(t), 638 InstResult::ResultType::VecReg)); 639 } 640 } 641 642 /** Vector element result. */ 643 template<typename T> 644 void setVecElemResult(T&& t) 645 { 646 if (instFlags[RecordResult]) { 647 instResult.push(InstResult(std::forward<T>(t), 648 InstResult::ResultType::VecElem)); 649 } 650 } 651 652 /** Predicate result. */ 653 template<typename T> 654 void setVecPredResult(T&& t) 655 { 656 if (instFlags[RecordResult]) { 657 instResult.push(InstResult(std::forward<T>(t), 658 InstResult::ResultType::VecPredReg)); 659 } 660 } 661 /** @} */ 662 663 /** Records an integer register being set to a value. */ 664 void setIntRegOperand(const StaticInst *si, int idx, RegVal val) 665 { 666 setScalarResult(val); 667 } 668 669 /** Records a CC register being set to a value. */ 670 void setCCRegOperand(const StaticInst *si, int idx, RegVal val) 671 { 672 setScalarResult(val); 673 } 674 675 /** Record a vector register being set to a value */ 676 void setVecRegOperand(const StaticInst *si, int idx, 677 const VecRegContainer& val) 678 { 679 setVecResult(val); 680 } 681 682 /** Records an fp register being set to an integer value. */ 683 void 684 setFloatRegOperandBits(const StaticInst *si, int idx, RegVal val) 685 { 686 setScalarResult(val); 687 } 688 689 /** Record a vector register being set to a value */ 690 void setVecElemOperand(const StaticInst *si, int idx, const VecElem val) 691 { 692 setVecElemResult(val); 693 } 694 695 /** Record a vector register being set to a value */ 696 void setVecPredRegOperand(const StaticInst *si, int idx, 697 const VecPredRegContainer& val) 698 { 699 setVecPredResult(val); 700 } 701 702 /** Records that one of the source registers is ready. */ 703 void markSrcRegReady(); 704 705 /** Marks a specific register as ready. */ 706 void markSrcRegReady(RegIndex src_idx); 707 708 /** Returns if a source register is ready. */ 709 bool isReadySrcRegIdx(int idx) const 710 { 711 return this->_readySrcRegIdx[idx]; 712 } 713 714 /** Sets this instruction as completed. */ 715 void setCompleted() { status.set(Completed); } 716 717 /** Returns whether or not this instruction is completed. */ 718 bool isCompleted() const { return status[Completed]; } 719 720 /** Marks the result as ready. */ 721 void setResultReady() { status.set(ResultReady); } 722 723 /** Returns whether or not the result is ready. */ 724 bool isResultReady() const { return status[ResultReady]; } 725 726 /** Sets this instruction as ready to issue. */ 727 void setCanIssue() { status.set(CanIssue); } 728 729 /** Returns whether or not this instruction is ready to issue. */ 730 bool readyToIssue() const { return status[CanIssue]; } 731 732 /** Clears this instruction being able to issue. */ 733 void clearCanIssue() { status.reset(CanIssue); } 734 735 /** Sets this instruction as issued from the IQ. */ 736 void setIssued() { status.set(Issued); } 737 738 /** Returns whether or not this instruction has issued. */ 739 bool isIssued() const { return status[Issued]; } 740 741 /** Clears this instruction as being issued. */ 742 void clearIssued() { status.reset(Issued); } 743 744 /** Sets this instruction as executed. */ 745 void setExecuted() { status.set(Executed); } 746 747 /** Returns whether or not this instruction has executed. */ 748 bool isExecuted() const { return status[Executed]; } 749 750 /** Sets this instruction as ready to commit. */ 751 void setCanCommit() { status.set(CanCommit); } 752 753 /** Clears this instruction as being ready to commit. */ 754 void clearCanCommit() { status.reset(CanCommit); } 755 756 /** Returns whether or not this instruction is ready to commit. */ 757 bool readyToCommit() const { return status[CanCommit]; } 758 759 void setAtCommit() { status.set(AtCommit); } 760 761 bool isAtCommit() { return status[AtCommit]; } 762 763 /** Sets this instruction as committed. */ 764 void setCommitted() { status.set(Committed); } 765 766 /** Returns whether or not this instruction is committed. */ 767 bool isCommitted() const { return status[Committed]; } 768 769 /** Sets this instruction as squashed. */ 770 void setSquashed() { status.set(Squashed); } 771 772 /** Returns whether or not this instruction is squashed. */ 773 bool isSquashed() const { return status[Squashed]; } 774 775 //Instruction Queue Entry 776 //----------------------- 777 /** Sets this instruction as a entry the IQ. */ 778 void setInIQ() { status.set(IqEntry); } 779 780 /** Sets this instruction as a entry the IQ. */ 781 void clearInIQ() { status.reset(IqEntry); } 782 783 /** Returns whether or not this instruction has issued. */ 784 bool isInIQ() const { return status[IqEntry]; } 785 786 /** Sets this instruction as squashed in the IQ. */ 787 void setSquashedInIQ() { status.set(SquashedInIQ); status.set(Squashed);} 788 789 /** Returns whether or not this instruction is squashed in the IQ. */ 790 bool isSquashedInIQ() const { return status[SquashedInIQ]; } 791 792 793 //Load / Store Queue Functions 794 //----------------------- 795 /** Sets this instruction as a entry the LSQ. */ 796 void setInLSQ() { status.set(LsqEntry); } 797 798 /** Sets this instruction as a entry the LSQ. */ 799 void removeInLSQ() { status.reset(LsqEntry); } 800 801 /** Returns whether or not this instruction is in the LSQ. */ 802 bool isInLSQ() const { return status[LsqEntry]; } 803 804 /** Sets this instruction as squashed in the LSQ. */ 805 void setSquashedInLSQ() { status.set(SquashedInLSQ);} 806 807 /** Returns whether or not this instruction is squashed in the LSQ. */ 808 bool isSquashedInLSQ() const { return status[SquashedInLSQ]; } 809 810 811 //Reorder Buffer Functions 812 //----------------------- 813 /** Sets this instruction as a entry the ROB. */ 814 void setInROB() { status.set(RobEntry); } 815 816 /** Sets this instruction as a entry the ROB. */ 817 void clearInROB() { status.reset(RobEntry); } 818 819 /** Returns whether or not this instruction is in the ROB. */ 820 bool isInROB() const { return status[RobEntry]; } 821 822 /** Sets this instruction as squashed in the ROB. */ 823 void setSquashedInROB() { status.set(SquashedInROB); } 824 825 /** Returns whether or not this instruction is squashed in the ROB. */ 826 bool isSquashedInROB() const { return status[SquashedInROB]; } 827 828 /** Read the PC state of this instruction. */ 829 TheISA::PCState pcState() const { return pc; } 830 831 /** Set the PC state of this instruction. */ 832 void pcState(const TheISA::PCState &val) { pc = val; } 833 834 /** Read the PC of this instruction. */ 835 Addr instAddr() const { return pc.instAddr(); } 836 837 /** Read the PC of the next instruction. */ 838 Addr nextInstAddr() const { return pc.nextInstAddr(); } 839 840 /**Read the micro PC of this instruction. */ 841 Addr microPC() const { return pc.microPC(); } 842 843 bool readPredicate() const 844 { 845 return instFlags[Predicate]; 846 } 847 848 void setPredicate(bool val) 849 { 850 instFlags[Predicate] = val; 851 852 if (traceData) { 853 traceData->setPredicate(val); 854 } 855 } 856 857 bool 858 readMemAccPredicate() const 859 { 860 return instFlags[MemAccPredicate]; 861 } 862 863 void 864 setMemAccPredicate(bool val) 865 { 866 instFlags[MemAccPredicate] = val; 867 } 868 869 /** Sets the ASID. */ 870 void setASID(short addr_space_id) { asid = addr_space_id; } 871 short getASID() { return asid; } 872 873 /** Sets the thread id. */ 874 void setTid(ThreadID tid) { threadNumber = tid; } 875 876 /** Sets the pointer to the thread state. */ 877 void setThreadState(ImplState *state) { thread = state; } 878 879 /** Returns the thread context. */ 880 ThreadContext *tcBase() { return thread->getTC(); } 881 882 public: 883 /** Returns whether or not the eff. addr. source registers are ready. */ 884 bool eaSrcsReady() const; 885 886 /** Is this instruction's memory access strictly ordered? */ 887 bool strictlyOrdered() const { return instFlags[IsStrictlyOrdered]; } 888 void strictlyOrdered(bool so) { instFlags[IsStrictlyOrdered] = so; } 889 890 /** Has this instruction generated a memory request. */ 891 bool hasRequest() const { return instFlags[ReqMade]; } 892 /** Assert this instruction has generated a memory request. */ 893 void setRequest() { instFlags[ReqMade] = true; } 894 895 /** Returns iterator to this instruction in the list of all insts. */ 896 ListIt &getInstListIt() { return instListIt; } 897 898 /** Sets iterator for this instruction in the list of all insts. */ 899 void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; } 900 901 public: 902 /** Returns the number of consecutive store conditional failures. */ 903 unsigned int readStCondFailures() const 904 { return thread->storeCondFailures; } 905 906 /** Sets the number of consecutive store conditional failures. */ 907 void setStCondFailures(unsigned int sc_failures) 908 { thread->storeCondFailures = sc_failures; } 909 910 public: 911 // monitor/mwait funtions 912 void armMonitor(Addr address) { cpu->armMonitor(threadNumber, address); } 913 bool mwait(PacketPtr pkt) { return cpu->mwait(threadNumber, pkt); } 914 void mwaitAtomic(ThreadContext *tc) 915 { return cpu->mwaitAtomic(threadNumber, tc, cpu->dtb); } 916 AddressMonitor *getAddrMonitor() 917 { return cpu->getCpuAddrMonitor(threadNumber); } 918}; 919 920template<class Impl> 921Fault 922BaseDynInst<Impl>::initiateMemRead(Addr addr, unsigned size, 923 Request::Flags flags, 924 const std::vector<bool>& byteEnable) 925{ 926 return cpu->pushRequest( 927 dynamic_cast<typename DynInstPtr::PtrType>(this), 928 /* ld */ true, nullptr, size, addr, flags, nullptr, nullptr, 929 byteEnable); 930} 931 932template<class Impl> 933Fault 934BaseDynInst<Impl>::writeMem(uint8_t *data, unsigned size, Addr addr, 935 Request::Flags flags, uint64_t *res, 936 const std::vector<bool>& byteEnable) 937{ 938 return cpu->pushRequest( 939 dynamic_cast<typename DynInstPtr::PtrType>(this), 940 /* st */ false, data, size, addr, flags, res, nullptr, byteEnable); 941} 942 943template<class Impl> 944Fault 945BaseDynInst<Impl>::initiateMemAMO(Addr addr, unsigned size, 946 Request::Flags flags, 947 AtomicOpFunctor *amo_op) 948{ 949 // atomic memory instructions do not have data to be written to memory yet 950 // since the atomic operations will be executed directly in cache/memory. 951 // Therefore, its `data` field is nullptr. 952 // Atomic memory requests need to carry their `amo_op` fields to cache/ 953 // memory 954 return cpu->pushRequest( 955 dynamic_cast<typename DynInstPtr::PtrType>(this), 956 /* atomic */ false, nullptr, size, addr, flags, nullptr, amo_op); 957} 958 959#endif // __CPU_BASE_DYN_INST_HH__ 960