base_dyn_inst.hh revision 13762:36d5a1d9f5e6 
1/*
2 * Copyright (c) 2011, 2013, 2016-2018 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder.  You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2004-2006 The Regents of The University of Michigan
16 * Copyright (c) 2009 The University of Edinburgh
17 * All rights reserved.
18 *
19 * Redistribution and use in source and binary forms, with or without
20 * modification, are permitted provided that the following conditions are
21 * met: redistributions of source code must retain the above copyright
22 * notice, this list of conditions and the following disclaimer;
23 * redistributions in binary form must reproduce the above copyright
24 * notice, this list of conditions and the following disclaimer in the
25 * documentation and/or other materials provided with the distribution;
26 * neither the name of the copyright holders nor the names of its
27 * contributors may be used to endorse or promote products derived from
28 * this software without specific prior written permission.
29 *
30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
34 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
35 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
36 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
37 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
38 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
39 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
40 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41 *
42 * Authors: Kevin Lim
43 *          Timothy M. Jones
44 */
45
46#ifndef __CPU_BASE_DYN_INST_HH__
47#define __CPU_BASE_DYN_INST_HH__
48
49#include <array>
50#include <bitset>
51#include <deque>
52#include <list>
53#include <string>
54
55#include "arch/generic/tlb.hh"
56#include "arch/utility.hh"
57#include "base/trace.hh"
58#include "config/the_isa.hh"
59#include "cpu/checker/cpu.hh"
60#include "cpu/exec_context.hh"
61#include "cpu/exetrace.hh"
62#include "cpu/inst_res.hh"
63#include "cpu/inst_seq.hh"
64#include "cpu/op_class.hh"
65#include "cpu/static_inst.hh"
66#include "cpu/translation.hh"
67#include "mem/packet.hh"
68#include "mem/request.hh"
69#include "sim/byteswap.hh"
70#include "sim/system.hh"
71
72/**
73 * @file
74 * Defines a dynamic instruction context.
75 */
76
77template <class Impl>
78class BaseDynInst : public ExecContext, public RefCounted
79{
80  public:
81    // Typedef for the CPU.
82    typedef typename Impl::CPUType ImplCPU;
83    typedef typename ImplCPU::ImplState ImplState;
84    using VecRegContainer = TheISA::VecRegContainer;
85
86    using LSQRequestPtr = typename Impl::CPUPol::LSQ::LSQRequest*;
87    using LQIterator = typename Impl::CPUPol::LSQUnit::LQIterator;
88    using SQIterator = typename Impl::CPUPol::LSQUnit::SQIterator;
89
90    // The DynInstPtr type.
91    typedef typename Impl::DynInstPtr DynInstPtr;
92    typedef RefCountingPtr<BaseDynInst<Impl> > BaseDynInstPtr;
93
94    // The list of instructions iterator type.
95    typedef typename std::list<DynInstPtr>::iterator ListIt;
96
97    enum {
98        MaxInstSrcRegs = TheISA::MaxInstSrcRegs,        /// Max source regs
99        MaxInstDestRegs = TheISA::MaxInstDestRegs       /// Max dest regs
100    };
101
102  protected:
103    enum Status {
104        IqEntry,                 /// Instruction is in the IQ
105        RobEntry,                /// Instruction is in the ROB
106        LsqEntry,                /// Instruction is in the LSQ
107        Completed,               /// Instruction has completed
108        ResultReady,             /// Instruction has its result
109        CanIssue,                /// Instruction can issue and execute
110        Issued,                  /// Instruction has issued
111        Executed,                /// Instruction has executed
112        CanCommit,               /// Instruction can commit
113        AtCommit,                /// Instruction has reached commit
114        Committed,               /// Instruction has committed
115        Squashed,                /// Instruction is squashed
116        SquashedInIQ,            /// Instruction is squashed in the IQ
117        SquashedInLSQ,           /// Instruction is squashed in the LSQ
118        SquashedInROB,           /// Instruction is squashed in the ROB
119        RecoverInst,             /// Is a recover instruction
120        BlockingInst,            /// Is a blocking instruction
121        ThreadsyncWait,          /// Is a thread synchronization instruction
122        SerializeBefore,         /// Needs to serialize on
123                                 /// instructions ahead of it
124        SerializeAfter,          /// Needs to serialize instructions behind it
125        SerializeHandled,        /// Serialization has been handled
126        NumStatus
127    };
128
129    enum Flags {
130        NotAnInst,
131        TranslationStarted,
132        TranslationCompleted,
133        PossibleLoadViolation,
134        HitExternalSnoop,
135        EffAddrValid,
136        RecordResult,
137        Predicate,
138        PredTaken,
139        IsStrictlyOrdered,
140        ReqMade,
141        MemOpDone,
142        MaxFlags
143    };
144
145  public:
146    /** The sequence number of the instruction. */
147    InstSeqNum seqNum;
148
149    /** The StaticInst used by this BaseDynInst. */
150    const StaticInstPtr staticInst;
151
152    /** Pointer to the Impl's CPU object. */
153    ImplCPU *cpu;
154
155    BaseCPU *getCpuPtr() { return cpu; }
156
157    /** Pointer to the thread state. */
158    ImplState *thread;
159
160    /** The kind of fault this instruction has generated. */
161    Fault fault;
162
163    /** InstRecord that tracks this instructions. */
164    Trace::InstRecord *traceData;
165
166  protected:
167    /** The result of the instruction; assumes an instruction can have many
168     *  destination registers.
169     */
170    std::queue<InstResult> instResult;
171
172    /** PC state for this instruction. */
173    TheISA::PCState pc;
174
175    /* An amalgamation of a lot of boolean values into one */
176    std::bitset<MaxFlags> instFlags;
177
178    /** The status of this BaseDynInst.  Several bits can be set. */
179    std::bitset<NumStatus> status;
180
181     /** Whether or not the source register is ready.
182     *  @todo: Not sure this should be here vs the derived class.
183     */
184    std::bitset<MaxInstSrcRegs> _readySrcRegIdx;
185
186  public:
187    /** The thread this instruction is from. */
188    ThreadID threadNumber;
189
190    /** Iterator pointing to this BaseDynInst in the list of all insts. */
191    ListIt instListIt;
192
193    ////////////////////// Branch Data ///////////////
194    /** Predicted PC state after this instruction. */
195    TheISA::PCState predPC;
196
197    /** The Macroop if one exists */
198    const StaticInstPtr macroop;
199
200    /** How many source registers are ready. */
201    uint8_t readyRegs;
202
203  public:
204    /////////////////////// Load Store Data //////////////////////
205    /** The effective virtual address (lds & stores only). */
206    Addr effAddr;
207
208    /** The effective physical address. */
209    Addr physEffAddr;
210
211    /** The memory request flags (from translation). */
212    unsigned memReqFlags;
213
214    /** data address space ID, for loads & stores. */
215    short asid;
216
217    /** The size of the request */
218    uint8_t effSize;
219
220    /** Pointer to the data for the memory access. */
221    uint8_t *memData;
222
223    /** Load queue index. */
224    int16_t lqIdx;
225    LQIterator lqIt;
226
227    /** Store queue index. */
228    int16_t sqIdx;
229    SQIterator sqIt;
230
231
232    /////////////////////// TLB Miss //////////////////////
233    /**
234     * Saved memory request (needed when the DTB address translation is
235     * delayed due to a hw page table walk).
236     */
237    LSQRequestPtr savedReq;
238
239    /////////////////////// Checker //////////////////////
240    // Need a copy of main request pointer to verify on writes.
241    RequestPtr reqToVerify;
242
243  protected:
244    /** Flattened register index of the destination registers of this
245     *  instruction.
246     */
247    std::array<RegId, TheISA::MaxInstDestRegs> _flatDestRegIdx;
248
249    /** Physical register index of the destination registers of this
250     *  instruction.
251     */
252    std::array<PhysRegIdPtr, TheISA::MaxInstDestRegs> _destRegIdx;
253
254    /** Physical register index of the source registers of this
255     *  instruction.
256     */
257    std::array<PhysRegIdPtr, TheISA::MaxInstSrcRegs> _srcRegIdx;
258
259    /** Physical register index of the previous producers of the
260     *  architected destinations.
261     */
262    std::array<PhysRegIdPtr, TheISA::MaxInstDestRegs> _prevDestRegIdx;
263
264
265  public:
266    /** Records changes to result? */
267    void recordResult(bool f) { instFlags[RecordResult] = f; }
268
269    /** Is the effective virtual address valid. */
270    bool effAddrValid() const { return instFlags[EffAddrValid]; }
271    void effAddrValid(bool b) { instFlags[EffAddrValid] = b; }
272
273    /** Whether or not the memory operation is done. */
274    bool memOpDone() const { return instFlags[MemOpDone]; }
275    void memOpDone(bool f) { instFlags[MemOpDone] = f; }
276
277    bool notAnInst() const { return instFlags[NotAnInst]; }
278    void setNotAnInst() { instFlags[NotAnInst] = true; }
279
280
281    ////////////////////////////////////////////
282    //
283    // INSTRUCTION EXECUTION
284    //
285    ////////////////////////////////////////////
286
287    void demapPage(Addr vaddr, uint64_t asn)
288    {
289        cpu->demapPage(vaddr, asn);
290    }
291    void demapInstPage(Addr vaddr, uint64_t asn)
292    {
293        cpu->demapPage(vaddr, asn);
294    }
295    void demapDataPage(Addr vaddr, uint64_t asn)
296    {
297        cpu->demapPage(vaddr, asn);
298    }
299
300    Fault initiateMemRead(Addr addr, unsigned size, Request::Flags flags);
301
302    Fault writeMem(uint8_t *data, unsigned size, Addr addr,
303                   Request::Flags flags, uint64_t *res);
304
305    Fault initiateMemAMO(Addr addr, unsigned size, Request::Flags flags,
306                         AtomicOpFunctor *amo_op);
307
308    /** True if the DTB address translation has started. */
309    bool translationStarted() const { return instFlags[TranslationStarted]; }
310    void translationStarted(bool f) { instFlags[TranslationStarted] = f; }
311
312    /** True if the DTB address translation has completed. */
313    bool translationCompleted() const { return instFlags[TranslationCompleted]; }
314    void translationCompleted(bool f) { instFlags[TranslationCompleted] = f; }
315
316    /** True if this address was found to match a previous load and they issued
317     * out of order. If that happend, then it's only a problem if an incoming
318     * snoop invalidate modifies the line, in which case we need to squash.
319     * If nothing modified the line the order doesn't matter.
320     */
321    bool possibleLoadViolation() const { return instFlags[PossibleLoadViolation]; }
322    void possibleLoadViolation(bool f) { instFlags[PossibleLoadViolation] = f; }
323
324    /** True if the address hit a external snoop while sitting in the LSQ.
325     * If this is true and a older instruction sees it, this instruction must
326     * reexecute
327     */
328    bool hitExternalSnoop() const { return instFlags[HitExternalSnoop]; }
329    void hitExternalSnoop(bool f) { instFlags[HitExternalSnoop] = f; }
330
331    /**
332     * Returns true if the DTB address translation is being delayed due to a hw
333     * page table walk.
334     */
335    bool isTranslationDelayed() const
336    {
337        return (translationStarted() && !translationCompleted());
338    }
339
340  public:
341#ifdef DEBUG
342    void dumpSNList();
343#endif
344
345    /** Returns the physical register index of the i'th destination
346     *  register.
347     */
348    PhysRegIdPtr renamedDestRegIdx(int idx) const
349    {
350        return _destRegIdx[idx];
351    }
352
353    /** Returns the physical register index of the i'th source register. */
354    PhysRegIdPtr renamedSrcRegIdx(int idx) const
355    {
356        assert(TheISA::MaxInstSrcRegs > idx);
357        return _srcRegIdx[idx];
358    }
359
360    /** Returns the flattened register index of the i'th destination
361     *  register.
362     */
363    const RegId& flattenedDestRegIdx(int idx) const
364    {
365        return _flatDestRegIdx[idx];
366    }
367
368    /** Returns the physical register index of the previous physical register
369     *  that remapped to the same logical register index.
370     */
371    PhysRegIdPtr prevDestRegIdx(int idx) const
372    {
373        return _prevDestRegIdx[idx];
374    }
375
376    /** Renames a destination register to a physical register.  Also records
377     *  the previous physical register that the logical register mapped to.
378     */
379    void renameDestReg(int idx,
380                       PhysRegIdPtr renamed_dest,
381                       PhysRegIdPtr previous_rename)
382    {
383        _destRegIdx[idx] = renamed_dest;
384        _prevDestRegIdx[idx] = previous_rename;
385    }
386
387    /** Renames a source logical register to the physical register which
388     *  has/will produce that logical register's result.
389     *  @todo: add in whether or not the source register is ready.
390     */
391    void renameSrcReg(int idx, PhysRegIdPtr renamed_src)
392    {
393        _srcRegIdx[idx] = renamed_src;
394    }
395
396    /** Flattens a destination architectural register index into a logical
397     * index.
398     */
399    void flattenDestReg(int idx, const RegId& flattened_dest)
400    {
401        _flatDestRegIdx[idx] = flattened_dest;
402    }
403    /** BaseDynInst constructor given a binary instruction.
404     *  @param staticInst A StaticInstPtr to the underlying instruction.
405     *  @param pc The PC state for the instruction.
406     *  @param predPC The predicted next PC state for the instruction.
407     *  @param seq_num The sequence number of the instruction.
408     *  @param cpu Pointer to the instruction's CPU.
409     */
410    BaseDynInst(const StaticInstPtr &staticInst, const StaticInstPtr &macroop,
411                TheISA::PCState pc, TheISA::PCState predPC,
412                InstSeqNum seq_num, ImplCPU *cpu);
413
414    /** BaseDynInst constructor given a StaticInst pointer.
415     *  @param _staticInst The StaticInst for this BaseDynInst.
416     */
417    BaseDynInst(const StaticInstPtr &staticInst, const StaticInstPtr &macroop);
418
419    /** BaseDynInst destructor. */
420    ~BaseDynInst();
421
422  private:
423    /** Function to initialize variables in the constructors. */
424    void initVars();
425
426  public:
427    /** Dumps out contents of this BaseDynInst. */
428    void dump();
429
430    /** Dumps out contents of this BaseDynInst into given string. */
431    void dump(std::string &outstring);
432
433    /** Read this CPU's ID. */
434    int cpuId() const { return cpu->cpuId(); }
435
436    /** Read this CPU's Socket ID. */
437    uint32_t socketId() const { return cpu->socketId(); }
438
439    /** Read this CPU's data requestor ID */
440    MasterID masterId() const { return cpu->dataMasterId(); }
441
442    /** Read this context's system-wide ID **/
443    ContextID contextId() const { return thread->contextId(); }
444
445    /** Returns the fault type. */
446    Fault getFault() const { return fault; }
447    /** TODO: This I added for the LSQRequest side to be able to modify the
448     * fault. There should be a better mechanism in place. */
449    Fault& getFault() { return fault; }
450
451    /** Checks whether or not this instruction has had its branch target
452     *  calculated yet.  For now it is not utilized and is hacked to be
453     *  always false.
454     *  @todo: Actually use this instruction.
455     */
456    bool doneTargCalc() { return false; }
457
458    /** Set the predicted target of this current instruction. */
459    void setPredTarg(const TheISA::PCState &_predPC)
460    {
461        predPC = _predPC;
462    }
463
464    const TheISA::PCState &readPredTarg() { return predPC; }
465
466    /** Returns the predicted PC immediately after the branch. */
467    Addr predInstAddr() { return predPC.instAddr(); }
468
469    /** Returns the predicted PC two instructions after the branch */
470    Addr predNextInstAddr() { return predPC.nextInstAddr(); }
471
472    /** Returns the predicted micro PC after the branch */
473    Addr predMicroPC() { return predPC.microPC(); }
474
475    /** Returns whether the instruction was predicted taken or not. */
476    bool readPredTaken()
477    {
478        return instFlags[PredTaken];
479    }
480
481    void setPredTaken(bool predicted_taken)
482    {
483        instFlags[PredTaken] = predicted_taken;
484    }
485
486    /** Returns whether the instruction mispredicted. */
487    bool mispredicted()
488    {
489        TheISA::PCState tempPC = pc;
490        TheISA::advancePC(tempPC, staticInst);
491        return !(tempPC == predPC);
492    }
493
494    //
495    //  Instruction types.  Forward checks to StaticInst object.
496    //
497    bool isNop()          const { return staticInst->isNop(); }
498    bool isMemRef()       const { return staticInst->isMemRef(); }
499    bool isLoad()         const { return staticInst->isLoad(); }
500    bool isStore()        const { return staticInst->isStore(); }
501    bool isAtomic()       const { return staticInst->isAtomic(); }
502    bool isStoreConditional() const
503    { return staticInst->isStoreConditional(); }
504    bool isInstPrefetch() const { return staticInst->isInstPrefetch(); }
505    bool isDataPrefetch() const { return staticInst->isDataPrefetch(); }
506    bool isInteger()      const { return staticInst->isInteger(); }
507    bool isFloating()     const { return staticInst->isFloating(); }
508    bool isVector()       const { return staticInst->isVector(); }
509    bool isControl()      const { return staticInst->isControl(); }
510    bool isCall()         const { return staticInst->isCall(); }
511    bool isReturn()       const { return staticInst->isReturn(); }
512    bool isDirectCtrl()   const { return staticInst->isDirectCtrl(); }
513    bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); }
514    bool isCondCtrl()     const { return staticInst->isCondCtrl(); }
515    bool isUncondCtrl()   const { return staticInst->isUncondCtrl(); }
516    bool isCondDelaySlot() const { return staticInst->isCondDelaySlot(); }
517    bool isThreadSync()   const { return staticInst->isThreadSync(); }
518    bool isSerializing()  const { return staticInst->isSerializing(); }
519    bool isSerializeBefore() const
520    { return staticInst->isSerializeBefore() || status[SerializeBefore]; }
521    bool isSerializeAfter() const
522    { return staticInst->isSerializeAfter() || status[SerializeAfter]; }
523    bool isSquashAfter() const { return staticInst->isSquashAfter(); }
524    bool isMemBarrier()   const { return staticInst->isMemBarrier(); }
525    bool isWriteBarrier() const { return staticInst->isWriteBarrier(); }
526    bool isNonSpeculative() const { return staticInst->isNonSpeculative(); }
527    bool isQuiesce() const { return staticInst->isQuiesce(); }
528    bool isIprAccess() const { return staticInst->isIprAccess(); }
529    bool isUnverifiable() const { return staticInst->isUnverifiable(); }
530    bool isSyscall() const { return staticInst->isSyscall(); }
531    bool isMacroop() const { return staticInst->isMacroop(); }
532    bool isMicroop() const { return staticInst->isMicroop(); }
533    bool isDelayedCommit() const { return staticInst->isDelayedCommit(); }
534    bool isLastMicroop() const { return staticInst->isLastMicroop(); }
535    bool isFirstMicroop() const { return staticInst->isFirstMicroop(); }
536    bool isMicroBranch() const { return staticInst->isMicroBranch(); }
537
538    /** Temporarily sets this instruction as a serialize before instruction. */
539    void setSerializeBefore() { status.set(SerializeBefore); }
540
541    /** Clears the serializeBefore part of this instruction. */
542    void clearSerializeBefore() { status.reset(SerializeBefore); }
543
544    /** Checks if this serializeBefore is only temporarily set. */
545    bool isTempSerializeBefore() { return status[SerializeBefore]; }
546
547    /** Temporarily sets this instruction as a serialize after instruction. */
548    void setSerializeAfter() { status.set(SerializeAfter); }
549
550    /** Clears the serializeAfter part of this instruction.*/
551    void clearSerializeAfter() { status.reset(SerializeAfter); }
552
553    /** Checks if this serializeAfter is only temporarily set. */
554    bool isTempSerializeAfter() { return status[SerializeAfter]; }
555
556    /** Sets the serialization part of this instruction as handled. */
557    void setSerializeHandled() { status.set(SerializeHandled); }
558
559    /** Checks if the serialization part of this instruction has been
560     *  handled.  This does not apply to the temporary serializing
561     *  state; it only applies to this instruction's own permanent
562     *  serializing state.
563     */
564    bool isSerializeHandled() { return status[SerializeHandled]; }
565
566    /** Returns the opclass of this instruction. */
567    OpClass opClass() const { return staticInst->opClass(); }
568
569    /** Returns the branch target address. */
570    TheISA::PCState branchTarget() const
571    { return staticInst->branchTarget(pc); }
572
573    /** Returns the number of source registers. */
574    int8_t numSrcRegs() const { return staticInst->numSrcRegs(); }
575
576    /** Returns the number of destination registers. */
577    int8_t numDestRegs() const { return staticInst->numDestRegs(); }
578
579    // the following are used to track physical register usage
580    // for machines with separate int & FP reg files
581    int8_t numFPDestRegs()  const { return staticInst->numFPDestRegs(); }
582    int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); }
583    int8_t numCCDestRegs() const { return staticInst->numCCDestRegs(); }
584    int8_t numVecDestRegs() const { return staticInst->numVecDestRegs(); }
585    int8_t numVecElemDestRegs() const
586    {
587        return staticInst->numVecElemDestRegs();
588    }
589    int8_t
590    numVecPredDestRegs() const
591    {
592        return staticInst->numVecPredDestRegs();
593    }
594
595    /** Returns the logical register index of the i'th destination register. */
596    const RegId& destRegIdx(int i) const { return staticInst->destRegIdx(i); }
597
598    /** Returns the logical register index of the i'th source register. */
599    const RegId& srcRegIdx(int i) const { return staticInst->srcRegIdx(i); }
600
601    /** Return the size of the instResult queue. */
602    uint8_t resultSize() { return instResult.size(); }
603
604    /** Pops a result off the instResult queue.
605     * If the result stack is empty, return the default value.
606     * */
607    InstResult popResult(InstResult dflt = InstResult())
608    {
609        if (!instResult.empty()) {
610            InstResult t = instResult.front();
611            instResult.pop();
612            return t;
613        }
614        return dflt;
615    }
616
617    /** Pushes a result onto the instResult queue. */
618    /** @{ */
619    /** Scalar result. */
620    template<typename T>
621    void setScalarResult(T&& t)
622    {
623        if (instFlags[RecordResult]) {
624            instResult.push(InstResult(std::forward<T>(t),
625                        InstResult::ResultType::Scalar));
626        }
627    }
628
629    /** Full vector result. */
630    template<typename T>
631    void setVecResult(T&& t)
632    {
633        if (instFlags[RecordResult]) {
634            instResult.push(InstResult(std::forward<T>(t),
635                        InstResult::ResultType::VecReg));
636        }
637    }
638
639    /** Vector element result. */
640    template<typename T>
641    void setVecElemResult(T&& t)
642    {
643        if (instFlags[RecordResult]) {
644            instResult.push(InstResult(std::forward<T>(t),
645                        InstResult::ResultType::VecElem));
646        }
647    }
648
649    /** Predicate result. */
650    template<typename T>
651    void setVecPredResult(T&& t)
652    {
653        if (instFlags[RecordResult]) {
654            instResult.push(InstResult(std::forward<T>(t),
655                            InstResult::ResultType::VecPredReg));
656        }
657    }
658    /** @} */
659
660    /** Records an integer register being set to a value. */
661    void setIntRegOperand(const StaticInst *si, int idx, RegVal val)
662    {
663        setScalarResult(val);
664    }
665
666    /** Records a CC register being set to a value. */
667    void setCCRegOperand(const StaticInst *si, int idx, RegVal val)
668    {
669        setScalarResult(val);
670    }
671
672    /** Record a vector register being set to a value */
673    void setVecRegOperand(const StaticInst *si, int idx,
674            const VecRegContainer& val)
675    {
676        setVecResult(val);
677    }
678
679    /** Records an fp register being set to an integer value. */
680    void
681    setFloatRegOperandBits(const StaticInst *si, int idx, RegVal val)
682    {
683        setScalarResult(val);
684    }
685
686    /** Record a vector register being set to a value */
687    void setVecElemOperand(const StaticInst *si, int idx, const VecElem val)
688    {
689        setVecElemResult(val);
690    }
691
692    /** Record a vector register being set to a value */
693    void setVecPredRegOperand(const StaticInst *si, int idx,
694                              const VecPredRegContainer& val)
695    {
696        setVecPredResult(val);
697    }
698
699    /** Records that one of the source registers is ready. */
700    void markSrcRegReady();
701
702    /** Marks a specific register as ready. */
703    void markSrcRegReady(RegIndex src_idx);
704
705    /** Returns if a source register is ready. */
706    bool isReadySrcRegIdx(int idx) const
707    {
708        return this->_readySrcRegIdx[idx];
709    }
710
711    /** Sets this instruction as completed. */
712    void setCompleted() { status.set(Completed); }
713
714    /** Returns whether or not this instruction is completed. */
715    bool isCompleted() const { return status[Completed]; }
716
717    /** Marks the result as ready. */
718    void setResultReady() { status.set(ResultReady); }
719
720    /** Returns whether or not the result is ready. */
721    bool isResultReady() const { return status[ResultReady]; }
722
723    /** Sets this instruction as ready to issue. */
724    void setCanIssue() { status.set(CanIssue); }
725
726    /** Returns whether or not this instruction is ready to issue. */
727    bool readyToIssue() const { return status[CanIssue]; }
728
729    /** Clears this instruction being able to issue. */
730    void clearCanIssue() { status.reset(CanIssue); }
731
732    /** Sets this instruction as issued from the IQ. */
733    void setIssued() { status.set(Issued); }
734
735    /** Returns whether or not this instruction has issued. */
736    bool isIssued() const { return status[Issued]; }
737
738    /** Clears this instruction as being issued. */
739    void clearIssued() { status.reset(Issued); }
740
741    /** Sets this instruction as executed. */
742    void setExecuted() { status.set(Executed); }
743
744    /** Returns whether or not this instruction has executed. */
745    bool isExecuted() const { return status[Executed]; }
746
747    /** Sets this instruction as ready to commit. */
748    void setCanCommit() { status.set(CanCommit); }
749
750    /** Clears this instruction as being ready to commit. */
751    void clearCanCommit() { status.reset(CanCommit); }
752
753    /** Returns whether or not this instruction is ready to commit. */
754    bool readyToCommit() const { return status[CanCommit]; }
755
756    void setAtCommit() { status.set(AtCommit); }
757
758    bool isAtCommit() { return status[AtCommit]; }
759
760    /** Sets this instruction as committed. */
761    void setCommitted() { status.set(Committed); }
762
763    /** Returns whether or not this instruction is committed. */
764    bool isCommitted() const { return status[Committed]; }
765
766    /** Sets this instruction as squashed. */
767    void setSquashed() { status.set(Squashed); }
768
769    /** Returns whether or not this instruction is squashed. */
770    bool isSquashed() const { return status[Squashed]; }
771
772    //Instruction Queue Entry
773    //-----------------------
774    /** Sets this instruction as a entry the IQ. */
775    void setInIQ() { status.set(IqEntry); }
776
777    /** Sets this instruction as a entry the IQ. */
778    void clearInIQ() { status.reset(IqEntry); }
779
780    /** Returns whether or not this instruction has issued. */
781    bool isInIQ() const { return status[IqEntry]; }
782
783    /** Sets this instruction as squashed in the IQ. */
784    void setSquashedInIQ() { status.set(SquashedInIQ); status.set(Squashed);}
785
786    /** Returns whether or not this instruction is squashed in the IQ. */
787    bool isSquashedInIQ() const { return status[SquashedInIQ]; }
788
789
790    //Load / Store Queue Functions
791    //-----------------------
792    /** Sets this instruction as a entry the LSQ. */
793    void setInLSQ() { status.set(LsqEntry); }
794
795    /** Sets this instruction as a entry the LSQ. */
796    void removeInLSQ() { status.reset(LsqEntry); }
797
798    /** Returns whether or not this instruction is in the LSQ. */
799    bool isInLSQ() const { return status[LsqEntry]; }
800
801    /** Sets this instruction as squashed in the LSQ. */
802    void setSquashedInLSQ() { status.set(SquashedInLSQ);}
803
804    /** Returns whether or not this instruction is squashed in the LSQ. */
805    bool isSquashedInLSQ() const { return status[SquashedInLSQ]; }
806
807
808    //Reorder Buffer Functions
809    //-----------------------
810    /** Sets this instruction as a entry the ROB. */
811    void setInROB() { status.set(RobEntry); }
812
813    /** Sets this instruction as a entry the ROB. */
814    void clearInROB() { status.reset(RobEntry); }
815
816    /** Returns whether or not this instruction is in the ROB. */
817    bool isInROB() const { return status[RobEntry]; }
818
819    /** Sets this instruction as squashed in the ROB. */
820    void setSquashedInROB() { status.set(SquashedInROB); }
821
822    /** Returns whether or not this instruction is squashed in the ROB. */
823    bool isSquashedInROB() const { return status[SquashedInROB]; }
824
825    /** Read the PC state of this instruction. */
826    TheISA::PCState pcState() const { return pc; }
827
828    /** Set the PC state of this instruction. */
829    void pcState(const TheISA::PCState &val) { pc = val; }
830
831    /** Read the PC of this instruction. */
832    Addr instAddr() const { return pc.instAddr(); }
833
834    /** Read the PC of the next instruction. */
835    Addr nextInstAddr() const { return pc.nextInstAddr(); }
836
837    /**Read the micro PC of this instruction. */
838    Addr microPC() const { return pc.microPC(); }
839
840    bool readPredicate() const
841    {
842        return instFlags[Predicate];
843    }
844
845    void setPredicate(bool val)
846    {
847        instFlags[Predicate] = val;
848
849        if (traceData) {
850            traceData->setPredicate(val);
851        }
852    }
853
854    /** Sets the ASID. */
855    void setASID(short addr_space_id) { asid = addr_space_id; }
856    short getASID() { return asid; }
857
858    /** Sets the thread id. */
859    void setTid(ThreadID tid) { threadNumber = tid; }
860
861    /** Sets the pointer to the thread state. */
862    void setThreadState(ImplState *state) { thread = state; }
863
864    /** Returns the thread context. */
865    ThreadContext *tcBase() { return thread->getTC(); }
866
867  public:
868    /** Returns whether or not the eff. addr. source registers are ready. */
869    bool eaSrcsReady() const;
870
871    /** Is this instruction's memory access strictly ordered? */
872    bool strictlyOrdered() const { return instFlags[IsStrictlyOrdered]; }
873    void strictlyOrdered(bool so) { instFlags[IsStrictlyOrdered] = so; }
874
875    /** Has this instruction generated a memory request. */
876    bool hasRequest() const { return instFlags[ReqMade]; }
877    /** Assert this instruction has generated a memory request. */
878    void setRequest() { instFlags[ReqMade] = true; }
879
880    /** Returns iterator to this instruction in the list of all insts. */
881    ListIt &getInstListIt() { return instListIt; }
882
883    /** Sets iterator for this instruction in the list of all insts. */
884    void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; }
885
886  public:
887    /** Returns the number of consecutive store conditional failures. */
888    unsigned int readStCondFailures() const
889    { return thread->storeCondFailures; }
890
891    /** Sets the number of consecutive store conditional failures. */
892    void setStCondFailures(unsigned int sc_failures)
893    { thread->storeCondFailures = sc_failures; }
894
895  public:
896    // monitor/mwait funtions
897    void armMonitor(Addr address) { cpu->armMonitor(threadNumber, address); }
898    bool mwait(PacketPtr pkt) { return cpu->mwait(threadNumber, pkt); }
899    void mwaitAtomic(ThreadContext *tc)
900    { return cpu->mwaitAtomic(threadNumber, tc, cpu->dtb); }
901    AddressMonitor *getAddrMonitor()
902    { return cpu->getCpuAddrMonitor(threadNumber); }
903};
904
905template<class Impl>
906Fault
907BaseDynInst<Impl>::initiateMemRead(Addr addr, unsigned size,
908                                   Request::Flags flags)
909{
910    return cpu->pushRequest(
911            dynamic_cast<typename DynInstPtr::PtrType>(this),
912            /* ld */ true, nullptr, size, addr, flags, nullptr);
913}
914
915template<class Impl>
916Fault
917BaseDynInst<Impl>::writeMem(uint8_t *data, unsigned size, Addr addr,
918                            Request::Flags flags, uint64_t *res)
919{
920    return cpu->pushRequest(
921            dynamic_cast<typename DynInstPtr::PtrType>(this),
922            /* st */ false, data, size, addr, flags, res);
923}
924
925template<class Impl>
926Fault
927BaseDynInst<Impl>::initiateMemAMO(Addr addr, unsigned size,
928                                  Request::Flags flags,
929                                  AtomicOpFunctor *amo_op)
930{
931    // atomic memory instructions do not have data to be written to memory yet
932    // since the atomic operations will be executed directly in cache/memory.
933    // Therefore, its `data` field is nullptr.
934    // Atomic memory requests need to carry their `amo_op` fields to cache/
935    // memory
936    return cpu->pushRequest(
937            dynamic_cast<typename DynInstPtr::PtrType>(this),
938            /* atomic */ false, nullptr, size, addr, flags, nullptr, amo_op);
939}
940
941#endif // __CPU_BASE_DYN_INST_HH__
942