base_dyn_inst.hh revision 13652:45d94ac03a27
12SN/A/* 210911Sandreas.sandberg@arm.com * Copyright (c) 2011, 2013, 2016-2018 ARM Limited 310911Sandreas.sandberg@arm.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 410911Sandreas.sandberg@arm.com * All rights reserved. 510911Sandreas.sandberg@arm.com * 610911Sandreas.sandberg@arm.com * The license below extends only to copyright in the software and shall 710911Sandreas.sandberg@arm.com * not be construed as granting a license to any other intellectual 810911Sandreas.sandberg@arm.com * property including but not limited to intellectual property relating 910911Sandreas.sandberg@arm.com * to a hardware implementation of the functionality of the software 1010911Sandreas.sandberg@arm.com * licensed hereunder. You may use the software subject to the license 1110911Sandreas.sandberg@arm.com * terms below provided that you ensure that this notice is replicated 1210911Sandreas.sandberg@arm.com * unmodified and in its entirety in all distributions of the software, 1310911Sandreas.sandberg@arm.com * modified or unmodified, in source code or in binary form. 141762SN/A * 157534Ssteve.reinhardt@amd.com * Copyright (c) 2004-2006 The Regents of The University of Michigan 162SN/A * Copyright (c) 2009 The University of Edinburgh 172SN/A * All rights reserved. 182SN/A * 192SN/A * Redistribution and use in source and binary forms, with or without 202SN/A * modification, are permitted provided that the following conditions are 212SN/A * met: redistributions of source code must retain the above copyright 222SN/A * notice, this list of conditions and the following disclaimer; 232SN/A * redistributions in binary form must reproduce the above copyright 242SN/A * notice, this list of conditions and the following disclaimer in the 252SN/A * documentation and/or other materials provided with the distribution; 262SN/A * neither the name of the copyright holders nor the names of its 272SN/A * contributors may be used to endorse or promote products derived from 282SN/A * this software without specific prior written permission. 292SN/A * 302SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 312SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 322SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 332SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 342SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 352SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 362SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 372SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 382SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 392SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 402665Ssaidi@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 412665Ssaidi@eecs.umich.edu * 422665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 432SN/A * Timothy M. Jones 442SN/A */ 452SN/A 462SN/A#ifndef __CPU_BASE_DYN_INST_HH__ 472SN/A#define __CPU_BASE_DYN_INST_HH__ 482SN/A 492SN/A#include <array> 502SN/A#include <bitset> 512SN/A#include <deque> 525491Sgblack@eecs.umich.edu#include <list> 532SN/A#include <string> 542SN/A 554762Snate@binkert.org#include "arch/generic/tlb.hh" 569342SAndreas.Sandberg@arm.com#include "arch/utility.hh" 5711800Sbrandon.potter@amd.com#include "base/trace.hh" 589356Snilay@cs.wisc.edu#include "config/the_isa.hh" 5913781Sgabeblack@google.com#include "cpu/checker/cpu.hh" 6056SN/A#include "cpu/exec_context.hh" 612SN/A#include "cpu/exetrace.hh" 6211800Sbrandon.potter@amd.com#include "cpu/inst_res.hh" 6310023Smatt.horsnell@ARM.com#include "cpu/inst_seq.hh" 6411800Sbrandon.potter@amd.com#include "cpu/o3/comm.hh" 659196SAndreas.Sandberg@arm.com#include "cpu/op_class.hh" 662SN/A#include "cpu/static_inst.hh" 672SN/A#include "cpu/translation.hh" 682SN/A#include "mem/packet.hh" 699196SAndreas.Sandberg@arm.com#include "mem/request.hh" 709196SAndreas.Sandberg@arm.com#include "sim/byteswap.hh" 719196SAndreas.Sandberg@arm.com#include "sim/system.hh" 729196SAndreas.Sandberg@arm.com 739196SAndreas.Sandberg@arm.com/** 749196SAndreas.Sandberg@arm.com * @file 759196SAndreas.Sandberg@arm.com * Defines a dynamic instruction context. 769196SAndreas.Sandberg@arm.com */ 779196SAndreas.Sandberg@arm.com 789196SAndreas.Sandberg@arm.comtemplate <class Impl> 799196SAndreas.Sandberg@arm.comclass BaseDynInst : public ExecContext, public RefCounted 809196SAndreas.Sandberg@arm.com{ 819196SAndreas.Sandberg@arm.com public: 829196SAndreas.Sandberg@arm.com // Typedef for the CPU. 839196SAndreas.Sandberg@arm.com typedef typename Impl::CPUType ImplCPU; 849196SAndreas.Sandberg@arm.com typedef typename ImplCPU::ImplState ImplState; 859196SAndreas.Sandberg@arm.com using VecRegContainer = TheISA::VecRegContainer; 869342SAndreas.Sandberg@arm.com 879196SAndreas.Sandberg@arm.com using LSQRequestPtr = typename Impl::CPUPol::LSQ::LSQRequest*; 889196SAndreas.Sandberg@arm.com using LQIterator = typename Impl::CPUPol::LSQUnit::LQIterator; 899196SAndreas.Sandberg@arm.com using SQIterator = typename Impl::CPUPol::LSQUnit::SQIterator; 909196SAndreas.Sandberg@arm.com 919196SAndreas.Sandberg@arm.com // The DynInstPtr type. 929196SAndreas.Sandberg@arm.com typedef typename Impl::DynInstPtr DynInstPtr; 939196SAndreas.Sandberg@arm.com typedef RefCountingPtr<BaseDynInst<Impl> > BaseDynInstPtr; 942SN/A 959342SAndreas.Sandberg@arm.com // The list of instructions iterator type. 962SN/A typedef typename std::list<DynInstPtr>::iterator ListIt; 972SN/A 982SN/A enum { 992SN/A MaxInstSrcRegs = TheISA::MaxInstSrcRegs, /// Max source regs 1009196SAndreas.Sandberg@arm.com MaxInstDestRegs = TheISA::MaxInstDestRegs /// Max dest regs 1012SN/A }; 1022SN/A 10310023Smatt.horsnell@ARM.com protected: 10410023Smatt.horsnell@ARM.com enum Status { 10510023Smatt.horsnell@ARM.com IqEntry, /// Instruction is in the IQ 1064762Snate@binkert.org RobEntry, /// Instruction is in the ROB 1079196SAndreas.Sandberg@arm.com LsqEntry, /// Instruction is in the LSQ 1084762Snate@binkert.org Completed, /// Instruction has completed 1094762Snate@binkert.org ResultReady, /// Instruction has its result 1102SN/A CanIssue, /// Instruction can issue and execute 1114762Snate@binkert.org Issued, /// Instruction has issued 1124762Snate@binkert.org Executed, /// Instruction has executed 1134762Snate@binkert.org CanCommit, /// Instruction can commit 11410422Sandreas.hansson@arm.com AtCommit, /// Instruction has reached commit 1152SN/A Committed, /// Instruction has committed 1165034Smilesck@eecs.umich.edu Squashed, /// Instruction is squashed 1175034Smilesck@eecs.umich.edu SquashedInIQ, /// Instruction is squashed in the IQ 1181553SN/A SquashedInLSQ, /// Instruction is squashed in the LSQ 119265SN/A SquashedInROB, /// Instruction is squashed in the ROB 1207532Ssteve.reinhardt@amd.com RecoverInst, /// Is a recover instruction 1217532Ssteve.reinhardt@amd.com BlockingInst, /// Is a blocking instruction 1227532Ssteve.reinhardt@amd.com ThreadsyncWait, /// Is a thread synchronization instruction 1237532Ssteve.reinhardt@amd.com SerializeBefore, /// Needs to serialize on 1247532Ssteve.reinhardt@amd.com /// instructions ahead of it 1257532Ssteve.reinhardt@amd.com SerializeAfter, /// Needs to serialize instructions behind it 126465SN/A SerializeHandled, /// Serialization has been handled 127465SN/A NumStatus 1287532Ssteve.reinhardt@amd.com }; 1297532Ssteve.reinhardt@amd.com 1307532Ssteve.reinhardt@amd.com enum Flags { 1317532Ssteve.reinhardt@amd.com NotAnInst, 1327532Ssteve.reinhardt@amd.com TranslationStarted, 1337532Ssteve.reinhardt@amd.com TranslationCompleted, 1347532Ssteve.reinhardt@amd.com PossibleLoadViolation, 1357532Ssteve.reinhardt@amd.com HitExternalSnoop, 1369196SAndreas.Sandberg@arm.com EffAddrValid, 1379196SAndreas.Sandberg@arm.com RecordResult, 1387532Ssteve.reinhardt@amd.com Predicate, 13910905Sandreas.sandberg@arm.com PredTaken, 1407532Ssteve.reinhardt@amd.com IsStrictlyOrdered, 1417532Ssteve.reinhardt@amd.com ReqMade, 1427532Ssteve.reinhardt@amd.com MemOpDone, 1437532Ssteve.reinhardt@amd.com MaxFlags 1447532Ssteve.reinhardt@amd.com }; 1457532Ssteve.reinhardt@amd.com 1467532Ssteve.reinhardt@amd.com public: 1477532Ssteve.reinhardt@amd.com /** The sequence number of the instruction. */ 1489196SAndreas.Sandberg@arm.com InstSeqNum seqNum; 1499196SAndreas.Sandberg@arm.com 1509196SAndreas.Sandberg@arm.com /** The StaticInst used by this BaseDynInst. */ 1512SN/A const StaticInstPtr staticInst; 1529196SAndreas.Sandberg@arm.com 1539196SAndreas.Sandberg@arm.com /** Pointer to the Impl's CPU object. */ 1549196SAndreas.Sandberg@arm.com ImplCPU *cpu; 1559196SAndreas.Sandberg@arm.com 156330SN/A BaseCPU *getCpuPtr() { return cpu; } 1572SN/A 1587532Ssteve.reinhardt@amd.com /** Pointer to the thread state. */ 15910023Smatt.horsnell@ARM.com ImplState *thread; 16010023Smatt.horsnell@ARM.com 16110023Smatt.horsnell@ARM.com /** The kind of fault this instruction has generated. */ 16210023Smatt.horsnell@ARM.com Fault fault; 16310023Smatt.horsnell@ARM.com 16410023Smatt.horsnell@ARM.com /** InstRecord that tracks this instructions. */ 16510023Smatt.horsnell@ARM.com Trace::InstRecord *traceData; 16610023Smatt.horsnell@ARM.com 16710023Smatt.horsnell@ARM.com protected: 16810023Smatt.horsnell@ARM.com /** The result of the instruction; assumes an instruction can have many 16910023Smatt.horsnell@ARM.com * destination registers. 17010023Smatt.horsnell@ARM.com */ 17110023Smatt.horsnell@ARM.com std::queue<InstResult> instResult; 17210023Smatt.horsnell@ARM.com 17310023Smatt.horsnell@ARM.com /** PC state for this instruction. */ 17413781Sgabeblack@google.com TheISA::PCState pc; 17513781Sgabeblack@google.com 17613781Sgabeblack@google.com /* An amalgamation of a lot of boolean values into one */ 17713781Sgabeblack@google.com std::bitset<MaxFlags> instFlags; 17813781Sgabeblack@google.com 17913781Sgabeblack@google.com /** The status of this BaseDynInst. Several bits can be set. */ 18013781Sgabeblack@google.com std::bitset<NumStatus> status; 18113781Sgabeblack@google.com 18213781Sgabeblack@google.com /** Whether or not the source register is ready. 18313781Sgabeblack@google.com * @todo: Not sure this should be here vs the derived class. 18413781Sgabeblack@google.com */ 18513781Sgabeblack@google.com std::bitset<MaxInstSrcRegs> _readySrcRegIdx; 1867532Ssteve.reinhardt@amd.com 1877532Ssteve.reinhardt@amd.com public: 1887823Ssteve.reinhardt@amd.com /** The thread this instruction is from. */ 1897532Ssteve.reinhardt@amd.com ThreadID threadNumber; 1907532Ssteve.reinhardt@amd.com 1917492Ssteve.reinhardt@amd.com /** Iterator pointing to this BaseDynInst in the list of all insts. */ 192330SN/A ListIt instListIt; 1939196SAndreas.Sandberg@arm.com 19410913Sandreas.sandberg@arm.com ////////////////////// Branch Data /////////////// 19510913Sandreas.sandberg@arm.com /** Predicted PC state after this instruction. */ 1969342SAndreas.Sandberg@arm.com TheISA::PCState predPC; 19711168Sandreas.hansson@arm.com 1989342SAndreas.Sandberg@arm.com /** The Macroop if one exists */ 19910911Sandreas.sandberg@arm.com const StaticInstPtr macroop; 20010911Sandreas.sandberg@arm.com 20110911Sandreas.sandberg@arm.com /** How many source registers are ready. */ 20210911Sandreas.sandberg@arm.com uint8_t readyRegs; 20310911Sandreas.sandberg@arm.com 20410911Sandreas.sandberg@arm.com public: 20510911Sandreas.sandberg@arm.com /////////////////////// Load Store Data ////////////////////// 20610911Sandreas.sandberg@arm.com /** The effective virtual address (lds & stores only). */ 20710911Sandreas.sandberg@arm.com Addr effAddr; 20810911Sandreas.sandberg@arm.com 20910911Sandreas.sandberg@arm.com /** The effective physical address. */ 21010911Sandreas.sandberg@arm.com Addr physEffAddr; 21110911Sandreas.sandberg@arm.com 21210911Sandreas.sandberg@arm.com /** The memory request flags (from translation). */ 21310911Sandreas.sandberg@arm.com unsigned memReqFlags; 21410911Sandreas.sandberg@arm.com 21510911Sandreas.sandberg@arm.com /** data address space ID, for loads & stores. */ 21610911Sandreas.sandberg@arm.com short asid; 21710911Sandreas.sandberg@arm.com 21810911Sandreas.sandberg@arm.com /** The size of the request */ 21910911Sandreas.sandberg@arm.com uint8_t effSize; 22010911Sandreas.sandberg@arm.com 22110905Sandreas.sandberg@arm.com /** Pointer to the data for the memory access. */ 22211168Sandreas.hansson@arm.com uint8_t *memData; 22311168Sandreas.hansson@arm.com 22410905Sandreas.sandberg@arm.com /** Load queue index. */ 2259342SAndreas.Sandberg@arm.com int16_t lqIdx; 2269196SAndreas.Sandberg@arm.com LQIterator lqIt; 2279196SAndreas.Sandberg@arm.com 22810905Sandreas.sandberg@arm.com /** Store queue index. */ 229938SN/A int16_t sqIdx; 2301031SN/A SQIterator sqIt; 2311031SN/A 2321031SN/A 2331031SN/A /////////////////////// TLB Miss ////////////////////// 2341031SN/A /** 2351031SN/A * Saved memory request (needed when the DTB address translation is 2365314Sstever@gmail.com * delayed due to a hw page table walk). 2375314Sstever@gmail.com */ 2385315Sstever@gmail.com LSQRequestPtr savedReq; 2395314Sstever@gmail.com 2405314Sstever@gmail.com /////////////////////// Checker ////////////////////// 2415314Sstever@gmail.com // Need a copy of main request pointer to verify on writes. 2422SN/A RequestPtr reqToVerify; 2432SN/A 24411067Sandreas.sandberg@arm.com protected: 24511067Sandreas.sandberg@arm.com /** Flattened register index of the destination registers of this 24611067Sandreas.sandberg@arm.com * instruction. 24711067Sandreas.sandberg@arm.com */ 24811067Sandreas.sandberg@arm.com std::array<RegId, TheISA::MaxInstDestRegs> _flatDestRegIdx; 24911067Sandreas.sandberg@arm.com 25011067Sandreas.sandberg@arm.com /** Physical register index of the destination registers of this 25111067Sandreas.sandberg@arm.com * instruction. 25211067Sandreas.sandberg@arm.com */ 25311067Sandreas.sandberg@arm.com std::array<PhysRegIdPtr, TheISA::MaxInstDestRegs> _destRegIdx; 25411067Sandreas.sandberg@arm.com 25511067Sandreas.sandberg@arm.com /** Physical register index of the source registers of this 25611067Sandreas.sandberg@arm.com * instruction. 25711067Sandreas.sandberg@arm.com */ 25811067Sandreas.sandberg@arm.com std::array<PhysRegIdPtr, TheISA::MaxInstSrcRegs> _srcRegIdx; 2599554Sandreas.hansson@arm.com 2609554Sandreas.hansson@arm.com /** Physical register index of the previous producers of the 2619554Sandreas.hansson@arm.com * architected destinations. 2629554Sandreas.hansson@arm.com */ 2632SN/A std::array<PhysRegIdPtr, TheISA::MaxInstDestRegs> _prevDestRegIdx; 264 265 266 public: 267 /** Records changes to result? */ 268 void recordResult(bool f) { instFlags[RecordResult] = f; } 269 270 /** Is the effective virtual address valid. */ 271 bool effAddrValid() const { return instFlags[EffAddrValid]; } 272 void effAddrValid(bool b) { instFlags[EffAddrValid] = b; } 273 274 /** Whether or not the memory operation is done. */ 275 bool memOpDone() const { return instFlags[MemOpDone]; } 276 void memOpDone(bool f) { instFlags[MemOpDone] = f; } 277 278 bool notAnInst() const { return instFlags[NotAnInst]; } 279 void setNotAnInst() { instFlags[NotAnInst] = true; } 280 281 282 //////////////////////////////////////////// 283 // 284 // INSTRUCTION EXECUTION 285 // 286 //////////////////////////////////////////// 287 288 void demapPage(Addr vaddr, uint64_t asn) 289 { 290 cpu->demapPage(vaddr, asn); 291 } 292 void demapInstPage(Addr vaddr, uint64_t asn) 293 { 294 cpu->demapPage(vaddr, asn); 295 } 296 void demapDataPage(Addr vaddr, uint64_t asn) 297 { 298 cpu->demapPage(vaddr, asn); 299 } 300 301 Fault initiateMemRead(Addr addr, unsigned size, Request::Flags flags); 302 303 Fault writeMem(uint8_t *data, unsigned size, Addr addr, 304 Request::Flags flags, uint64_t *res); 305 306 Fault initiateMemAMO(Addr addr, unsigned size, Request::Flags flags, 307 AtomicOpFunctor *amo_op); 308 309 /** True if the DTB address translation has started. */ 310 bool translationStarted() const { return instFlags[TranslationStarted]; } 311 void translationStarted(bool f) { instFlags[TranslationStarted] = f; } 312 313 /** True if the DTB address translation has completed. */ 314 bool translationCompleted() const { return instFlags[TranslationCompleted]; } 315 void translationCompleted(bool f) { instFlags[TranslationCompleted] = f; } 316 317 /** True if this address was found to match a previous load and they issued 318 * out of order. If that happend, then it's only a problem if an incoming 319 * snoop invalidate modifies the line, in which case we need to squash. 320 * If nothing modified the line the order doesn't matter. 321 */ 322 bool possibleLoadViolation() const { return instFlags[PossibleLoadViolation]; } 323 void possibleLoadViolation(bool f) { instFlags[PossibleLoadViolation] = f; } 324 325 /** True if the address hit a external snoop while sitting in the LSQ. 326 * If this is true and a older instruction sees it, this instruction must 327 * reexecute 328 */ 329 bool hitExternalSnoop() const { return instFlags[HitExternalSnoop]; } 330 void hitExternalSnoop(bool f) { instFlags[HitExternalSnoop] = f; } 331 332 /** 333 * Returns true if the DTB address translation is being delayed due to a hw 334 * page table walk. 335 */ 336 bool isTranslationDelayed() const 337 { 338 return (translationStarted() && !translationCompleted()); 339 } 340 341 public: 342#ifdef DEBUG 343 void dumpSNList(); 344#endif 345 346 /** Returns the physical register index of the i'th destination 347 * register. 348 */ 349 PhysRegIdPtr renamedDestRegIdx(int idx) const 350 { 351 return _destRegIdx[idx]; 352 } 353 354 /** Returns the physical register index of the i'th source register. */ 355 PhysRegIdPtr renamedSrcRegIdx(int idx) const 356 { 357 assert(TheISA::MaxInstSrcRegs > idx); 358 return _srcRegIdx[idx]; 359 } 360 361 /** Returns the flattened register index of the i'th destination 362 * register. 363 */ 364 const RegId& flattenedDestRegIdx(int idx) const 365 { 366 return _flatDestRegIdx[idx]; 367 } 368 369 /** Returns the physical register index of the previous physical register 370 * that remapped to the same logical register index. 371 */ 372 PhysRegIdPtr prevDestRegIdx(int idx) const 373 { 374 return _prevDestRegIdx[idx]; 375 } 376 377 /** Renames a destination register to a physical register. Also records 378 * the previous physical register that the logical register mapped to. 379 */ 380 void renameDestReg(int idx, 381 PhysRegIdPtr renamed_dest, 382 PhysRegIdPtr previous_rename) 383 { 384 _destRegIdx[idx] = renamed_dest; 385 _prevDestRegIdx[idx] = previous_rename; 386 } 387 388 /** Renames a source logical register to the physical register which 389 * has/will produce that logical register's result. 390 * @todo: add in whether or not the source register is ready. 391 */ 392 void renameSrcReg(int idx, PhysRegIdPtr renamed_src) 393 { 394 _srcRegIdx[idx] = renamed_src; 395 } 396 397 /** Flattens a destination architectural register index into a logical 398 * index. 399 */ 400 void flattenDestReg(int idx, const RegId& flattened_dest) 401 { 402 _flatDestRegIdx[idx] = flattened_dest; 403 } 404 /** BaseDynInst constructor given a binary instruction. 405 * @param staticInst A StaticInstPtr to the underlying instruction. 406 * @param pc The PC state for the instruction. 407 * @param predPC The predicted next PC state for the instruction. 408 * @param seq_num The sequence number of the instruction. 409 * @param cpu Pointer to the instruction's CPU. 410 */ 411 BaseDynInst(const StaticInstPtr &staticInst, const StaticInstPtr ¯oop, 412 TheISA::PCState pc, TheISA::PCState predPC, 413 InstSeqNum seq_num, ImplCPU *cpu); 414 415 /** BaseDynInst constructor given a StaticInst pointer. 416 * @param _staticInst The StaticInst for this BaseDynInst. 417 */ 418 BaseDynInst(const StaticInstPtr &staticInst, const StaticInstPtr ¯oop); 419 420 /** BaseDynInst destructor. */ 421 ~BaseDynInst(); 422 423 private: 424 /** Function to initialize variables in the constructors. */ 425 void initVars(); 426 427 public: 428 /** Dumps out contents of this BaseDynInst. */ 429 void dump(); 430 431 /** Dumps out contents of this BaseDynInst into given string. */ 432 void dump(std::string &outstring); 433 434 /** Read this CPU's ID. */ 435 int cpuId() const { return cpu->cpuId(); } 436 437 /** Read this CPU's Socket ID. */ 438 uint32_t socketId() const { return cpu->socketId(); } 439 440 /** Read this CPU's data requestor ID */ 441 MasterID masterId() const { return cpu->dataMasterId(); } 442 443 /** Read this context's system-wide ID **/ 444 ContextID contextId() const { return thread->contextId(); } 445 446 /** Returns the fault type. */ 447 Fault getFault() const { return fault; } 448 /** TODO: This I added for the LSQRequest side to be able to modify the 449 * fault. There should be a better mechanism in place. */ 450 Fault& getFault() { return fault; } 451 452 /** Checks whether or not this instruction has had its branch target 453 * calculated yet. For now it is not utilized and is hacked to be 454 * always false. 455 * @todo: Actually use this instruction. 456 */ 457 bool doneTargCalc() { return false; } 458 459 /** Set the predicted target of this current instruction. */ 460 void setPredTarg(const TheISA::PCState &_predPC) 461 { 462 predPC = _predPC; 463 } 464 465 const TheISA::PCState &readPredTarg() { return predPC; } 466 467 /** Returns the predicted PC immediately after the branch. */ 468 Addr predInstAddr() { return predPC.instAddr(); } 469 470 /** Returns the predicted PC two instructions after the branch */ 471 Addr predNextInstAddr() { return predPC.nextInstAddr(); } 472 473 /** Returns the predicted micro PC after the branch */ 474 Addr predMicroPC() { return predPC.microPC(); } 475 476 /** Returns whether the instruction was predicted taken or not. */ 477 bool readPredTaken() 478 { 479 return instFlags[PredTaken]; 480 } 481 482 void setPredTaken(bool predicted_taken) 483 { 484 instFlags[PredTaken] = predicted_taken; 485 } 486 487 /** Returns whether the instruction mispredicted. */ 488 bool mispredicted() 489 { 490 TheISA::PCState tempPC = pc; 491 TheISA::advancePC(tempPC, staticInst); 492 return !(tempPC == predPC); 493 } 494 495 // 496 // Instruction types. Forward checks to StaticInst object. 497 // 498 bool isNop() const { return staticInst->isNop(); } 499 bool isMemRef() const { return staticInst->isMemRef(); } 500 bool isLoad() const { return staticInst->isLoad(); } 501 bool isStore() const { return staticInst->isStore(); } 502 bool isAtomic() const { return staticInst->isAtomic(); } 503 bool isStoreConditional() const 504 { return staticInst->isStoreConditional(); } 505 bool isInstPrefetch() const { return staticInst->isInstPrefetch(); } 506 bool isDataPrefetch() const { return staticInst->isDataPrefetch(); } 507 bool isInteger() const { return staticInst->isInteger(); } 508 bool isFloating() const { return staticInst->isFloating(); } 509 bool isVector() const { return staticInst->isVector(); } 510 bool isControl() const { return staticInst->isControl(); } 511 bool isCall() const { return staticInst->isCall(); } 512 bool isReturn() const { return staticInst->isReturn(); } 513 bool isDirectCtrl() const { return staticInst->isDirectCtrl(); } 514 bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); } 515 bool isCondCtrl() const { return staticInst->isCondCtrl(); } 516 bool isUncondCtrl() const { return staticInst->isUncondCtrl(); } 517 bool isCondDelaySlot() const { return staticInst->isCondDelaySlot(); } 518 bool isThreadSync() const { return staticInst->isThreadSync(); } 519 bool isSerializing() const { return staticInst->isSerializing(); } 520 bool isSerializeBefore() const 521 { return staticInst->isSerializeBefore() || status[SerializeBefore]; } 522 bool isSerializeAfter() const 523 { return staticInst->isSerializeAfter() || status[SerializeAfter]; } 524 bool isSquashAfter() const { return staticInst->isSquashAfter(); } 525 bool isMemBarrier() const { return staticInst->isMemBarrier(); } 526 bool isWriteBarrier() const { return staticInst->isWriteBarrier(); } 527 bool isNonSpeculative() const { return staticInst->isNonSpeculative(); } 528 bool isQuiesce() const { return staticInst->isQuiesce(); } 529 bool isIprAccess() const { return staticInst->isIprAccess(); } 530 bool isUnverifiable() const { return staticInst->isUnverifiable(); } 531 bool isSyscall() const { return staticInst->isSyscall(); } 532 bool isMacroop() const { return staticInst->isMacroop(); } 533 bool isMicroop() const { return staticInst->isMicroop(); } 534 bool isDelayedCommit() const { return staticInst->isDelayedCommit(); } 535 bool isLastMicroop() const { return staticInst->isLastMicroop(); } 536 bool isFirstMicroop() const { return staticInst->isFirstMicroop(); } 537 bool isMicroBranch() const { return staticInst->isMicroBranch(); } 538 539 /** Temporarily sets this instruction as a serialize before instruction. */ 540 void setSerializeBefore() { status.set(SerializeBefore); } 541 542 /** Clears the serializeBefore part of this instruction. */ 543 void clearSerializeBefore() { status.reset(SerializeBefore); } 544 545 /** Checks if this serializeBefore is only temporarily set. */ 546 bool isTempSerializeBefore() { return status[SerializeBefore]; } 547 548 /** Temporarily sets this instruction as a serialize after instruction. */ 549 void setSerializeAfter() { status.set(SerializeAfter); } 550 551 /** Clears the serializeAfter part of this instruction.*/ 552 void clearSerializeAfter() { status.reset(SerializeAfter); } 553 554 /** Checks if this serializeAfter is only temporarily set. */ 555 bool isTempSerializeAfter() { return status[SerializeAfter]; } 556 557 /** Sets the serialization part of this instruction as handled. */ 558 void setSerializeHandled() { status.set(SerializeHandled); } 559 560 /** Checks if the serialization part of this instruction has been 561 * handled. This does not apply to the temporary serializing 562 * state; it only applies to this instruction's own permanent 563 * serializing state. 564 */ 565 bool isSerializeHandled() { return status[SerializeHandled]; } 566 567 /** Returns the opclass of this instruction. */ 568 OpClass opClass() const { return staticInst->opClass(); } 569 570 /** Returns the branch target address. */ 571 TheISA::PCState branchTarget() const 572 { return staticInst->branchTarget(pc); } 573 574 /** Returns the number of source registers. */ 575 int8_t numSrcRegs() const { return staticInst->numSrcRegs(); } 576 577 /** Returns the number of destination registers. */ 578 int8_t numDestRegs() const { return staticInst->numDestRegs(); } 579 580 // the following are used to track physical register usage 581 // for machines with separate int & FP reg files 582 int8_t numFPDestRegs() const { return staticInst->numFPDestRegs(); } 583 int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); } 584 int8_t numCCDestRegs() const { return staticInst->numCCDestRegs(); } 585 int8_t numVecDestRegs() const { return staticInst->numVecDestRegs(); } 586 int8_t numVecElemDestRegs() const 587 { 588 return staticInst->numVecElemDestRegs(); 589 } 590 int8_t 591 numVecPredDestRegs() const 592 { 593 return staticInst->numVecPredDestRegs(); 594 } 595 596 /** Returns the logical register index of the i'th destination register. */ 597 const RegId& destRegIdx(int i) const { return staticInst->destRegIdx(i); } 598 599 /** Returns the logical register index of the i'th source register. */ 600 const RegId& srcRegIdx(int i) const { return staticInst->srcRegIdx(i); } 601 602 /** Return the size of the instResult queue. */ 603 uint8_t resultSize() { return instResult.size(); } 604 605 /** Pops a result off the instResult queue. 606 * If the result stack is empty, return the default value. 607 * */ 608 InstResult popResult(InstResult dflt = InstResult()) 609 { 610 if (!instResult.empty()) { 611 InstResult t = instResult.front(); 612 instResult.pop(); 613 return t; 614 } 615 return dflt; 616 } 617 618 /** Pushes a result onto the instResult queue. */ 619 /** @{ */ 620 /** Scalar result. */ 621 template<typename T> 622 void setScalarResult(T&& t) 623 { 624 if (instFlags[RecordResult]) { 625 instResult.push(InstResult(std::forward<T>(t), 626 InstResult::ResultType::Scalar)); 627 } 628 } 629 630 /** Full vector result. */ 631 template<typename T> 632 void setVecResult(T&& t) 633 { 634 if (instFlags[RecordResult]) { 635 instResult.push(InstResult(std::forward<T>(t), 636 InstResult::ResultType::VecReg)); 637 } 638 } 639 640 /** Vector element result. */ 641 template<typename T> 642 void setVecElemResult(T&& t) 643 { 644 if (instFlags[RecordResult]) { 645 instResult.push(InstResult(std::forward<T>(t), 646 InstResult::ResultType::VecElem)); 647 } 648 } 649 650 /** Predicate result. */ 651 template<typename T> 652 void setVecPredResult(T&& t) 653 { 654 if (instFlags[RecordResult]) { 655 instResult.push(InstResult(std::forward<T>(t), 656 InstResult::ResultType::VecPredReg)); 657 } 658 } 659 /** @} */ 660 661 /** Records an integer register being set to a value. */ 662 void setIntRegOperand(const StaticInst *si, int idx, RegVal val) 663 { 664 setScalarResult(val); 665 } 666 667 /** Records a CC register being set to a value. */ 668 void setCCRegOperand(const StaticInst *si, int idx, RegVal val) 669 { 670 setScalarResult(val); 671 } 672 673 /** Record a vector register being set to a value */ 674 void setVecRegOperand(const StaticInst *si, int idx, 675 const VecRegContainer& val) 676 { 677 setVecResult(val); 678 } 679 680 /** Records an fp register being set to an integer value. */ 681 void 682 setFloatRegOperandBits(const StaticInst *si, int idx, RegVal val) 683 { 684 setScalarResult(val); 685 } 686 687 /** Record a vector register being set to a value */ 688 void setVecElemOperand(const StaticInst *si, int idx, const VecElem val) 689 { 690 setVecElemResult(val); 691 } 692 693 /** Record a vector register being set to a value */ 694 void setVecPredRegOperand(const StaticInst *si, int idx, 695 const VecPredRegContainer& val) 696 { 697 setVecPredResult(val); 698 } 699 700 /** Records that one of the source registers is ready. */ 701 void markSrcRegReady(); 702 703 /** Marks a specific register as ready. */ 704 void markSrcRegReady(RegIndex src_idx); 705 706 /** Returns if a source register is ready. */ 707 bool isReadySrcRegIdx(int idx) const 708 { 709 return this->_readySrcRegIdx[idx]; 710 } 711 712 /** Sets this instruction as completed. */ 713 void setCompleted() { status.set(Completed); } 714 715 /** Returns whether or not this instruction is completed. */ 716 bool isCompleted() const { return status[Completed]; } 717 718 /** Marks the result as ready. */ 719 void setResultReady() { status.set(ResultReady); } 720 721 /** Returns whether or not the result is ready. */ 722 bool isResultReady() const { return status[ResultReady]; } 723 724 /** Sets this instruction as ready to issue. */ 725 void setCanIssue() { status.set(CanIssue); } 726 727 /** Returns whether or not this instruction is ready to issue. */ 728 bool readyToIssue() const { return status[CanIssue]; } 729 730 /** Clears this instruction being able to issue. */ 731 void clearCanIssue() { status.reset(CanIssue); } 732 733 /** Sets this instruction as issued from the IQ. */ 734 void setIssued() { status.set(Issued); } 735 736 /** Returns whether or not this instruction has issued. */ 737 bool isIssued() const { return status[Issued]; } 738 739 /** Clears this instruction as being issued. */ 740 void clearIssued() { status.reset(Issued); } 741 742 /** Sets this instruction as executed. */ 743 void setExecuted() { status.set(Executed); } 744 745 /** Returns whether or not this instruction has executed. */ 746 bool isExecuted() const { return status[Executed]; } 747 748 /** Sets this instruction as ready to commit. */ 749 void setCanCommit() { status.set(CanCommit); } 750 751 /** Clears this instruction as being ready to commit. */ 752 void clearCanCommit() { status.reset(CanCommit); } 753 754 /** Returns whether or not this instruction is ready to commit. */ 755 bool readyToCommit() const { return status[CanCommit]; } 756 757 void setAtCommit() { status.set(AtCommit); } 758 759 bool isAtCommit() { return status[AtCommit]; } 760 761 /** Sets this instruction as committed. */ 762 void setCommitted() { status.set(Committed); } 763 764 /** Returns whether or not this instruction is committed. */ 765 bool isCommitted() const { return status[Committed]; } 766 767 /** Sets this instruction as squashed. */ 768 void setSquashed() { status.set(Squashed); } 769 770 /** Returns whether or not this instruction is squashed. */ 771 bool isSquashed() const { return status[Squashed]; } 772 773 //Instruction Queue Entry 774 //----------------------- 775 /** Sets this instruction as a entry the IQ. */ 776 void setInIQ() { status.set(IqEntry); } 777 778 /** Sets this instruction as a entry the IQ. */ 779 void clearInIQ() { status.reset(IqEntry); } 780 781 /** Returns whether or not this instruction has issued. */ 782 bool isInIQ() const { return status[IqEntry]; } 783 784 /** Sets this instruction as squashed in the IQ. */ 785 void setSquashedInIQ() { status.set(SquashedInIQ); status.set(Squashed);} 786 787 /** Returns whether or not this instruction is squashed in the IQ. */ 788 bool isSquashedInIQ() const { return status[SquashedInIQ]; } 789 790 791 //Load / Store Queue Functions 792 //----------------------- 793 /** Sets this instruction as a entry the LSQ. */ 794 void setInLSQ() { status.set(LsqEntry); } 795 796 /** Sets this instruction as a entry the LSQ. */ 797 void removeInLSQ() { status.reset(LsqEntry); } 798 799 /** Returns whether or not this instruction is in the LSQ. */ 800 bool isInLSQ() const { return status[LsqEntry]; } 801 802 /** Sets this instruction as squashed in the LSQ. */ 803 void setSquashedInLSQ() { status.set(SquashedInLSQ);} 804 805 /** Returns whether or not this instruction is squashed in the LSQ. */ 806 bool isSquashedInLSQ() const { return status[SquashedInLSQ]; } 807 808 809 //Reorder Buffer Functions 810 //----------------------- 811 /** Sets this instruction as a entry the ROB. */ 812 void setInROB() { status.set(RobEntry); } 813 814 /** Sets this instruction as a entry the ROB. */ 815 void clearInROB() { status.reset(RobEntry); } 816 817 /** Returns whether or not this instruction is in the ROB. */ 818 bool isInROB() const { return status[RobEntry]; } 819 820 /** Sets this instruction as squashed in the ROB. */ 821 void setSquashedInROB() { status.set(SquashedInROB); } 822 823 /** Returns whether or not this instruction is squashed in the ROB. */ 824 bool isSquashedInROB() const { return status[SquashedInROB]; } 825 826 /** Read the PC state of this instruction. */ 827 TheISA::PCState pcState() const { return pc; } 828 829 /** Set the PC state of this instruction. */ 830 void pcState(const TheISA::PCState &val) { pc = val; } 831 832 /** Read the PC of this instruction. */ 833 Addr instAddr() const { return pc.instAddr(); } 834 835 /** Read the PC of the next instruction. */ 836 Addr nextInstAddr() const { return pc.nextInstAddr(); } 837 838 /**Read the micro PC of this instruction. */ 839 Addr microPC() const { return pc.microPC(); } 840 841 bool readPredicate() const 842 { 843 return instFlags[Predicate]; 844 } 845 846 void setPredicate(bool val) 847 { 848 instFlags[Predicate] = val; 849 850 if (traceData) { 851 traceData->setPredicate(val); 852 } 853 } 854 855 /** Sets the ASID. */ 856 void setASID(short addr_space_id) { asid = addr_space_id; } 857 short getASID() { return asid; } 858 859 /** Sets the thread id. */ 860 void setTid(ThreadID tid) { threadNumber = tid; } 861 862 /** Sets the pointer to the thread state. */ 863 void setThreadState(ImplState *state) { thread = state; } 864 865 /** Returns the thread context. */ 866 ThreadContext *tcBase() { return thread->getTC(); } 867 868 public: 869 /** Returns whether or not the eff. addr. source registers are ready. */ 870 bool eaSrcsReady() const; 871 872 /** Is this instruction's memory access strictly ordered? */ 873 bool strictlyOrdered() const { return instFlags[IsStrictlyOrdered]; } 874 void strictlyOrdered(bool so) { instFlags[IsStrictlyOrdered] = so; } 875 876 /** Has this instruction generated a memory request. */ 877 bool hasRequest() const { return instFlags[ReqMade]; } 878 /** Assert this instruction has generated a memory request. */ 879 void setRequest() { instFlags[ReqMade] = true; } 880 881 /** Returns iterator to this instruction in the list of all insts. */ 882 ListIt &getInstListIt() { return instListIt; } 883 884 /** Sets iterator for this instruction in the list of all insts. */ 885 void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; } 886 887 public: 888 /** Returns the number of consecutive store conditional failures. */ 889 unsigned int readStCondFailures() const 890 { return thread->storeCondFailures; } 891 892 /** Sets the number of consecutive store conditional failures. */ 893 void setStCondFailures(unsigned int sc_failures) 894 { thread->storeCondFailures = sc_failures; } 895 896 public: 897 // monitor/mwait funtions 898 void armMonitor(Addr address) { cpu->armMonitor(threadNumber, address); } 899 bool mwait(PacketPtr pkt) { return cpu->mwait(threadNumber, pkt); } 900 void mwaitAtomic(ThreadContext *tc) 901 { return cpu->mwaitAtomic(threadNumber, tc, cpu->dtb); } 902 AddressMonitor *getAddrMonitor() 903 { return cpu->getCpuAddrMonitor(threadNumber); } 904}; 905 906template<class Impl> 907Fault 908BaseDynInst<Impl>::initiateMemRead(Addr addr, unsigned size, 909 Request::Flags flags) 910{ 911 return cpu->pushRequest( 912 dynamic_cast<typename DynInstPtr::PtrType>(this), 913 /* ld */ true, nullptr, size, addr, flags, nullptr); 914} 915 916template<class Impl> 917Fault 918BaseDynInst<Impl>::writeMem(uint8_t *data, unsigned size, Addr addr, 919 Request::Flags flags, uint64_t *res) 920{ 921 return cpu->pushRequest( 922 dynamic_cast<typename DynInstPtr::PtrType>(this), 923 /* st */ false, data, size, addr, flags, res); 924} 925 926template<class Impl> 927Fault 928BaseDynInst<Impl>::initiateMemAMO(Addr addr, unsigned size, 929 Request::Flags flags, 930 AtomicOpFunctor *amo_op) 931{ 932 // atomic memory instructions do not have data to be written to memory yet 933 // since the atomic operations will be executed directly in cache/memory. 934 // Therefore, its `data` field is nullptr. 935 // Atomic memory requests need to carry their `amo_op` fields to cache/ 936 // memory 937 return cpu->pushRequest( 938 dynamic_cast<typename DynInstPtr::PtrType>(this), 939 /* atomic */ false, nullptr, size, addr, flags, nullptr, amo_op); 940} 941 942#endif // __CPU_BASE_DYN_INST_HH__ 943