base_dyn_inst.hh revision 13590:d7e018859709 
1/*
2 * Copyright (c) 2011, 2013, 2016-2018 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder.  You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2004-2006 The Regents of The University of Michigan
16 * Copyright (c) 2009 The University of Edinburgh
17 * All rights reserved.
18 *
19 * Redistribution and use in source and binary forms, with or without
20 * modification, are permitted provided that the following conditions are
21 * met: redistributions of source code must retain the above copyright
22 * notice, this list of conditions and the following disclaimer;
23 * redistributions in binary form must reproduce the above copyright
24 * notice, this list of conditions and the following disclaimer in the
25 * documentation and/or other materials provided with the distribution;
26 * neither the name of the copyright holders nor the names of its
27 * contributors may be used to endorse or promote products derived from
28 * this software without specific prior written permission.
29 *
30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
34 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
35 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
36 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
37 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
38 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
39 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
40 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41 *
42 * Authors: Kevin Lim
43 *          Timothy M. Jones
44 */
45
46#ifndef __CPU_BASE_DYN_INST_HH__
47#define __CPU_BASE_DYN_INST_HH__
48
49#include <array>
50#include <bitset>
51#include <deque>
52#include <list>
53#include <string>
54
55#include "arch/generic/tlb.hh"
56#include "arch/utility.hh"
57#include "base/trace.hh"
58#include "config/the_isa.hh"
59#include "cpu/checker/cpu.hh"
60#include "cpu/exec_context.hh"
61#include "cpu/exetrace.hh"
62#include "cpu/inst_res.hh"
63#include "cpu/inst_seq.hh"
64#include "cpu/o3/comm.hh"
65#include "cpu/op_class.hh"
66#include "cpu/static_inst.hh"
67#include "cpu/translation.hh"
68#include "mem/packet.hh"
69#include "mem/request.hh"
70#include "sim/byteswap.hh"
71#include "sim/system.hh"
72
73/**
74 * @file
75 * Defines a dynamic instruction context.
76 */
77
78template <class Impl>
79class BaseDynInst : public ExecContext, public RefCounted
80{
81  public:
82    // Typedef for the CPU.
83    typedef typename Impl::CPUType ImplCPU;
84    typedef typename ImplCPU::ImplState ImplState;
85    using VecRegContainer = TheISA::VecRegContainer;
86
87    using LSQRequestPtr = typename Impl::CPUPol::LSQ::LSQRequest*;
88    using LQIterator = typename Impl::CPUPol::LSQUnit::LQIterator;
89    using SQIterator = typename Impl::CPUPol::LSQUnit::SQIterator;
90
91    // The DynInstPtr type.
92    typedef typename Impl::DynInstPtr DynInstPtr;
93    typedef RefCountingPtr<BaseDynInst<Impl> > BaseDynInstPtr;
94
95    // The list of instructions iterator type.
96    typedef typename std::list<DynInstPtr>::iterator ListIt;
97
98    enum {
99        MaxInstSrcRegs = TheISA::MaxInstSrcRegs,        /// Max source regs
100        MaxInstDestRegs = TheISA::MaxInstDestRegs       /// Max dest regs
101    };
102
103  protected:
104    enum Status {
105        IqEntry,                 /// Instruction is in the IQ
106        RobEntry,                /// Instruction is in the ROB
107        LsqEntry,                /// Instruction is in the LSQ
108        Completed,               /// Instruction has completed
109        ResultReady,             /// Instruction has its result
110        CanIssue,                /// Instruction can issue and execute
111        Issued,                  /// Instruction has issued
112        Executed,                /// Instruction has executed
113        CanCommit,               /// Instruction can commit
114        AtCommit,                /// Instruction has reached commit
115        Committed,               /// Instruction has committed
116        Squashed,                /// Instruction is squashed
117        SquashedInIQ,            /// Instruction is squashed in the IQ
118        SquashedInLSQ,           /// Instruction is squashed in the LSQ
119        SquashedInROB,           /// Instruction is squashed in the ROB
120        RecoverInst,             /// Is a recover instruction
121        BlockingInst,            /// Is a blocking instruction
122        ThreadsyncWait,          /// Is a thread synchronization instruction
123        SerializeBefore,         /// Needs to serialize on
124                                 /// instructions ahead of it
125        SerializeAfter,          /// Needs to serialize instructions behind it
126        SerializeHandled,        /// Serialization has been handled
127        NumStatus
128    };
129
130    enum Flags {
131        NotAnInst,
132        TranslationStarted,
133        TranslationCompleted,
134        PossibleLoadViolation,
135        HitExternalSnoop,
136        EffAddrValid,
137        RecordResult,
138        Predicate,
139        PredTaken,
140        IsStrictlyOrdered,
141        ReqMade,
142        MemOpDone,
143        MaxFlags
144    };
145
146  public:
147    /** The sequence number of the instruction. */
148    InstSeqNum seqNum;
149
150    /** The StaticInst used by this BaseDynInst. */
151    const StaticInstPtr staticInst;
152
153    /** Pointer to the Impl's CPU object. */
154    ImplCPU *cpu;
155
156    BaseCPU *getCpuPtr() { return cpu; }
157
158    /** Pointer to the thread state. */
159    ImplState *thread;
160
161    /** The kind of fault this instruction has generated. */
162    Fault fault;
163
164    /** InstRecord that tracks this instructions. */
165    Trace::InstRecord *traceData;
166
167  protected:
168    /** The result of the instruction; assumes an instruction can have many
169     *  destination registers.
170     */
171    std::queue<InstResult> instResult;
172
173    /** PC state for this instruction. */
174    TheISA::PCState pc;
175
176    /* An amalgamation of a lot of boolean values into one */
177    std::bitset<MaxFlags> instFlags;
178
179    /** The status of this BaseDynInst.  Several bits can be set. */
180    std::bitset<NumStatus> status;
181
182     /** Whether or not the source register is ready.
183     *  @todo: Not sure this should be here vs the derived class.
184     */
185    std::bitset<MaxInstSrcRegs> _readySrcRegIdx;
186
187  public:
188    /** The thread this instruction is from. */
189    ThreadID threadNumber;
190
191    /** Iterator pointing to this BaseDynInst in the list of all insts. */
192    ListIt instListIt;
193
194    ////////////////////// Branch Data ///////////////
195    /** Predicted PC state after this instruction. */
196    TheISA::PCState predPC;
197
198    /** The Macroop if one exists */
199    const StaticInstPtr macroop;
200
201    /** How many source registers are ready. */
202    uint8_t readyRegs;
203
204  public:
205    /////////////////////// Load Store Data //////////////////////
206    /** The effective virtual address (lds & stores only). */
207    Addr effAddr;
208
209    /** The effective physical address. */
210    Addr physEffAddr;
211
212    /** The memory request flags (from translation). */
213    unsigned memReqFlags;
214
215    /** data address space ID, for loads & stores. */
216    short asid;
217
218    /** The size of the request */
219    uint8_t effSize;
220
221    /** Pointer to the data for the memory access. */
222    uint8_t *memData;
223
224    /** Load queue index. */
225    int16_t lqIdx;
226    LQIterator lqIt;
227
228    /** Store queue index. */
229    int16_t sqIdx;
230    SQIterator sqIt;
231
232
233    /////////////////////// TLB Miss //////////////////////
234    /**
235     * Saved memory request (needed when the DTB address translation is
236     * delayed due to a hw page table walk).
237     */
238    LSQRequestPtr savedReq;
239
240    /////////////////////// Checker //////////////////////
241    // Need a copy of main request pointer to verify on writes.
242    RequestPtr reqToVerify;
243
244  protected:
245    /** Flattened register index of the destination registers of this
246     *  instruction.
247     */
248    std::array<RegId, TheISA::MaxInstDestRegs> _flatDestRegIdx;
249
250    /** Physical register index of the destination registers of this
251     *  instruction.
252     */
253    std::array<PhysRegIdPtr, TheISA::MaxInstDestRegs> _destRegIdx;
254
255    /** Physical register index of the source registers of this
256     *  instruction.
257     */
258    std::array<PhysRegIdPtr, TheISA::MaxInstSrcRegs> _srcRegIdx;
259
260    /** Physical register index of the previous producers of the
261     *  architected destinations.
262     */
263    std::array<PhysRegIdPtr, TheISA::MaxInstDestRegs> _prevDestRegIdx;
264
265
266  public:
267    /** Records changes to result? */
268    void recordResult(bool f) { instFlags[RecordResult] = f; }
269
270    /** Is the effective virtual address valid. */
271    bool effAddrValid() const { return instFlags[EffAddrValid]; }
272    void effAddrValid(bool b) { instFlags[EffAddrValid] = b; }
273
274    /** Whether or not the memory operation is done. */
275    bool memOpDone() const { return instFlags[MemOpDone]; }
276    void memOpDone(bool f) { instFlags[MemOpDone] = f; }
277
278    bool notAnInst() const { return instFlags[NotAnInst]; }
279    void setNotAnInst() { instFlags[NotAnInst] = true; }
280
281
282    ////////////////////////////////////////////
283    //
284    // INSTRUCTION EXECUTION
285    //
286    ////////////////////////////////////////////
287
288    void demapPage(Addr vaddr, uint64_t asn)
289    {
290        cpu->demapPage(vaddr, asn);
291    }
292    void demapInstPage(Addr vaddr, uint64_t asn)
293    {
294        cpu->demapPage(vaddr, asn);
295    }
296    void demapDataPage(Addr vaddr, uint64_t asn)
297    {
298        cpu->demapPage(vaddr, asn);
299    }
300
301    Fault initiateMemRead(Addr addr, unsigned size, Request::Flags flags);
302
303    Fault writeMem(uint8_t *data, unsigned size, Addr addr,
304                   Request::Flags flags, uint64_t *res);
305
306    /** True if the DTB address translation has started. */
307    bool translationStarted() const { return instFlags[TranslationStarted]; }
308    void translationStarted(bool f) { instFlags[TranslationStarted] = f; }
309
310    /** True if the DTB address translation has completed. */
311    bool translationCompleted() const { return instFlags[TranslationCompleted]; }
312    void translationCompleted(bool f) { instFlags[TranslationCompleted] = f; }
313
314    /** True if this address was found to match a previous load and they issued
315     * out of order. If that happend, then it's only a problem if an incoming
316     * snoop invalidate modifies the line, in which case we need to squash.
317     * If nothing modified the line the order doesn't matter.
318     */
319    bool possibleLoadViolation() const { return instFlags[PossibleLoadViolation]; }
320    void possibleLoadViolation(bool f) { instFlags[PossibleLoadViolation] = f; }
321
322    /** True if the address hit a external snoop while sitting in the LSQ.
323     * If this is true and a older instruction sees it, this instruction must
324     * reexecute
325     */
326    bool hitExternalSnoop() const { return instFlags[HitExternalSnoop]; }
327    void hitExternalSnoop(bool f) { instFlags[HitExternalSnoop] = f; }
328
329    /**
330     * Returns true if the DTB address translation is being delayed due to a hw
331     * page table walk.
332     */
333    bool isTranslationDelayed() const
334    {
335        return (translationStarted() && !translationCompleted());
336    }
337
338  public:
339#ifdef DEBUG
340    void dumpSNList();
341#endif
342
343    /** Returns the physical register index of the i'th destination
344     *  register.
345     */
346    PhysRegIdPtr renamedDestRegIdx(int idx) const
347    {
348        return _destRegIdx[idx];
349    }
350
351    /** Returns the physical register index of the i'th source register. */
352    PhysRegIdPtr renamedSrcRegIdx(int idx) const
353    {
354        assert(TheISA::MaxInstSrcRegs > idx);
355        return _srcRegIdx[idx];
356    }
357
358    /** Returns the flattened register index of the i'th destination
359     *  register.
360     */
361    const RegId& flattenedDestRegIdx(int idx) const
362    {
363        return _flatDestRegIdx[idx];
364    }
365
366    /** Returns the physical register index of the previous physical register
367     *  that remapped to the same logical register index.
368     */
369    PhysRegIdPtr prevDestRegIdx(int idx) const
370    {
371        return _prevDestRegIdx[idx];
372    }
373
374    /** Renames a destination register to a physical register.  Also records
375     *  the previous physical register that the logical register mapped to.
376     */
377    void renameDestReg(int idx,
378                       PhysRegIdPtr renamed_dest,
379                       PhysRegIdPtr previous_rename)
380    {
381        _destRegIdx[idx] = renamed_dest;
382        _prevDestRegIdx[idx] = previous_rename;
383    }
384
385    /** Renames a source logical register to the physical register which
386     *  has/will produce that logical register's result.
387     *  @todo: add in whether or not the source register is ready.
388     */
389    void renameSrcReg(int idx, PhysRegIdPtr renamed_src)
390    {
391        _srcRegIdx[idx] = renamed_src;
392    }
393
394    /** Flattens a destination architectural register index into a logical
395     * index.
396     */
397    void flattenDestReg(int idx, const RegId& flattened_dest)
398    {
399        _flatDestRegIdx[idx] = flattened_dest;
400    }
401    /** BaseDynInst constructor given a binary instruction.
402     *  @param staticInst A StaticInstPtr to the underlying instruction.
403     *  @param pc The PC state for the instruction.
404     *  @param predPC The predicted next PC state for the instruction.
405     *  @param seq_num The sequence number of the instruction.
406     *  @param cpu Pointer to the instruction's CPU.
407     */
408    BaseDynInst(const StaticInstPtr &staticInst, const StaticInstPtr &macroop,
409                TheISA::PCState pc, TheISA::PCState predPC,
410                InstSeqNum seq_num, ImplCPU *cpu);
411
412    /** BaseDynInst constructor given a StaticInst pointer.
413     *  @param _staticInst The StaticInst for this BaseDynInst.
414     */
415    BaseDynInst(const StaticInstPtr &staticInst, const StaticInstPtr &macroop);
416
417    /** BaseDynInst destructor. */
418    ~BaseDynInst();
419
420  private:
421    /** Function to initialize variables in the constructors. */
422    void initVars();
423
424  public:
425    /** Dumps out contents of this BaseDynInst. */
426    void dump();
427
428    /** Dumps out contents of this BaseDynInst into given string. */
429    void dump(std::string &outstring);
430
431    /** Read this CPU's ID. */
432    int cpuId() const { return cpu->cpuId(); }
433
434    /** Read this CPU's Socket ID. */
435    uint32_t socketId() const { return cpu->socketId(); }
436
437    /** Read this CPU's data requestor ID */
438    MasterID masterId() const { return cpu->dataMasterId(); }
439
440    /** Read this context's system-wide ID **/
441    ContextID contextId() const { return thread->contextId(); }
442
443    /** Returns the fault type. */
444    Fault getFault() const { return fault; }
445    /** TODO: This I added for the LSQRequest side to be able to modify the
446     * fault. There should be a better mechanism in place. */
447    Fault& getFault() { return fault; }
448
449    /** Checks whether or not this instruction has had its branch target
450     *  calculated yet.  For now it is not utilized and is hacked to be
451     *  always false.
452     *  @todo: Actually use this instruction.
453     */
454    bool doneTargCalc() { return false; }
455
456    /** Set the predicted target of this current instruction. */
457    void setPredTarg(const TheISA::PCState &_predPC)
458    {
459        predPC = _predPC;
460    }
461
462    const TheISA::PCState &readPredTarg() { return predPC; }
463
464    /** Returns the predicted PC immediately after the branch. */
465    Addr predInstAddr() { return predPC.instAddr(); }
466
467    /** Returns the predicted PC two instructions after the branch */
468    Addr predNextInstAddr() { return predPC.nextInstAddr(); }
469
470    /** Returns the predicted micro PC after the branch */
471    Addr predMicroPC() { return predPC.microPC(); }
472
473    /** Returns whether the instruction was predicted taken or not. */
474    bool readPredTaken()
475    {
476        return instFlags[PredTaken];
477    }
478
479    void setPredTaken(bool predicted_taken)
480    {
481        instFlags[PredTaken] = predicted_taken;
482    }
483
484    /** Returns whether the instruction mispredicted. */
485    bool mispredicted()
486    {
487        TheISA::PCState tempPC = pc;
488        TheISA::advancePC(tempPC, staticInst);
489        return !(tempPC == predPC);
490    }
491
492    //
493    //  Instruction types.  Forward checks to StaticInst object.
494    //
495    bool isNop()          const { return staticInst->isNop(); }
496    bool isMemRef()       const { return staticInst->isMemRef(); }
497    bool isLoad()         const { return staticInst->isLoad(); }
498    bool isStore()        const { return staticInst->isStore(); }
499    bool isAtomic()       const { return staticInst->isAtomic(); }
500    bool isStoreConditional() const
501    { return staticInst->isStoreConditional(); }
502    bool isInstPrefetch() const { return staticInst->isInstPrefetch(); }
503    bool isDataPrefetch() const { return staticInst->isDataPrefetch(); }
504    bool isInteger()      const { return staticInst->isInteger(); }
505    bool isFloating()     const { return staticInst->isFloating(); }
506    bool isVector()       const { return staticInst->isVector(); }
507    bool isControl()      const { return staticInst->isControl(); }
508    bool isCall()         const { return staticInst->isCall(); }
509    bool isReturn()       const { return staticInst->isReturn(); }
510    bool isDirectCtrl()   const { return staticInst->isDirectCtrl(); }
511    bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); }
512    bool isCondCtrl()     const { return staticInst->isCondCtrl(); }
513    bool isUncondCtrl()   const { return staticInst->isUncondCtrl(); }
514    bool isCondDelaySlot() const { return staticInst->isCondDelaySlot(); }
515    bool isThreadSync()   const { return staticInst->isThreadSync(); }
516    bool isSerializing()  const { return staticInst->isSerializing(); }
517    bool isSerializeBefore() const
518    { return staticInst->isSerializeBefore() || status[SerializeBefore]; }
519    bool isSerializeAfter() const
520    { return staticInst->isSerializeAfter() || status[SerializeAfter]; }
521    bool isSquashAfter() const { return staticInst->isSquashAfter(); }
522    bool isMemBarrier()   const { return staticInst->isMemBarrier(); }
523    bool isWriteBarrier() const { return staticInst->isWriteBarrier(); }
524    bool isNonSpeculative() const { return staticInst->isNonSpeculative(); }
525    bool isQuiesce() const { return staticInst->isQuiesce(); }
526    bool isIprAccess() const { return staticInst->isIprAccess(); }
527    bool isUnverifiable() const { return staticInst->isUnverifiable(); }
528    bool isSyscall() const { return staticInst->isSyscall(); }
529    bool isMacroop() const { return staticInst->isMacroop(); }
530    bool isMicroop() const { return staticInst->isMicroop(); }
531    bool isDelayedCommit() const { return staticInst->isDelayedCommit(); }
532    bool isLastMicroop() const { return staticInst->isLastMicroop(); }
533    bool isFirstMicroop() const { return staticInst->isFirstMicroop(); }
534    bool isMicroBranch() const { return staticInst->isMicroBranch(); }
535
536    /** Temporarily sets this instruction as a serialize before instruction. */
537    void setSerializeBefore() { status.set(SerializeBefore); }
538
539    /** Clears the serializeBefore part of this instruction. */
540    void clearSerializeBefore() { status.reset(SerializeBefore); }
541
542    /** Checks if this serializeBefore is only temporarily set. */
543    bool isTempSerializeBefore() { return status[SerializeBefore]; }
544
545    /** Temporarily sets this instruction as a serialize after instruction. */
546    void setSerializeAfter() { status.set(SerializeAfter); }
547
548    /** Clears the serializeAfter part of this instruction.*/
549    void clearSerializeAfter() { status.reset(SerializeAfter); }
550
551    /** Checks if this serializeAfter is only temporarily set. */
552    bool isTempSerializeAfter() { return status[SerializeAfter]; }
553
554    /** Sets the serialization part of this instruction as handled. */
555    void setSerializeHandled() { status.set(SerializeHandled); }
556
557    /** Checks if the serialization part of this instruction has been
558     *  handled.  This does not apply to the temporary serializing
559     *  state; it only applies to this instruction's own permanent
560     *  serializing state.
561     */
562    bool isSerializeHandled() { return status[SerializeHandled]; }
563
564    /** Returns the opclass of this instruction. */
565    OpClass opClass() const { return staticInst->opClass(); }
566
567    /** Returns the branch target address. */
568    TheISA::PCState branchTarget() const
569    { return staticInst->branchTarget(pc); }
570
571    /** Returns the number of source registers. */
572    int8_t numSrcRegs() const { return staticInst->numSrcRegs(); }
573
574    /** Returns the number of destination registers. */
575    int8_t numDestRegs() const { return staticInst->numDestRegs(); }
576
577    // the following are used to track physical register usage
578    // for machines with separate int & FP reg files
579    int8_t numFPDestRegs()  const { return staticInst->numFPDestRegs(); }
580    int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); }
581    int8_t numCCDestRegs() const { return staticInst->numCCDestRegs(); }
582    int8_t numVecDestRegs() const { return staticInst->numVecDestRegs(); }
583    int8_t numVecElemDestRegs() const
584    {
585        return staticInst->numVecElemDestRegs();
586    }
587
588    /** Returns the logical register index of the i'th destination register. */
589    const RegId& destRegIdx(int i) const { return staticInst->destRegIdx(i); }
590
591    /** Returns the logical register index of the i'th source register. */
592    const RegId& srcRegIdx(int i) const { return staticInst->srcRegIdx(i); }
593
594    /** Return the size of the instResult queue. */
595    uint8_t resultSize() { return instResult.size(); }
596
597    /** Pops a result off the instResult queue.
598     * If the result stack is empty, return the default value.
599     * */
600    InstResult popResult(InstResult dflt = InstResult())
601    {
602        if (!instResult.empty()) {
603            InstResult t = instResult.front();
604            instResult.pop();
605            return t;
606        }
607        return dflt;
608    }
609
610    /** Pushes a result onto the instResult queue. */
611    /** @{ */
612    /** Scalar result. */
613    template<typename T>
614    void setScalarResult(T&& t)
615    {
616        if (instFlags[RecordResult]) {
617            instResult.push(InstResult(std::forward<T>(t),
618                        InstResult::ResultType::Scalar));
619        }
620    }
621
622    /** Full vector result. */
623    template<typename T>
624    void setVecResult(T&& t)
625    {
626        if (instFlags[RecordResult]) {
627            instResult.push(InstResult(std::forward<T>(t),
628                        InstResult::ResultType::VecReg));
629        }
630    }
631
632    /** Vector element result. */
633    template<typename T>
634    void setVecElemResult(T&& t)
635    {
636        if (instFlags[RecordResult]) {
637            instResult.push(InstResult(std::forward<T>(t),
638                        InstResult::ResultType::VecElem));
639        }
640    }
641    /** @} */
642
643    /** Records an integer register being set to a value. */
644    void setIntRegOperand(const StaticInst *si, int idx, RegVal val)
645    {
646        setScalarResult(val);
647    }
648
649    /** Records a CC register being set to a value. */
650    void setCCRegOperand(const StaticInst *si, int idx, CCReg val)
651    {
652        setScalarResult(val);
653    }
654
655    /** Record a vector register being set to a value */
656    void setVecRegOperand(const StaticInst *si, int idx,
657            const VecRegContainer& val)
658    {
659        setVecResult(val);
660    }
661
662    /** Records an fp register being set to an integer value. */
663    void
664    setFloatRegOperandBits(const StaticInst *si, int idx, RegVal val)
665    {
666        setScalarResult(val);
667    }
668
669    /** Record a vector register being set to a value */
670    void setVecElemOperand(const StaticInst *si, int idx, const VecElem val)
671    {
672        setVecElemResult(val);
673    }
674
675    /** Records that one of the source registers is ready. */
676    void markSrcRegReady();
677
678    /** Marks a specific register as ready. */
679    void markSrcRegReady(RegIndex src_idx);
680
681    /** Returns if a source register is ready. */
682    bool isReadySrcRegIdx(int idx) const
683    {
684        return this->_readySrcRegIdx[idx];
685    }
686
687    /** Sets this instruction as completed. */
688    void setCompleted() { status.set(Completed); }
689
690    /** Returns whether or not this instruction is completed. */
691    bool isCompleted() const { return status[Completed]; }
692
693    /** Marks the result as ready. */
694    void setResultReady() { status.set(ResultReady); }
695
696    /** Returns whether or not the result is ready. */
697    bool isResultReady() const { return status[ResultReady]; }
698
699    /** Sets this instruction as ready to issue. */
700    void setCanIssue() { status.set(CanIssue); }
701
702    /** Returns whether or not this instruction is ready to issue. */
703    bool readyToIssue() const { return status[CanIssue]; }
704
705    /** Clears this instruction being able to issue. */
706    void clearCanIssue() { status.reset(CanIssue); }
707
708    /** Sets this instruction as issued from the IQ. */
709    void setIssued() { status.set(Issued); }
710
711    /** Returns whether or not this instruction has issued. */
712    bool isIssued() const { return status[Issued]; }
713
714    /** Clears this instruction as being issued. */
715    void clearIssued() { status.reset(Issued); }
716
717    /** Sets this instruction as executed. */
718    void setExecuted() { status.set(Executed); }
719
720    /** Returns whether or not this instruction has executed. */
721    bool isExecuted() const { return status[Executed]; }
722
723    /** Sets this instruction as ready to commit. */
724    void setCanCommit() { status.set(CanCommit); }
725
726    /** Clears this instruction as being ready to commit. */
727    void clearCanCommit() { status.reset(CanCommit); }
728
729    /** Returns whether or not this instruction is ready to commit. */
730    bool readyToCommit() const { return status[CanCommit]; }
731
732    void setAtCommit() { status.set(AtCommit); }
733
734    bool isAtCommit() { return status[AtCommit]; }
735
736    /** Sets this instruction as committed. */
737    void setCommitted() { status.set(Committed); }
738
739    /** Returns whether or not this instruction is committed. */
740    bool isCommitted() const { return status[Committed]; }
741
742    /** Sets this instruction as squashed. */
743    void setSquashed() { status.set(Squashed); }
744
745    /** Returns whether or not this instruction is squashed. */
746    bool isSquashed() const { return status[Squashed]; }
747
748    //Instruction Queue Entry
749    //-----------------------
750    /** Sets this instruction as a entry the IQ. */
751    void setInIQ() { status.set(IqEntry); }
752
753    /** Sets this instruction as a entry the IQ. */
754    void clearInIQ() { status.reset(IqEntry); }
755
756    /** Returns whether or not this instruction has issued. */
757    bool isInIQ() const { return status[IqEntry]; }
758
759    /** Sets this instruction as squashed in the IQ. */
760    void setSquashedInIQ() { status.set(SquashedInIQ); status.set(Squashed);}
761
762    /** Returns whether or not this instruction is squashed in the IQ. */
763    bool isSquashedInIQ() const { return status[SquashedInIQ]; }
764
765
766    //Load / Store Queue Functions
767    //-----------------------
768    /** Sets this instruction as a entry the LSQ. */
769    void setInLSQ() { status.set(LsqEntry); }
770
771    /** Sets this instruction as a entry the LSQ. */
772    void removeInLSQ() { status.reset(LsqEntry); }
773
774    /** Returns whether or not this instruction is in the LSQ. */
775    bool isInLSQ() const { return status[LsqEntry]; }
776
777    /** Sets this instruction as squashed in the LSQ. */
778    void setSquashedInLSQ() { status.set(SquashedInLSQ);}
779
780    /** Returns whether or not this instruction is squashed in the LSQ. */
781    bool isSquashedInLSQ() const { return status[SquashedInLSQ]; }
782
783
784    //Reorder Buffer Functions
785    //-----------------------
786    /** Sets this instruction as a entry the ROB. */
787    void setInROB() { status.set(RobEntry); }
788
789    /** Sets this instruction as a entry the ROB. */
790    void clearInROB() { status.reset(RobEntry); }
791
792    /** Returns whether or not this instruction is in the ROB. */
793    bool isInROB() const { return status[RobEntry]; }
794
795    /** Sets this instruction as squashed in the ROB. */
796    void setSquashedInROB() { status.set(SquashedInROB); }
797
798    /** Returns whether or not this instruction is squashed in the ROB. */
799    bool isSquashedInROB() const { return status[SquashedInROB]; }
800
801    /** Read the PC state of this instruction. */
802    TheISA::PCState pcState() const { return pc; }
803
804    /** Set the PC state of this instruction. */
805    void pcState(const TheISA::PCState &val) { pc = val; }
806
807    /** Read the PC of this instruction. */
808    Addr instAddr() const { return pc.instAddr(); }
809
810    /** Read the PC of the next instruction. */
811    Addr nextInstAddr() const { return pc.nextInstAddr(); }
812
813    /**Read the micro PC of this instruction. */
814    Addr microPC() const { return pc.microPC(); }
815
816    bool readPredicate() const
817    {
818        return instFlags[Predicate];
819    }
820
821    void setPredicate(bool val)
822    {
823        instFlags[Predicate] = val;
824
825        if (traceData) {
826            traceData->setPredicate(val);
827        }
828    }
829
830    /** Sets the ASID. */
831    void setASID(short addr_space_id) { asid = addr_space_id; }
832    short getASID() { return asid; }
833
834    /** Sets the thread id. */
835    void setTid(ThreadID tid) { threadNumber = tid; }
836
837    /** Sets the pointer to the thread state. */
838    void setThreadState(ImplState *state) { thread = state; }
839
840    /** Returns the thread context. */
841    ThreadContext *tcBase() { return thread->getTC(); }
842
843  public:
844    /** Returns whether or not the eff. addr. source registers are ready. */
845    bool eaSrcsReady() const;
846
847    /** Is this instruction's memory access strictly ordered? */
848    bool strictlyOrdered() const { return instFlags[IsStrictlyOrdered]; }
849    void strictlyOrdered(bool so) { instFlags[IsStrictlyOrdered] = so; }
850
851    /** Has this instruction generated a memory request. */
852    bool hasRequest() const { return instFlags[ReqMade]; }
853    /** Assert this instruction has generated a memory request. */
854    void setRequest() { instFlags[ReqMade] = true; }
855
856    /** Returns iterator to this instruction in the list of all insts. */
857    ListIt &getInstListIt() { return instListIt; }
858
859    /** Sets iterator for this instruction in the list of all insts. */
860    void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; }
861
862  public:
863    /** Returns the number of consecutive store conditional failures. */
864    unsigned int readStCondFailures() const
865    { return thread->storeCondFailures; }
866
867    /** Sets the number of consecutive store conditional failures. */
868    void setStCondFailures(unsigned int sc_failures)
869    { thread->storeCondFailures = sc_failures; }
870
871  public:
872    // monitor/mwait funtions
873    void armMonitor(Addr address) { cpu->armMonitor(threadNumber, address); }
874    bool mwait(PacketPtr pkt) { return cpu->mwait(threadNumber, pkt); }
875    void mwaitAtomic(ThreadContext *tc)
876    { return cpu->mwaitAtomic(threadNumber, tc, cpu->dtb); }
877    AddressMonitor *getAddrMonitor()
878    { return cpu->getCpuAddrMonitor(threadNumber); }
879};
880
881template<class Impl>
882Fault
883BaseDynInst<Impl>::initiateMemRead(Addr addr, unsigned size,
884                                   Request::Flags flags)
885{
886    return cpu->pushRequest(
887            dynamic_cast<typename DynInstPtr::PtrType>(this),
888            /* ld */ true, nullptr, size, addr, flags, nullptr);
889}
890
891template<class Impl>
892Fault
893BaseDynInst<Impl>::writeMem(uint8_t *data, unsigned size, Addr addr,
894                            Request::Flags flags, uint64_t *res)
895{
896    return cpu->pushRequest(
897            dynamic_cast<typename DynInstPtr::PtrType>(this),
898            /* st */ false, data, size, addr, flags, res);
899}
900
901#endif // __CPU_BASE_DYN_INST_HH__
902