base_dyn_inst.hh revision 13590
11060SN/A/* 22702Sktlim@umich.edu * Copyright (c) 2011, 2013, 2016-2018 ARM Limited 31060SN/A * Copyright (c) 2013 Advanced Micro Devices, Inc. 41060SN/A * All rights reserved. 51060SN/A * 61060SN/A * The license below extends only to copyright in the software and shall 71060SN/A * not be construed as granting a license to any other intellectual 81060SN/A * property including but not limited to intellectual property relating 91060SN/A * to a hardware implementation of the functionality of the software 101060SN/A * licensed hereunder. You may use the software subject to the license 111060SN/A * terms below provided that you ensure that this notice is replicated 121060SN/A * unmodified and in its entirety in all distributions of the software, 131060SN/A * modified or unmodified, in source code or in binary form. 141060SN/A * 151060SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 161060SN/A * Copyright (c) 2009 The University of Edinburgh 171060SN/A * All rights reserved. 181060SN/A * 191060SN/A * Redistribution and use in source and binary forms, with or without 201060SN/A * modification, are permitted provided that the following conditions are 211060SN/A * met: redistributions of source code must retain the above copyright 221060SN/A * notice, this list of conditions and the following disclaimer; 231060SN/A * redistributions in binary form must reproduce the above copyright 241060SN/A * notice, this list of conditions and the following disclaimer in the 251060SN/A * documentation and/or other materials provided with the distribution; 261060SN/A * neither the name of the copyright holders nor the names of its 272665Ssaidi@eecs.umich.edu * contributors may be used to endorse or promote products derived from 282665Ssaidi@eecs.umich.edu * this software without specific prior written permission. 291060SN/A * 301060SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 311464SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 321464SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 331060SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 342731Sktlim@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 352292SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 361464SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 371060SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 382669Sktlim@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 391060SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 401060SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 411858SN/A * 423770Sgblack@eecs.umich.edu * Authors: Kevin Lim 431464SN/A * Timothy M. Jones 441464SN/A */ 452669Sktlim@umich.edu 461060SN/A#ifndef __CPU_BASE_DYN_INST_HH__ 472669Sktlim@umich.edu#define __CPU_BASE_DYN_INST_HH__ 482292SN/A 496023Snate@binkert.org#include <array> 501060SN/A#include <bitset> 511060SN/A#include <deque> 521060SN/A#include <list> 531060SN/A#include <string> 541060SN/A 551060SN/A#include "arch/generic/tlb.hh" 561061SN/A#include "arch/utility.hh" 571061SN/A#include "base/trace.hh" 581060SN/A#include "config/the_isa.hh" 591060SN/A#include "cpu/checker/cpu.hh" 601061SN/A#include "cpu/exec_context.hh" 611060SN/A#include "cpu/exetrace.hh" 621060SN/A#include "cpu/inst_res.hh" 631060SN/A#include "cpu/inst_seq.hh" 642733Sktlim@umich.edu#include "cpu/o3/comm.hh" 652733Sktlim@umich.edu#include "cpu/op_class.hh" 661060SN/A#include "cpu/static_inst.hh" 672292SN/A#include "cpu/translation.hh" 682107SN/A#include "mem/packet.hh" 692690Sktlim@umich.edu#include "mem/request.hh" 702107SN/A#include "sim/byteswap.hh" 712690Sktlim@umich.edu#include "sim/system.hh" 722690Sktlim@umich.edu 731060SN/A/** 742292SN/A * @file 752292SN/A * Defines a dynamic instruction context. 762292SN/A */ 772292SN/A 782292SN/Atemplate <class Impl> 792292SN/Aclass BaseDynInst : public ExecContext, public RefCounted 801060SN/A{ 815543Ssaidi@eecs.umich.edu public: 825543Ssaidi@eecs.umich.edu // Typedef for the CPU. 831060SN/A typedef typename Impl::CPUType ImplCPU; 841060SN/A typedef typename ImplCPU::ImplState ImplState; 852292SN/A using VecRegContainer = TheISA::VecRegContainer; 862107SN/A 871060SN/A using LSQRequestPtr = typename Impl::CPUPol::LSQ::LSQRequest*; 881060SN/A using LQIterator = typename Impl::CPUPol::LSQUnit::LQIterator; 891060SN/A using SQIterator = typename Impl::CPUPol::LSQUnit::SQIterator; 901060SN/A 911060SN/A // The DynInstPtr type. 921060SN/A typedef typename Impl::DynInstPtr DynInstPtr; 932292SN/A typedef RefCountingPtr<BaseDynInst<Impl> > BaseDynInstPtr; 941060SN/A 951060SN/A // The list of instructions iterator type. 965358Sgblack@eecs.umich.edu typedef typename std::list<DynInstPtr>::iterator ListIt; 975358Sgblack@eecs.umich.edu 985358Sgblack@eecs.umich.edu enum { 995358Sgblack@eecs.umich.edu MaxInstSrcRegs = TheISA::MaxInstSrcRegs, /// Max source regs 1005358Sgblack@eecs.umich.edu MaxInstDestRegs = TheISA::MaxInstDestRegs /// Max dest regs 1015358Sgblack@eecs.umich.edu }; 1025358Sgblack@eecs.umich.edu 1035358Sgblack@eecs.umich.edu protected: 1045358Sgblack@eecs.umich.edu enum Status { 1055358Sgblack@eecs.umich.edu IqEntry, /// Instruction is in the IQ 1065358Sgblack@eecs.umich.edu RobEntry, /// Instruction is in the ROB 1075358Sgblack@eecs.umich.edu LsqEntry, /// Instruction is in the LSQ 1085358Sgblack@eecs.umich.edu Completed, /// Instruction has completed 1092292SN/A ResultReady, /// Instruction has its result 1102292SN/A CanIssue, /// Instruction can issue and execute 1112292SN/A Issued, /// Instruction has issued 1122292SN/A Executed, /// Instruction has executed 1132292SN/A CanCommit, /// Instruction can commit 1142292SN/A AtCommit, /// Instruction has reached commit 1152292SN/A Committed, /// Instruction has committed 1161060SN/A Squashed, /// Instruction is squashed 1172132SN/A SquashedInIQ, /// Instruction is squashed in the IQ 1181060SN/A SquashedInLSQ, /// Instruction is squashed in the LSQ 1192292SN/A SquashedInROB, /// Instruction is squashed in the ROB 1202292SN/A RecoverInst, /// Is a recover instruction 1212292SN/A BlockingInst, /// Is a blocking instruction 1222292SN/A ThreadsyncWait, /// Is a thread synchronization instruction 1232292SN/A SerializeBefore, /// Needs to serialize on 1242292SN/A /// instructions ahead of it 1252292SN/A SerializeAfter, /// Needs to serialize instructions behind it 1262292SN/A SerializeHandled, /// Serialization has been handled 1271060SN/A NumStatus 1282132SN/A }; 1291060SN/A 1301060SN/A enum Flags { 1311060SN/A NotAnInst, 1321060SN/A TranslationStarted, 1332132SN/A TranslationCompleted, 1342132SN/A PossibleLoadViolation, 1351060SN/A HitExternalSnoop, 1361684SN/A EffAddrValid, 1371060SN/A RecordResult, 1381060SN/A Predicate, 1391060SN/A PredTaken, 1401060SN/A IsStrictlyOrdered, 1412731Sktlim@umich.edu ReqMade, 1422731Sktlim@umich.edu MemOpDone, 1432731Sktlim@umich.edu MaxFlags 1442731Sktlim@umich.edu }; 1452731Sktlim@umich.edu 1462731Sktlim@umich.edu public: 1472731Sktlim@umich.edu /** The sequence number of the instruction. */ 1482731Sktlim@umich.edu InstSeqNum seqNum; 1492731Sktlim@umich.edu 1502731Sktlim@umich.edu /** The StaticInst used by this BaseDynInst. */ 1512731Sktlim@umich.edu const StaticInstPtr staticInst; 1522731Sktlim@umich.edu 1532731Sktlim@umich.edu /** Pointer to the Impl's CPU object. */ 1542731Sktlim@umich.edu ImplCPU *cpu; 1552731Sktlim@umich.edu 1562731Sktlim@umich.edu BaseCPU *getCpuPtr() { return cpu; } 1572731Sktlim@umich.edu 1582731Sktlim@umich.edu /** Pointer to the thread state. */ 1592731Sktlim@umich.edu ImplState *thread; 1602731Sktlim@umich.edu 1612731Sktlim@umich.edu /** The kind of fault this instruction has generated. */ 1622731Sktlim@umich.edu Fault fault; 1632731Sktlim@umich.edu 1642731Sktlim@umich.edu /** InstRecord that tracks this instructions. */ 1652731Sktlim@umich.edu Trace::InstRecord *traceData; 1662292SN/A 1672731Sktlim@umich.edu protected: 1682731Sktlim@umich.edu /** The result of the instruction; assumes an instruction can have many 1691060SN/A * destination registers. 1701060SN/A */ 1716221Snate@binkert.org std::queue<InstResult> instResult; 1721060SN/A 1731060SN/A /** PC state for this instruction. */ 1741060SN/A TheISA::PCState pc; 1751060SN/A 1762292SN/A /* An amalgamation of a lot of boolean values into one */ 1772292SN/A std::bitset<MaxFlags> instFlags; 1782292SN/A 1792733Sktlim@umich.edu /** The status of this BaseDynInst. Several bits can be set. */ 1802733Sktlim@umich.edu std::bitset<NumStatus> status; 1811060SN/A 1822680Sktlim@umich.edu /** Whether or not the source register is ready. 1832292SN/A * @todo: Not sure this should be here vs the derived class. 1841060SN/A */ 1851060SN/A std::bitset<MaxInstSrcRegs> _readySrcRegIdx; 1862132SN/A 1871060SN/A public: 1882702Sktlim@umich.edu /** The thread this instruction is from. */ 1892669Sktlim@umich.edu ThreadID threadNumber; 1902292SN/A 1911060SN/A /** Iterator pointing to this BaseDynInst in the list of all insts. */ 1921060SN/A ListIt instListIt; 1931060SN/A 1944032Sktlim@umich.edu ////////////////////// Branch Data /////////////// 1954032Sktlim@umich.edu /** Predicted PC state after this instruction. */ 1964032Sktlim@umich.edu TheISA::PCState predPC; 1971060SN/A 1981060SN/A /** The Macroop if one exists */ 1991060SN/A const StaticInstPtr macroop; 2001060SN/A 2011060SN/A /** How many source registers are ready. */ 2021060SN/A uint8_t readyRegs; 2031060SN/A 2041060SN/A public: 2051060SN/A /////////////////////// Load Store Data ////////////////////// 2061060SN/A /** The effective virtual address (lds & stores only). */ 2071060SN/A Addr effAddr; 2081060SN/A 2091464SN/A /** The effective physical address. */ 2101464SN/A Addr physEffAddr; 2112356SN/A 2121464SN/A /** The memory request flags (from translation). */ 2131464SN/A unsigned memReqFlags; 2141060SN/A 2151464SN/A /** data address space ID, for loads & stores. */ 2161464SN/A short asid; 2171464SN/A 2181464SN/A /** The size of the request */ 2191060SN/A uint8_t effSize; 2203326Sktlim@umich.edu 2213326Sktlim@umich.edu /** Pointer to the data for the memory access. */ 2223326Sktlim@umich.edu uint8_t *memData; 2231060SN/A 2241060SN/A /** Load queue index. */ 2251060SN/A int16_t lqIdx; 2264636Sgblack@eecs.umich.edu LQIterator lqIt; 2274636Sgblack@eecs.umich.edu 2284636Sgblack@eecs.umich.edu /** Store queue index. */ 2293965Sgblack@eecs.umich.edu int16_t sqIdx; 2301060SN/A SQIterator sqIt; 2311060SN/A 2321060SN/A 2331060SN/A /////////////////////// TLB Miss ////////////////////// 2341060SN/A /** 2351060SN/A * Saved memory request (needed when the DTB address translation is 2362935Sksewell@umich.edu * delayed due to a hw page table walk). 2372935Sksewell@umich.edu */ 2382935Sksewell@umich.edu LSQRequestPtr savedReq; 2394636Sgblack@eecs.umich.edu 2404636Sgblack@eecs.umich.edu /////////////////////// Checker ////////////////////// 2414636Sgblack@eecs.umich.edu // Need a copy of main request pointer to verify on writes. 2421060SN/A RequestPtr reqToVerify; 2431060SN/A 2441060SN/A protected: 2453794Sgblack@eecs.umich.edu /** Flattened register index of the destination registers of this 2463794Sgblack@eecs.umich.edu * instruction. 2473794Sgblack@eecs.umich.edu */ 2484636Sgblack@eecs.umich.edu std::array<RegId, TheISA::MaxInstDestRegs> _flatDestRegIdx; 2494636Sgblack@eecs.umich.edu 2504636Sgblack@eecs.umich.edu /** Physical register index of the destination registers of this 2513794Sgblack@eecs.umich.edu * instruction. 2523794Sgblack@eecs.umich.edu */ 2533794Sgblack@eecs.umich.edu std::array<PhysRegIdPtr, TheISA::MaxInstDestRegs> _destRegIdx; 2543965Sgblack@eecs.umich.edu 2553965Sgblack@eecs.umich.edu /** Physical register index of the source registers of this 2562292SN/A * instruction. 2572292SN/A */ 2582292SN/A std::array<PhysRegIdPtr, TheISA::MaxInstSrcRegs> _srcRegIdx; 2592292SN/A 2602292SN/A /** Physical register index of the previous producers of the 2612292SN/A * architected destinations. 2621060SN/A */ 2631060SN/A std::array<PhysRegIdPtr, TheISA::MaxInstDestRegs> _prevDestRegIdx; 2641060SN/A 2653770Sgblack@eecs.umich.edu 2663770Sgblack@eecs.umich.edu public: 2673770Sgblack@eecs.umich.edu /** Records changes to result? */ 2683770Sgblack@eecs.umich.edu void recordResult(bool f) { instFlags[RecordResult] = f; } 2693770Sgblack@eecs.umich.edu 2703770Sgblack@eecs.umich.edu /** Is the effective virtual address valid. */ 2713770Sgblack@eecs.umich.edu bool effAddrValid() const { return instFlags[EffAddrValid]; } 2723770Sgblack@eecs.umich.edu void effAddrValid(bool b) { instFlags[EffAddrValid] = b; } 2733770Sgblack@eecs.umich.edu 2743770Sgblack@eecs.umich.edu /** Whether or not the memory operation is done. */ 2753770Sgblack@eecs.umich.edu bool memOpDone() const { return instFlags[MemOpDone]; } 2763770Sgblack@eecs.umich.edu void memOpDone(bool f) { instFlags[MemOpDone] = f; } 2773770Sgblack@eecs.umich.edu 2783770Sgblack@eecs.umich.edu bool notAnInst() const { return instFlags[NotAnInst]; } 2793770Sgblack@eecs.umich.edu void setNotAnInst() { instFlags[NotAnInst] = true; } 2803770Sgblack@eecs.umich.edu 2813770Sgblack@eecs.umich.edu 2823770Sgblack@eecs.umich.edu //////////////////////////////////////////// 2833770Sgblack@eecs.umich.edu // 2843770Sgblack@eecs.umich.edu // INSTRUCTION EXECUTION 2853770Sgblack@eecs.umich.edu // 2863770Sgblack@eecs.umich.edu //////////////////////////////////////////// 2873770Sgblack@eecs.umich.edu 2883770Sgblack@eecs.umich.edu void demapPage(Addr vaddr, uint64_t asn) 2893770Sgblack@eecs.umich.edu { 2903770Sgblack@eecs.umich.edu cpu->demapPage(vaddr, asn); 2911060SN/A } 2923770Sgblack@eecs.umich.edu void demapInstPage(Addr vaddr, uint64_t asn) 2933770Sgblack@eecs.umich.edu { 2943770Sgblack@eecs.umich.edu cpu->demapPage(vaddr, asn); 2953770Sgblack@eecs.umich.edu } 2963770Sgblack@eecs.umich.edu void demapDataPage(Addr vaddr, uint64_t asn) 2973770Sgblack@eecs.umich.edu { 2983770Sgblack@eecs.umich.edu cpu->demapPage(vaddr, asn); 2993770Sgblack@eecs.umich.edu } 3003770Sgblack@eecs.umich.edu 3013770Sgblack@eecs.umich.edu Fault initiateMemRead(Addr addr, unsigned size, Request::Flags flags); 3023770Sgblack@eecs.umich.edu 3033770Sgblack@eecs.umich.edu Fault writeMem(uint8_t *data, unsigned size, Addr addr, 3043770Sgblack@eecs.umich.edu Request::Flags flags, uint64_t *res); 3053770Sgblack@eecs.umich.edu 3063770Sgblack@eecs.umich.edu /** True if the DTB address translation has started. */ 3073770Sgblack@eecs.umich.edu bool translationStarted() const { return instFlags[TranslationStarted]; } 3083770Sgblack@eecs.umich.edu void translationStarted(bool f) { instFlags[TranslationStarted] = f; } 3093770Sgblack@eecs.umich.edu 3103770Sgblack@eecs.umich.edu /** True if the DTB address translation has completed. */ 3113770Sgblack@eecs.umich.edu bool translationCompleted() const { return instFlags[TranslationCompleted]; } 3123770Sgblack@eecs.umich.edu void translationCompleted(bool f) { instFlags[TranslationCompleted] = f; } 3133770Sgblack@eecs.umich.edu 3143770Sgblack@eecs.umich.edu /** True if this address was found to match a previous load and they issued 3153770Sgblack@eecs.umich.edu * out of order. If that happend, then it's only a problem if an incoming 3163770Sgblack@eecs.umich.edu * snoop invalidate modifies the line, in which case we need to squash. 3173770Sgblack@eecs.umich.edu * If nothing modified the line the order doesn't matter. 3183770Sgblack@eecs.umich.edu */ 3193770Sgblack@eecs.umich.edu bool possibleLoadViolation() const { return instFlags[PossibleLoadViolation]; } 3203770Sgblack@eecs.umich.edu void possibleLoadViolation(bool f) { instFlags[PossibleLoadViolation] = f; } 3213770Sgblack@eecs.umich.edu 3223770Sgblack@eecs.umich.edu /** True if the address hit a external snoop while sitting in the LSQ. 3233770Sgblack@eecs.umich.edu * If this is true and a older instruction sees it, this instruction must 3243770Sgblack@eecs.umich.edu * reexecute 3253770Sgblack@eecs.umich.edu */ 3263770Sgblack@eecs.umich.edu bool hitExternalSnoop() const { return instFlags[HitExternalSnoop]; } 3273770Sgblack@eecs.umich.edu void hitExternalSnoop(bool f) { instFlags[HitExternalSnoop] = f; } 3283770Sgblack@eecs.umich.edu 3293770Sgblack@eecs.umich.edu /** 3303770Sgblack@eecs.umich.edu * Returns true if the DTB address translation is being delayed due to a hw 3313770Sgblack@eecs.umich.edu * page table walk. 3323770Sgblack@eecs.umich.edu */ 3333770Sgblack@eecs.umich.edu bool isTranslationDelayed() const 3343770Sgblack@eecs.umich.edu { 3353770Sgblack@eecs.umich.edu return (translationStarted() && !translationCompleted()); 3363770Sgblack@eecs.umich.edu } 3373770Sgblack@eecs.umich.edu 3383770Sgblack@eecs.umich.edu public: 3393770Sgblack@eecs.umich.edu#ifdef DEBUG 3403770Sgblack@eecs.umich.edu void dumpSNList(); 3413770Sgblack@eecs.umich.edu#endif 3423770Sgblack@eecs.umich.edu 3433770Sgblack@eecs.umich.edu /** Returns the physical register index of the i'th destination 3443770Sgblack@eecs.umich.edu * register. 3453770Sgblack@eecs.umich.edu */ 3463770Sgblack@eecs.umich.edu PhysRegIdPtr renamedDestRegIdx(int idx) const 3473770Sgblack@eecs.umich.edu { 3483770Sgblack@eecs.umich.edu return _destRegIdx[idx]; 3493770Sgblack@eecs.umich.edu } 3503770Sgblack@eecs.umich.edu 3513770Sgblack@eecs.umich.edu /** Returns the physical register index of the i'th source register. */ 3523770Sgblack@eecs.umich.edu PhysRegIdPtr renamedSrcRegIdx(int idx) const 3533770Sgblack@eecs.umich.edu { 3543770Sgblack@eecs.umich.edu assert(TheISA::MaxInstSrcRegs > idx); 3553770Sgblack@eecs.umich.edu return _srcRegIdx[idx]; 3563770Sgblack@eecs.umich.edu } 3573770Sgblack@eecs.umich.edu 3583770Sgblack@eecs.umich.edu /** Returns the flattened register index of the i'th destination 3593770Sgblack@eecs.umich.edu * register. 3603770Sgblack@eecs.umich.edu */ 3613770Sgblack@eecs.umich.edu const RegId& flattenedDestRegIdx(int idx) const 3623770Sgblack@eecs.umich.edu { 3634636Sgblack@eecs.umich.edu return _flatDestRegIdx[idx]; 3644636Sgblack@eecs.umich.edu } 3654636Sgblack@eecs.umich.edu 3664636Sgblack@eecs.umich.edu /** Returns the physical register index of the previous physical register 3674636Sgblack@eecs.umich.edu * that remapped to the same logical register index. 3684636Sgblack@eecs.umich.edu */ 3694636Sgblack@eecs.umich.edu PhysRegIdPtr prevDestRegIdx(int idx) const 3704636Sgblack@eecs.umich.edu { 3714636Sgblack@eecs.umich.edu return _prevDestRegIdx[idx]; 3724636Sgblack@eecs.umich.edu } 3734636Sgblack@eecs.umich.edu 3743770Sgblack@eecs.umich.edu /** Renames a destination register to a physical register. Also records 3752292SN/A * the previous physical register that the logical register mapped to. 3762292SN/A */ 3772292SN/A void renameDestReg(int idx, 3782292SN/A PhysRegIdPtr renamed_dest, 3793794Sgblack@eecs.umich.edu PhysRegIdPtr previous_rename) 3802292SN/A { 3812292SN/A _destRegIdx[idx] = renamed_dest; 3822292SN/A _prevDestRegIdx[idx] = previous_rename; 3834636Sgblack@eecs.umich.edu } 3844636Sgblack@eecs.umich.edu 3853770Sgblack@eecs.umich.edu /** Renames a source logical register to the physical register which 3861060SN/A * has/will produce that logical register's result. 3872292SN/A * @todo: add in whether or not the source register is ready. 3882292SN/A */ 3892292SN/A void renameSrcReg(int idx, PhysRegIdPtr renamed_src) 3902107SN/A { 3911060SN/A _srcRegIdx[idx] = renamed_src; 3921060SN/A } 3931060SN/A 3941060SN/A /** Flattens a destination architectural register index into a logical 3951464SN/A * index. 3961684SN/A */ 3971464SN/A void flattenDestReg(int idx, const RegId& flattened_dest) 3981060SN/A { 3991464SN/A _flatDestRegIdx[idx] = flattened_dest; 4001060SN/A } 4011060SN/A /** BaseDynInst constructor given a binary instruction. 4021060SN/A * @param staticInst A StaticInstPtr to the underlying instruction. 4031060SN/A * @param pc The PC state for the instruction. 4041060SN/A * @param predPC The predicted next PC state for the instruction. 4051060SN/A * @param seq_num The sequence number of the instruction. 4063326Sktlim@umich.edu * @param cpu Pointer to the instruction's CPU. 4075712Shsul@eecs.umich.edu */ 4083326Sktlim@umich.edu BaseDynInst(const StaticInstPtr &staticInst, const StaticInstPtr ¯oop, 4095714Shsul@eecs.umich.edu TheISA::PCState pc, TheISA::PCState predPC, 4105714Shsul@eecs.umich.edu InstSeqNum seq_num, ImplCPU *cpu); 4115714Shsul@eecs.umich.edu 4121060SN/A /** BaseDynInst constructor given a StaticInst pointer. 4132132SN/A * @param _staticInst The StaticInst for this BaseDynInst. 4141060SN/A */ 4151060SN/A BaseDynInst(const StaticInstPtr &staticInst, const StaticInstPtr ¯oop); 4161060SN/A 4171060SN/A /** BaseDynInst destructor. */ 4182292SN/A ~BaseDynInst(); 4191060SN/A 4201060SN/A private: 4211060SN/A /** Function to initialize variables in the constructors. */ 4221684SN/A void initVars(); 4231684SN/A 4241684SN/A public: 4251060SN/A /** Dumps out contents of this BaseDynInst. */ 4261060SN/A void dump(); 4272935Sksewell@umich.edu 4282935Sksewell@umich.edu /** Dumps out contents of this BaseDynInst into given string. */ 4292935Sksewell@umich.edu void dump(std::string &outstring); 4303965Sgblack@eecs.umich.edu 4313965Sgblack@eecs.umich.edu /** Read this CPU's ID. */ 4323965Sgblack@eecs.umich.edu int cpuId() const { return cpu->cpuId(); } 4333965Sgblack@eecs.umich.edu 4343965Sgblack@eecs.umich.edu /** Read this CPU's Socket ID. */ 4353965Sgblack@eecs.umich.edu uint32_t socketId() const { return cpu->socketId(); } 4363965Sgblack@eecs.umich.edu 4373965Sgblack@eecs.umich.edu /** Read this CPU's data requestor ID */ 4382935Sksewell@umich.edu MasterID masterId() const { return cpu->dataMasterId(); } 4394636Sgblack@eecs.umich.edu 4404636Sgblack@eecs.umich.edu /** Read this context's system-wide ID **/ 4414636Sgblack@eecs.umich.edu ContextID contextId() const { return thread->contextId(); } 4424636Sgblack@eecs.umich.edu 4434636Sgblack@eecs.umich.edu /** Returns the fault type. */ 4441060SN/A Fault getFault() const { return fault; } 4454636Sgblack@eecs.umich.edu /** TODO: This I added for the LSQRequest side to be able to modify the 4464636Sgblack@eecs.umich.edu * fault. There should be a better mechanism in place. */ 4473794Sgblack@eecs.umich.edu Fault& getFault() { return fault; } 4483794Sgblack@eecs.umich.edu 4493794Sgblack@eecs.umich.edu /** Checks whether or not this instruction has had its branch target 4504636Sgblack@eecs.umich.edu * calculated yet. For now it is not utilized and is hacked to be 4513794Sgblack@eecs.umich.edu * always false. 4521060SN/A * @todo: Actually use this instruction. 4533794Sgblack@eecs.umich.edu */ 4543794Sgblack@eecs.umich.edu bool doneTargCalc() { return false; } 4553794Sgblack@eecs.umich.edu 4563794Sgblack@eecs.umich.edu /** Set the predicted target of this current instruction. */ 4573794Sgblack@eecs.umich.edu void setPredTarg(const TheISA::PCState &_predPC) 4581060SN/A { 4594636Sgblack@eecs.umich.edu predPC = _predPC; 4604636Sgblack@eecs.umich.edu } 4614636Sgblack@eecs.umich.edu 4621060SN/A const TheISA::PCState &readPredTarg() { return predPC; } 4633794Sgblack@eecs.umich.edu 4643794Sgblack@eecs.umich.edu /** Returns the predicted PC immediately after the branch. */ 4653794Sgblack@eecs.umich.edu Addr predInstAddr() { return predPC.instAddr(); } 4663794Sgblack@eecs.umich.edu 4673794Sgblack@eecs.umich.edu /** Returns the predicted PC two instructions after the branch */ 4683794Sgblack@eecs.umich.edu Addr predNextInstAddr() { return predPC.nextInstAddr(); } 4693794Sgblack@eecs.umich.edu 4703794Sgblack@eecs.umich.edu /** Returns the predicted micro PC after the branch */ 4713794Sgblack@eecs.umich.edu Addr predMicroPC() { return predPC.microPC(); } 4721060SN/A 4731060SN/A /** Returns whether the instruction was predicted taken or not. */ 4742935Sksewell@umich.edu bool readPredTaken() 4753794Sgblack@eecs.umich.edu { 4763965Sgblack@eecs.umich.edu return instFlags[PredTaken]; 4774636Sgblack@eecs.umich.edu } 4784636Sgblack@eecs.umich.edu 4793794Sgblack@eecs.umich.edu void setPredTaken(bool predicted_taken) 4803794Sgblack@eecs.umich.edu { 4811060SN/A instFlags[PredTaken] = predicted_taken; 4821060SN/A } 4831060SN/A 4845543Ssaidi@eecs.umich.edu /** Returns whether the instruction mispredicted. */ 4855543Ssaidi@eecs.umich.edu bool mispredicted() 4865543Ssaidi@eecs.umich.edu { 4875543Ssaidi@eecs.umich.edu TheISA::PCState tempPC = pc; 4882336SN/A TheISA::advancePC(tempPC, staticInst); 4892336SN/A return !(tempPC == predPC); 4901060SN/A } 4911060SN/A 4921060SN/A // 4935543Ssaidi@eecs.umich.edu // Instruction types. Forward checks to StaticInst object. 4945543Ssaidi@eecs.umich.edu // 4955543Ssaidi@eecs.umich.edu bool isNop() const { return staticInst->isNop(); } 4965543Ssaidi@eecs.umich.edu bool isMemRef() const { return staticInst->isMemRef(); } 4975543Ssaidi@eecs.umich.edu bool isLoad() const { return staticInst->isLoad(); } 4985543Ssaidi@eecs.umich.edu bool isStore() const { return staticInst->isStore(); } 4991060SN/A bool isAtomic() const { return staticInst->isAtomic(); } 5005543Ssaidi@eecs.umich.edu bool isStoreConditional() const 5015543Ssaidi@eecs.umich.edu { return staticInst->isStoreConditional(); } 5022935Sksewell@umich.edu bool isInstPrefetch() const { return staticInst->isInstPrefetch(); } 5031060SN/A bool isDataPrefetch() const { return staticInst->isDataPrefetch(); } 5041060SN/A bool isInteger() const { return staticInst->isInteger(); } 5052292SN/A bool isFloating() const { return staticInst->isFloating(); } 5062731Sktlim@umich.edu bool isVector() const { return staticInst->isVector(); } 5072292SN/A bool isControl() const { return staticInst->isControl(); } 5082731Sktlim@umich.edu bool isCall() const { return staticInst->isCall(); } 5091060SN/A bool isReturn() const { return staticInst->isReturn(); } 5101060SN/A bool isDirectCtrl() const { return staticInst->isDirectCtrl(); } 5111060SN/A bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); } 5122292SN/A bool isCondCtrl() const { return staticInst->isCondCtrl(); } 5132336SN/A bool isUncondCtrl() const { return staticInst->isUncondCtrl(); } 5142308SN/A bool isCondDelaySlot() const { return staticInst->isCondDelaySlot(); } 5154828Sgblack@eecs.umich.edu bool isThreadSync() const { return staticInst->isThreadSync(); } 5164654Sgblack@eecs.umich.edu bool isSerializing() const { return staticInst->isSerializing(); } 5174654Sgblack@eecs.umich.edu bool isSerializeBefore() const 5184636Sgblack@eecs.umich.edu { return staticInst->isSerializeBefore() || status[SerializeBefore]; } 5194654Sgblack@eecs.umich.edu bool isSerializeAfter() const 5204654Sgblack@eecs.umich.edu { return staticInst->isSerializeAfter() || status[SerializeAfter]; } 5214636Sgblack@eecs.umich.edu bool isSquashAfter() const { return staticInst->isSquashAfter(); } 5222292SN/A bool isMemBarrier() const { return staticInst->isMemBarrier(); } 5232292SN/A bool isWriteBarrier() const { return staticInst->isWriteBarrier(); } 5242731Sktlim@umich.edu bool isNonSpeculative() const { return staticInst->isNonSpeculative(); } 5252292SN/A bool isQuiesce() const { return staticInst->isQuiesce(); } 5262292SN/A bool isIprAccess() const { return staticInst->isIprAccess(); } 5272731Sktlim@umich.edu bool isUnverifiable() const { return staticInst->isUnverifiable(); } 5282292SN/A bool isSyscall() const { return staticInst->isSyscall(); } 5292292SN/A bool isMacroop() const { return staticInst->isMacroop(); } 5302731Sktlim@umich.edu bool isMicroop() const { return staticInst->isMicroop(); } 5312292SN/A bool isDelayedCommit() const { return staticInst->isDelayedCommit(); } 5322292SN/A bool isLastMicroop() const { return staticInst->isLastMicroop(); } 5332731Sktlim@umich.edu bool isFirstMicroop() const { return staticInst->isFirstMicroop(); } 5342292SN/A bool isMicroBranch() const { return staticInst->isMicroBranch(); } 5352292SN/A 5362731Sktlim@umich.edu /** Temporarily sets this instruction as a serialize before instruction. */ 5372292SN/A void setSerializeBefore() { status.set(SerializeBefore); } 5382292SN/A 5392731Sktlim@umich.edu /** Clears the serializeBefore part of this instruction. */ 5402292SN/A void clearSerializeBefore() { status.reset(SerializeBefore); } 5412731Sktlim@umich.edu 5422731Sktlim@umich.edu /** Checks if this serializeBefore is only temporarily set. */ 5432292SN/A bool isTempSerializeBefore() { return status[SerializeBefore]; } 5442292SN/A 5452292SN/A /** Temporarily sets this instruction as a serialize after instruction. */ 5462292SN/A void setSerializeAfter() { status.set(SerializeAfter); } 5472292SN/A 5482292SN/A /** Clears the serializeAfter part of this instruction.*/ 5492731Sktlim@umich.edu void clearSerializeAfter() { status.reset(SerializeAfter); } 5501060SN/A 5511464SN/A /** Checks if this serializeAfter is only temporarily set. */ 5521464SN/A bool isTempSerializeAfter() { return status[SerializeAfter]; } 5531464SN/A 5541464SN/A /** Sets the serialization part of this instruction as handled. */ 5551464SN/A void setSerializeHandled() { status.set(SerializeHandled); } 5561464SN/A 5572292SN/A /** Checks if the serialization part of this instruction has been 5585543Ssaidi@eecs.umich.edu * handled. This does not apply to the temporary serializing 5591684SN/A * state; it only applies to this instruction's own permanent 5602292SN/A * serializing state. 5611060SN/A */ 5621060SN/A bool isSerializeHandled() { return status[SerializeHandled]; } 5631060SN/A 5641060SN/A /** Returns the opclass of this instruction. */ 5651060SN/A OpClass opClass() const { return staticInst->opClass(); } 5661060SN/A 5671060SN/A /** Returns the branch target address. */ 5681060SN/A TheISA::PCState branchTarget() const 5692292SN/A { return staticInst->branchTarget(pc); } 5701060SN/A 5711060SN/A /** Returns the number of source registers. */ 5722292SN/A int8_t numSrcRegs() const { return staticInst->numSrcRegs(); } 5731060SN/A 5741684SN/A /** Returns the number of destination registers. */ 5751464SN/A int8_t numDestRegs() const { return staticInst->numDestRegs(); } 5761684SN/A 5771684SN/A // the following are used to track physical register usage 5782356SN/A // for machines with separate int & FP reg files 5791684SN/A int8_t numFPDestRegs() const { return staticInst->numFPDestRegs(); } 5801684SN/A int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); } 5811464SN/A int8_t numCCDestRegs() const { return staticInst->numCCDestRegs(); } 5821060SN/A int8_t numVecDestRegs() const { return staticInst->numVecDestRegs(); } 5832702Sktlim@umich.edu int8_t numVecElemDestRegs() const 5843735Sstever@eecs.umich.edu { 5851060SN/A return staticInst->numVecElemDestRegs(); 5863326Sktlim@umich.edu } 5873326Sktlim@umich.edu 5881060SN/A /** Returns the logical register index of the i'th destination register. */ 5891060SN/A const RegId& destRegIdx(int i) const { return staticInst->destRegIdx(i); } 5902702Sktlim@umich.edu 5913735Sstever@eecs.umich.edu /** Returns the logical register index of the i'th source register. */ 5923735Sstever@eecs.umich.edu const RegId& srcRegIdx(int i) const { return staticInst->srcRegIdx(i); } 5932690Sktlim@umich.edu 5943326Sktlim@umich.edu /** Return the size of the instResult queue. */ 5953326Sktlim@umich.edu uint8_t resultSize() { return instResult.size(); } 5963326Sktlim@umich.edu 5973326Sktlim@umich.edu /** Pops a result off the instResult queue. 5983326Sktlim@umich.edu * If the result stack is empty, return the default value. 5993326Sktlim@umich.edu * */ 6003326Sktlim@umich.edu InstResult popResult(InstResult dflt = InstResult()) 6013326Sktlim@umich.edu { 6022690Sktlim@umich.edu if (!instResult.empty()) { 6032690Sktlim@umich.edu InstResult t = instResult.front(); 6042702Sktlim@umich.edu instResult.pop(); 6053735Sstever@eecs.umich.edu return t; 6061060SN/A } 6073326Sktlim@umich.edu return dflt; 6083326Sktlim@umich.edu } 6092308SN/A 6101060SN/A /** Pushes a result onto the instResult queue. */ 6112702Sktlim@umich.edu /** @{ */ 6123735Sstever@eecs.umich.edu /** Scalar result. */ 6133735Sstever@eecs.umich.edu template<typename T> 6142308SN/A void setScalarResult(T&& t) 6153326Sktlim@umich.edu { 6163326Sktlim@umich.edu if (instFlags[RecordResult]) { 6172308SN/A instResult.push(InstResult(std::forward<T>(t), 6181060SN/A InstResult::ResultType::Scalar)); 6192702Sktlim@umich.edu } 6203735Sstever@eecs.umich.edu } 6212308SN/A 6223326Sktlim@umich.edu /** Full vector result. */ 6233326Sktlim@umich.edu template<typename T> 6241060SN/A void setVecResult(T&& t) 6251060SN/A { 6262190SN/A if (instFlags[RecordResult]) { 6272292SN/A instResult.push(InstResult(std::forward<T>(t), 6282190SN/A InstResult::ResultType::VecReg)); 6292331SN/A } 6302292SN/A } 6312190SN/A 6321684SN/A /** Vector element result. */ 6331464SN/A template<typename T> 6341464SN/A void setVecElemResult(T&& t) 6351464SN/A { 6361464SN/A if (instFlags[RecordResult]) { 6371464SN/A instResult.push(InstResult(std::forward<T>(t), 6381684SN/A InstResult::ResultType::VecElem)); 6392731Sktlim@umich.edu } 6401464SN/A } 6412292SN/A /** @} */ 6422731Sktlim@umich.edu 6431464SN/A /** Records an integer register being set to a value. */ 6442731Sktlim@umich.edu void setIntRegOperand(const StaticInst *si, int idx, RegVal val) 6452731Sktlim@umich.edu { 6462308SN/A setScalarResult(val); 6472731Sktlim@umich.edu } 6482731Sktlim@umich.edu 6492308SN/A /** Records a CC register being set to a value. */ 6501060SN/A void setCCRegOperand(const StaticInst *si, int idx, CCReg val) 6512731Sktlim@umich.edu { 6521060SN/A setScalarResult(val); 6531060SN/A } 6542731Sktlim@umich.edu 6551060SN/A /** Record a vector register being set to a value */ 6564032Sktlim@umich.edu void setVecRegOperand(const StaticInst *si, int idx, 6574032Sktlim@umich.edu const VecRegContainer& val) 6584032Sktlim@umich.edu { 6591060SN/A setVecResult(val); 6602731Sktlim@umich.edu } 6611060SN/A 6621060SN/A /** Records an fp register being set to an integer value. */ 6632731Sktlim@umich.edu void 6641060SN/A setFloatRegOperandBits(const StaticInst *si, int idx, RegVal val) 6654032Sktlim@umich.edu { 6664032Sktlim@umich.edu setScalarResult(val); 6674032Sktlim@umich.edu } 6681060SN/A 6692731Sktlim@umich.edu /** Record a vector register being set to a value */ 6701060SN/A void setVecElemOperand(const StaticInst *si, int idx, const VecElem val) 6711060SN/A { 6722731Sktlim@umich.edu setVecElemResult(val); 6731060SN/A } 6741060SN/A 6752731Sktlim@umich.edu /** Records that one of the source registers is ready. */ 6761060SN/A void markSrcRegReady(); 6771061SN/A 6782731Sktlim@umich.edu /** Marks a specific register as ready. */ 6791061SN/A void markSrcRegReady(RegIndex src_idx); 6801060SN/A 6812731Sktlim@umich.edu /** Returns if a source register is ready. */ 6822731Sktlim@umich.edu bool isReadySrcRegIdx(int idx) const 6832731Sktlim@umich.edu { 6842731Sktlim@umich.edu return this->_readySrcRegIdx[idx]; 6852731Sktlim@umich.edu } 6861060SN/A 6872292SN/A /** Sets this instruction as completed. */ 6882731Sktlim@umich.edu void setCompleted() { status.set(Completed); } 6892292SN/A 6902292SN/A /** Returns whether or not this instruction is completed. */ 6912731Sktlim@umich.edu bool isCompleted() const { return status[Completed]; } 6922292SN/A 6931060SN/A /** Marks the result as ready. */ 6942731Sktlim@umich.edu void setResultReady() { status.set(ResultReady); } 6951060SN/A 6961060SN/A /** Returns whether or not the result is ready. */ 6972731Sktlim@umich.edu bool isResultReady() const { return status[ResultReady]; } 6981060SN/A 6992292SN/A /** Sets this instruction as ready to issue. */ 7002292SN/A void setCanIssue() { status.set(CanIssue); } 7012292SN/A 7022731Sktlim@umich.edu /** Returns whether or not this instruction is ready to issue. */ 7032292SN/A bool readyToIssue() const { return status[CanIssue]; } 7042292SN/A 7052731Sktlim@umich.edu /** Clears this instruction being able to issue. */ 7062731Sktlim@umich.edu void clearCanIssue() { status.reset(CanIssue); } 7072731Sktlim@umich.edu 7082731Sktlim@umich.edu /** Sets this instruction as issued from the IQ. */ 7092292SN/A void setIssued() { status.set(Issued); } 7101060SN/A 7112731Sktlim@umich.edu /** Returns whether or not this instruction has issued. */ 7121060SN/A bool isIssued() const { return status[Issued]; } 7131060SN/A 7142731Sktlim@umich.edu /** Clears this instruction as being issued. */ 7152292SN/A void clearIssued() { status.reset(Issued); } 7162292SN/A 7172292SN/A /** Sets this instruction as executed. */ 7182292SN/A void setExecuted() { status.set(Executed); } 7192292SN/A 7202731Sktlim@umich.edu /** Returns whether or not this instruction has executed. */ 7212292SN/A bool isExecuted() const { return status[Executed]; } 7222292SN/A 7232731Sktlim@umich.edu /** Sets this instruction as ready to commit. */ 7242731Sktlim@umich.edu void setCanCommit() { status.set(CanCommit); } 7252731Sktlim@umich.edu 7262731Sktlim@umich.edu /** Clears this instruction as being ready to commit. */ 7272292SN/A void clearCanCommit() { status.reset(CanCommit); } 7282292SN/A 7292731Sktlim@umich.edu /** Returns whether or not this instruction is ready to commit. */ 7302292SN/A bool readyToCommit() const { return status[CanCommit]; } 7312292SN/A 7322731Sktlim@umich.edu void setAtCommit() { status.set(AtCommit); } 7332292SN/A 7342292SN/A bool isAtCommit() { return status[AtCommit]; } 7352292SN/A 7362292SN/A /** Sets this instruction as committed. */ 7372292SN/A void setCommitted() { status.set(Committed); } 7382731Sktlim@umich.edu 7392292SN/A /** Returns whether or not this instruction is committed. */ 7402292SN/A bool isCommitted() const { return status[Committed]; } 7412731Sktlim@umich.edu 7422731Sktlim@umich.edu /** Sets this instruction as squashed. */ 7432731Sktlim@umich.edu void setSquashed() { status.set(Squashed); } 7442731Sktlim@umich.edu 7452292SN/A /** Returns whether or not this instruction is squashed. */ 7462292SN/A bool isSquashed() const { return status[Squashed]; } 7472731Sktlim@umich.edu 7482292SN/A //Instruction Queue Entry 7492292SN/A //----------------------- 7502731Sktlim@umich.edu /** Sets this instruction as a entry the IQ. */ 7512292SN/A void setInIQ() { status.set(IqEntry); } 7521060SN/A 7531464SN/A /** Sets this instruction as a entry the IQ. */ 7541060SN/A void clearInIQ() { status.reset(IqEntry); } 7554636Sgblack@eecs.umich.edu 7564636Sgblack@eecs.umich.edu /** Returns whether or not this instruction has issued. */ 7574636Sgblack@eecs.umich.edu bool isInIQ() const { return status[IqEntry]; } 7581060SN/A 7594636Sgblack@eecs.umich.edu /** Sets this instruction as squashed in the IQ. */ 7602308SN/A void setSquashedInIQ() { status.set(SquashedInIQ); status.set(Squashed);} 7612308SN/A 7622308SN/A /** Returns whether or not this instruction is squashed in the IQ. */ 7632190SN/A bool isSquashedInIQ() const { return status[SquashedInIQ]; } 7642935Sksewell@umich.edu 7654636Sgblack@eecs.umich.edu 7662935Sksewell@umich.edu //Load / Store Queue Functions 7674632Sgblack@eecs.umich.edu //----------------------- 7682935Sksewell@umich.edu /** Sets this instruction as a entry the LSQ. */ 7694632Sgblack@eecs.umich.edu void setInLSQ() { status.set(LsqEntry); } 7702935Sksewell@umich.edu 7712935Sksewell@umich.edu /** Sets this instruction as a entry the LSQ. */ 7724636Sgblack@eecs.umich.edu void removeInLSQ() { status.reset(LsqEntry); } 7734636Sgblack@eecs.umich.edu 7744636Sgblack@eecs.umich.edu /** Returns whether or not this instruction is in the LSQ. */ 7754636Sgblack@eecs.umich.edu bool isInLSQ() const { return status[LsqEntry]; } 7764636Sgblack@eecs.umich.edu 7772702Sktlim@umich.edu /** Sets this instruction as squashed in the LSQ. */ 7782292SN/A void setSquashedInLSQ() { status.set(SquashedInLSQ);} 7792292SN/A 7802702Sktlim@umich.edu /** Returns whether or not this instruction is squashed in the LSQ. */ 7816221Snate@binkert.org bool isSquashedInLSQ() const { return status[SquashedInLSQ]; } 7822292SN/A 7832731Sktlim@umich.edu 7842702Sktlim@umich.edu //Reorder Buffer Functions 7851060SN/A //----------------------- 7862731Sktlim@umich.edu /** Sets this instruction as a entry the ROB. */ 7872680Sktlim@umich.edu void setInROB() { status.set(RobEntry); } 7881464SN/A 7891464SN/A /** Sets this instruction as a entry the ROB. */ 7901684SN/A void clearInROB() { status.reset(RobEntry); } 7911684SN/A 7921684SN/A /** Returns whether or not this instruction is in the ROB. */ 7931464SN/A bool isInROB() const { return status[RobEntry]; } 7942292SN/A 7951684SN/A /** Sets this instruction as squashed in the ROB. */ 7961684SN/A void setSquashedInROB() { status.set(SquashedInROB); } 7971684SN/A 7981464SN/A /** Returns whether or not this instruction is squashed in the ROB. */ 7991464SN/A bool isSquashedInROB() const { return status[SquashedInROB]; } 8004032Sktlim@umich.edu 8014032Sktlim@umich.edu /** Read the PC state of this instruction. */ 8024032Sktlim@umich.edu TheISA::PCState pcState() const { return pc; } 8034032Sktlim@umich.edu 8044032Sktlim@umich.edu /** Set the PC state of this instruction. */ 8054032Sktlim@umich.edu void pcState(const TheISA::PCState &val) { pc = val; } 8061464SN/A 8071684SN/A /** Read the PC of this instruction. */ 8081464SN/A Addr instAddr() const { return pc.instAddr(); } 8091684SN/A 8101684SN/A /** Read the PC of the next instruction. */ 8111464SN/A Addr nextInstAddr() const { return pc.nextInstAddr(); } 8121684SN/A 8131684SN/A /**Read the micro PC of this instruction. */ 8141464SN/A Addr microPC() const { return pc.microPC(); } 8151684SN/A 8161684SN/A bool readPredicate() const 8171464SN/A { 8181681SN/A return instFlags[Predicate]; 8192292SN/A } 8202292SN/A 8212292SN/A void setPredicate(bool val) 8224032Sktlim@umich.edu { 8234032Sktlim@umich.edu instFlags[Predicate] = val; 8244032Sktlim@umich.edu 8254032Sktlim@umich.edu if (traceData) { 8264032Sktlim@umich.edu traceData->setPredicate(val); 8274032Sktlim@umich.edu } 8281681SN/A } 8291684SN/A 8301681SN/A /** Sets the ASID. */ 8311684SN/A void setASID(short addr_space_id) { asid = addr_space_id; } 8321684SN/A short getASID() { return asid; } 8331681SN/A 8342292SN/A /** Sets the thread id. */ 8352292SN/A void setTid(ThreadID tid) { threadNumber = tid; } 8362292SN/A 8372292SN/A /** Sets the pointer to the thread state. */ 8382292SN/A void setThreadState(ImplState *state) { thread = state; } 8392292SN/A 8402292SN/A /** Returns the thread context. */ 8412292SN/A ThreadContext *tcBase() { return thread->getTC(); } 8422292SN/A 8433326Sktlim@umich.edu public: 8443326Sktlim@umich.edu /** Returns whether or not the eff. addr. source registers are ready. */ 8453326Sktlim@umich.edu bool eaSrcsReady() const; 8463326Sktlim@umich.edu 8473326Sktlim@umich.edu /** Is this instruction's memory access strictly ordered? */ 8483326Sktlim@umich.edu bool strictlyOrdered() const { return instFlags[IsStrictlyOrdered]; } 8493326Sktlim@umich.edu void strictlyOrdered(bool so) { instFlags[IsStrictlyOrdered] = so; } 8503326Sktlim@umich.edu 8513326Sktlim@umich.edu /** Has this instruction generated a memory request. */ 8521060SN/A bool hasRequest() const { return instFlags[ReqMade]; } 8531060SN/A /** Assert this instruction has generated a memory request. */ 8541060SN/A void setRequest() { instFlags[ReqMade] = true; } 8551060SN/A 8562132SN/A /** Returns iterator to this instruction in the list of all insts. */ 8571060SN/A ListIt &getInstListIt() { return instListIt; } 8581060SN/A 8594032Sktlim@umich.edu /** Sets iterator for this instruction in the list of all insts. */ 8606429Ssteve.reinhardt@amd.com void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; } 8616429Ssteve.reinhardt@amd.com 8622292SN/A public: 8636023Snate@binkert.org /** Returns the number of consecutive store conditional failures. */ 8641060SN/A unsigned int readStCondFailures() const 8654032Sktlim@umich.edu { return thread->storeCondFailures; } 8664032Sktlim@umich.edu 8674032Sktlim@umich.edu /** Sets the number of consecutive store conditional failures. */ 8682678Sktlim@umich.edu void setStCondFailures(unsigned int sc_failures) 8692678Sktlim@umich.edu { thread->storeCondFailures = sc_failures; } 8704032Sktlim@umich.edu 8712678Sktlim@umich.edu public: 8722678Sktlim@umich.edu // monitor/mwait funtions 8731060SN/A void armMonitor(Addr address) { cpu->armMonitor(threadNumber, address); } 8742690Sktlim@umich.edu bool mwait(PacketPtr pkt) { return cpu->mwait(threadNumber, pkt); } 8752292SN/A void mwaitAtomic(ThreadContext *tc) 8762292SN/A { return cpu->mwaitAtomic(threadNumber, tc, cpu->dtb); } 8772292SN/A AddressMonitor *getAddrMonitor() 8782292SN/A { return cpu->getCpuAddrMonitor(threadNumber); } 8792292SN/A}; 8802292SN/A 8812292SN/Atemplate<class Impl> 8822292SN/AFault 8831681SN/ABaseDynInst<Impl>::initiateMemRead(Addr addr, unsigned size, 8842632Sstever@eecs.umich.edu Request::Flags flags) 8851684SN/A{ 8861060SN/A return cpu->pushRequest( 8871060SN/A dynamic_cast<typename DynInstPtr::PtrType>(this), 8881060SN/A /* ld */ true, nullptr, size, addr, flags, nullptr); 8892292SN/A} 8902292SN/A 8912292SN/Atemplate<class Impl> 8922292SN/AFault 8934032Sktlim@umich.eduBaseDynInst<Impl>::writeMem(uint8_t *data, unsigned size, Addr addr, 8941060SN/A Request::Flags flags, uint64_t *res) 8951060SN/A{ 8961060SN/A return cpu->pushRequest( 8971060SN/A dynamic_cast<typename DynInstPtr::PtrType>(this), 8981060SN/A /* st */ false, data, size, addr, flags, res); 8991060SN/A} 9001060SN/A 9011060SN/A#endif // __CPU_BASE_DYN_INST_HH__ 9021060SN/A