base_dyn_inst.hh revision 12107:998b4c54ee51
1/* 2 * Copyright (c) 2011,2013,2016 ARM Limited 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved. 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating 9 * to a hardware implementation of the functionality of the software 10 * licensed hereunder. You may use the software subject to the license 11 * terms below provided that you ensure that this notice is replicated 12 * unmodified and in its entirety in all distributions of the software, 13 * modified or unmodified, in source code or in binary form. 14 * 15 * Copyright (c) 2004-2006 The Regents of The University of Michigan 16 * Copyright (c) 2009 The University of Edinburgh 17 * All rights reserved. 18 * 19 * Redistribution and use in source and binary forms, with or without 20 * modification, are permitted provided that the following conditions are 21 * met: redistributions of source code must retain the above copyright 22 * notice, this list of conditions and the following disclaimer; 23 * redistributions in binary form must reproduce the above copyright 24 * notice, this list of conditions and the following disclaimer in the 25 * documentation and/or other materials provided with the distribution; 26 * neither the name of the copyright holders nor the names of its 27 * contributors may be used to endorse or promote products derived from 28 * this software without specific prior written permission. 29 * 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 34 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 35 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 36 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 37 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 38 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 39 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 40 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 41 * 42 * Authors: Kevin Lim 43 * Timothy M. Jones 44 */ 45 46#ifndef __CPU_BASE_DYN_INST_HH__ 47#define __CPU_BASE_DYN_INST_HH__ 48 49#include <array> 50#include <bitset> 51#include <list> 52#include <queue> 53#include <string> 54 55#include "arch/generic/tlb.hh" 56#include "arch/utility.hh" 57#include "base/trace.hh" 58#include "config/the_isa.hh" 59#include "cpu/checker/cpu.hh" 60#include "cpu/exec_context.hh" 61#include "cpu/exetrace.hh" 62#include "cpu/inst_res.hh" 63#include "cpu/inst_seq.hh" 64#include "cpu/o3/comm.hh" 65#include "cpu/op_class.hh" 66#include "cpu/static_inst.hh" 67#include "cpu/translation.hh" 68#include "mem/packet.hh" 69#include "mem/request.hh" 70#include "sim/byteswap.hh" 71#include "sim/system.hh" 72 73/** 74 * @file 75 * Defines a dynamic instruction context. 76 */ 77 78template <class Impl> 79class BaseDynInst : public ExecContext, public RefCounted 80{ 81 public: 82 // Typedef for the CPU. 83 typedef typename Impl::CPUType ImplCPU; 84 typedef typename ImplCPU::ImplState ImplState; 85 86 // The DynInstPtr type. 87 typedef typename Impl::DynInstPtr DynInstPtr; 88 typedef RefCountingPtr<BaseDynInst<Impl> > BaseDynInstPtr; 89 90 // The list of instructions iterator type. 91 typedef typename std::list<DynInstPtr>::iterator ListIt; 92 93 enum { 94 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, /// Max source regs 95 MaxInstDestRegs = TheISA::MaxInstDestRegs /// Max dest regs 96 }; 97 98 protected: 99 enum Status { 100 IqEntry, /// Instruction is in the IQ 101 RobEntry, /// Instruction is in the ROB 102 LsqEntry, /// Instruction is in the LSQ 103 Completed, /// Instruction has completed 104 ResultReady, /// Instruction has its result 105 CanIssue, /// Instruction can issue and execute 106 Issued, /// Instruction has issued 107 Executed, /// Instruction has executed 108 CanCommit, /// Instruction can commit 109 AtCommit, /// Instruction has reached commit 110 Committed, /// Instruction has committed 111 Squashed, /// Instruction is squashed 112 SquashedInIQ, /// Instruction is squashed in the IQ 113 SquashedInLSQ, /// Instruction is squashed in the LSQ 114 SquashedInROB, /// Instruction is squashed in the ROB 115 RecoverInst, /// Is a recover instruction 116 BlockingInst, /// Is a blocking instruction 117 ThreadsyncWait, /// Is a thread synchronization instruction 118 SerializeBefore, /// Needs to serialize on 119 /// instructions ahead of it 120 SerializeAfter, /// Needs to serialize instructions behind it 121 SerializeHandled, /// Serialization has been handled 122 NumStatus 123 }; 124 125 enum Flags { 126 TranslationStarted, 127 TranslationCompleted, 128 PossibleLoadViolation, 129 HitExternalSnoop, 130 EffAddrValid, 131 RecordResult, 132 Predicate, 133 PredTaken, 134 /** Whether or not the effective address calculation is completed. 135 * @todo: Consider if this is necessary or not. 136 */ 137 EACalcDone, 138 IsStrictlyOrdered, 139 ReqMade, 140 MemOpDone, 141 MaxFlags 142 }; 143 144 public: 145 /** The sequence number of the instruction. */ 146 InstSeqNum seqNum; 147 148 /** The StaticInst used by this BaseDynInst. */ 149 const StaticInstPtr staticInst; 150 151 /** Pointer to the Impl's CPU object. */ 152 ImplCPU *cpu; 153 154 BaseCPU *getCpuPtr() { return cpu; } 155 156 /** Pointer to the thread state. */ 157 ImplState *thread; 158 159 /** The kind of fault this instruction has generated. */ 160 Fault fault; 161 162 /** InstRecord that tracks this instructions. */ 163 Trace::InstRecord *traceData; 164 165 protected: 166 /** The result of the instruction; assumes an instruction can have many 167 * destination registers. 168 */ 169 std::queue<InstResult> instResult; 170 171 /** PC state for this instruction. */ 172 TheISA::PCState pc; 173 174 /* An amalgamation of a lot of boolean values into one */ 175 std::bitset<MaxFlags> instFlags; 176 177 /** The status of this BaseDynInst. Several bits can be set. */ 178 std::bitset<NumStatus> status; 179 180 /** Whether or not the source register is ready. 181 * @todo: Not sure this should be here vs the derived class. 182 */ 183 std::bitset<MaxInstSrcRegs> _readySrcRegIdx; 184 185 public: 186 /** The thread this instruction is from. */ 187 ThreadID threadNumber; 188 189 /** Iterator pointing to this BaseDynInst in the list of all insts. */ 190 ListIt instListIt; 191 192 ////////////////////// Branch Data /////////////// 193 /** Predicted PC state after this instruction. */ 194 TheISA::PCState predPC; 195 196 /** The Macroop if one exists */ 197 const StaticInstPtr macroop; 198 199 /** How many source registers are ready. */ 200 uint8_t readyRegs; 201 202 public: 203 /////////////////////// Load Store Data ////////////////////// 204 /** The effective virtual address (lds & stores only). */ 205 Addr effAddr; 206 207 /** The effective physical address. */ 208 Addr physEffAddrLow; 209 210 /** The effective physical address 211 * of the second request for a split request 212 */ 213 Addr physEffAddrHigh; 214 215 /** The memory request flags (from translation). */ 216 unsigned memReqFlags; 217 218 /** data address space ID, for loads & stores. */ 219 short asid; 220 221 /** The size of the request */ 222 uint8_t effSize; 223 224 /** Pointer to the data for the memory access. */ 225 uint8_t *memData; 226 227 /** Load queue index. */ 228 int16_t lqIdx; 229 230 /** Store queue index. */ 231 int16_t sqIdx; 232 233 234 /////////////////////// TLB Miss ////////////////////// 235 /** 236 * Saved memory requests (needed when the DTB address translation is 237 * delayed due to a hw page table walk). 238 */ 239 RequestPtr savedReq; 240 RequestPtr savedSreqLow; 241 RequestPtr savedSreqHigh; 242 243 /////////////////////// Checker ////////////////////// 244 // Need a copy of main request pointer to verify on writes. 245 RequestPtr reqToVerify; 246 247 private: 248 /** Instruction effective address. 249 * @todo: Consider if this is necessary or not. 250 */ 251 Addr instEffAddr; 252 253 protected: 254 /** Flattened register index of the destination registers of this 255 * instruction. 256 */ 257 std::array<RegId, TheISA::MaxInstDestRegs> _flatDestRegIdx; 258 259 /** Physical register index of the destination registers of this 260 * instruction. 261 */ 262 std::array<PhysRegIdPtr, TheISA::MaxInstDestRegs> _destRegIdx; 263 264 /** Physical register index of the source registers of this 265 * instruction. 266 */ 267 std::array<PhysRegIdPtr, TheISA::MaxInstSrcRegs> _srcRegIdx; 268 269 /** Physical register index of the previous producers of the 270 * architected destinations. 271 */ 272 std::array<PhysRegIdPtr, TheISA::MaxInstDestRegs> _prevDestRegIdx; 273 274 275 public: 276 /** Records changes to result? */ 277 void recordResult(bool f) { instFlags[RecordResult] = f; } 278 279 /** Is the effective virtual address valid. */ 280 bool effAddrValid() const { return instFlags[EffAddrValid]; } 281 282 /** Whether or not the memory operation is done. */ 283 bool memOpDone() const { return instFlags[MemOpDone]; } 284 void memOpDone(bool f) { instFlags[MemOpDone] = f; } 285 286 287 //////////////////////////////////////////// 288 // 289 // INSTRUCTION EXECUTION 290 // 291 //////////////////////////////////////////// 292 293 void demapPage(Addr vaddr, uint64_t asn) 294 { 295 cpu->demapPage(vaddr, asn); 296 } 297 void demapInstPage(Addr vaddr, uint64_t asn) 298 { 299 cpu->demapPage(vaddr, asn); 300 } 301 void demapDataPage(Addr vaddr, uint64_t asn) 302 { 303 cpu->demapPage(vaddr, asn); 304 } 305 306 Fault initiateMemRead(Addr addr, unsigned size, Request::Flags flags); 307 308 Fault writeMem(uint8_t *data, unsigned size, Addr addr, 309 Request::Flags flags, uint64_t *res); 310 311 /** Splits a request in two if it crosses a dcache block. */ 312 void splitRequest(RequestPtr req, RequestPtr &sreqLow, 313 RequestPtr &sreqHigh); 314 315 /** Initiate a DTB address translation. */ 316 void initiateTranslation(RequestPtr req, RequestPtr sreqLow, 317 RequestPtr sreqHigh, uint64_t *res, 318 BaseTLB::Mode mode); 319 320 /** Finish a DTB address translation. */ 321 void finishTranslation(WholeTranslationState *state); 322 323 /** True if the DTB address translation has started. */ 324 bool translationStarted() const { return instFlags[TranslationStarted]; } 325 void translationStarted(bool f) { instFlags[TranslationStarted] = f; } 326 327 /** True if the DTB address translation has completed. */ 328 bool translationCompleted() const { return instFlags[TranslationCompleted]; } 329 void translationCompleted(bool f) { instFlags[TranslationCompleted] = f; } 330 331 /** True if this address was found to match a previous load and they issued 332 * out of order. If that happend, then it's only a problem if an incoming 333 * snoop invalidate modifies the line, in which case we need to squash. 334 * If nothing modified the line the order doesn't matter. 335 */ 336 bool possibleLoadViolation() const { return instFlags[PossibleLoadViolation]; } 337 void possibleLoadViolation(bool f) { instFlags[PossibleLoadViolation] = f; } 338 339 /** True if the address hit a external snoop while sitting in the LSQ. 340 * If this is true and a older instruction sees it, this instruction must 341 * reexecute 342 */ 343 bool hitExternalSnoop() const { return instFlags[HitExternalSnoop]; } 344 void hitExternalSnoop(bool f) { instFlags[HitExternalSnoop] = f; } 345 346 /** 347 * Returns true if the DTB address translation is being delayed due to a hw 348 * page table walk. 349 */ 350 bool isTranslationDelayed() const 351 { 352 return (translationStarted() && !translationCompleted()); 353 } 354 355 public: 356#ifdef DEBUG 357 void dumpSNList(); 358#endif 359 360 /** Returns the physical register index of the i'th destination 361 * register. 362 */ 363 PhysRegIdPtr renamedDestRegIdx(int idx) const 364 { 365 return _destRegIdx[idx]; 366 } 367 368 /** Returns the physical register index of the i'th source register. */ 369 PhysRegIdPtr renamedSrcRegIdx(int idx) const 370 { 371 assert(TheISA::MaxInstSrcRegs > idx); 372 return _srcRegIdx[idx]; 373 } 374 375 /** Returns the flattened register index of the i'th destination 376 * register. 377 */ 378 const RegId& flattenedDestRegIdx(int idx) const 379 { 380 return _flatDestRegIdx[idx]; 381 } 382 383 /** Returns the physical register index of the previous physical register 384 * that remapped to the same logical register index. 385 */ 386 PhysRegIdPtr prevDestRegIdx(int idx) const 387 { 388 return _prevDestRegIdx[idx]; 389 } 390 391 /** Renames a destination register to a physical register. Also records 392 * the previous physical register that the logical register mapped to. 393 */ 394 void renameDestReg(int idx, 395 PhysRegIdPtr renamed_dest, 396 PhysRegIdPtr previous_rename) 397 { 398 _destRegIdx[idx] = renamed_dest; 399 _prevDestRegIdx[idx] = previous_rename; 400 } 401 402 /** Renames a source logical register to the physical register which 403 * has/will produce that logical register's result. 404 * @todo: add in whether or not the source register is ready. 405 */ 406 void renameSrcReg(int idx, PhysRegIdPtr renamed_src) 407 { 408 _srcRegIdx[idx] = renamed_src; 409 } 410 411 /** Flattens a destination architectural register index into a logical 412 * index. 413 */ 414 void flattenDestReg(int idx, const RegId& flattened_dest) 415 { 416 _flatDestRegIdx[idx] = flattened_dest; 417 } 418 /** BaseDynInst constructor given a binary instruction. 419 * @param staticInst A StaticInstPtr to the underlying instruction. 420 * @param pc The PC state for the instruction. 421 * @param predPC The predicted next PC state for the instruction. 422 * @param seq_num The sequence number of the instruction. 423 * @param cpu Pointer to the instruction's CPU. 424 */ 425 BaseDynInst(const StaticInstPtr &staticInst, const StaticInstPtr ¯oop, 426 TheISA::PCState pc, TheISA::PCState predPC, 427 InstSeqNum seq_num, ImplCPU *cpu); 428 429 /** BaseDynInst constructor given a StaticInst pointer. 430 * @param _staticInst The StaticInst for this BaseDynInst. 431 */ 432 BaseDynInst(const StaticInstPtr &staticInst, const StaticInstPtr ¯oop); 433 434 /** BaseDynInst destructor. */ 435 ~BaseDynInst(); 436 437 private: 438 /** Function to initialize variables in the constructors. */ 439 void initVars(); 440 441 public: 442 /** Dumps out contents of this BaseDynInst. */ 443 void dump(); 444 445 /** Dumps out contents of this BaseDynInst into given string. */ 446 void dump(std::string &outstring); 447 448 /** Read this CPU's ID. */ 449 int cpuId() const { return cpu->cpuId(); } 450 451 /** Read this CPU's Socket ID. */ 452 uint32_t socketId() const { return cpu->socketId(); } 453 454 /** Read this CPU's data requestor ID */ 455 MasterID masterId() const { return cpu->dataMasterId(); } 456 457 /** Read this context's system-wide ID **/ 458 ContextID contextId() const { return thread->contextId(); } 459 460 /** Returns the fault type. */ 461 Fault getFault() const { return fault; } 462 463 /** Checks whether or not this instruction has had its branch target 464 * calculated yet. For now it is not utilized and is hacked to be 465 * always false. 466 * @todo: Actually use this instruction. 467 */ 468 bool doneTargCalc() { return false; } 469 470 /** Set the predicted target of this current instruction. */ 471 void setPredTarg(const TheISA::PCState &_predPC) 472 { 473 predPC = _predPC; 474 } 475 476 const TheISA::PCState &readPredTarg() { return predPC; } 477 478 /** Returns the predicted PC immediately after the branch. */ 479 Addr predInstAddr() { return predPC.instAddr(); } 480 481 /** Returns the predicted PC two instructions after the branch */ 482 Addr predNextInstAddr() { return predPC.nextInstAddr(); } 483 484 /** Returns the predicted micro PC after the branch */ 485 Addr predMicroPC() { return predPC.microPC(); } 486 487 /** Returns whether the instruction was predicted taken or not. */ 488 bool readPredTaken() 489 { 490 return instFlags[PredTaken]; 491 } 492 493 void setPredTaken(bool predicted_taken) 494 { 495 instFlags[PredTaken] = predicted_taken; 496 } 497 498 /** Returns whether the instruction mispredicted. */ 499 bool mispredicted() 500 { 501 TheISA::PCState tempPC = pc; 502 TheISA::advancePC(tempPC, staticInst); 503 return !(tempPC == predPC); 504 } 505 506 // 507 // Instruction types. Forward checks to StaticInst object. 508 // 509 bool isNop() const { return staticInst->isNop(); } 510 bool isMemRef() const { return staticInst->isMemRef(); } 511 bool isLoad() const { return staticInst->isLoad(); } 512 bool isStore() const { return staticInst->isStore(); } 513 bool isStoreConditional() const 514 { return staticInst->isStoreConditional(); } 515 bool isInstPrefetch() const { return staticInst->isInstPrefetch(); } 516 bool isDataPrefetch() const { return staticInst->isDataPrefetch(); } 517 bool isInteger() const { return staticInst->isInteger(); } 518 bool isFloating() const { return staticInst->isFloating(); } 519 bool isControl() const { return staticInst->isControl(); } 520 bool isCall() const { return staticInst->isCall(); } 521 bool isReturn() const { return staticInst->isReturn(); } 522 bool isDirectCtrl() const { return staticInst->isDirectCtrl(); } 523 bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); } 524 bool isCondCtrl() const { return staticInst->isCondCtrl(); } 525 bool isUncondCtrl() const { return staticInst->isUncondCtrl(); } 526 bool isCondDelaySlot() const { return staticInst->isCondDelaySlot(); } 527 bool isThreadSync() const { return staticInst->isThreadSync(); } 528 bool isSerializing() const { return staticInst->isSerializing(); } 529 bool isSerializeBefore() const 530 { return staticInst->isSerializeBefore() || status[SerializeBefore]; } 531 bool isSerializeAfter() const 532 { return staticInst->isSerializeAfter() || status[SerializeAfter]; } 533 bool isSquashAfter() const { return staticInst->isSquashAfter(); } 534 bool isMemBarrier() const { return staticInst->isMemBarrier(); } 535 bool isWriteBarrier() const { return staticInst->isWriteBarrier(); } 536 bool isNonSpeculative() const { return staticInst->isNonSpeculative(); } 537 bool isQuiesce() const { return staticInst->isQuiesce(); } 538 bool isIprAccess() const { return staticInst->isIprAccess(); } 539 bool isUnverifiable() const { return staticInst->isUnverifiable(); } 540 bool isSyscall() const { return staticInst->isSyscall(); } 541 bool isMacroop() const { return staticInst->isMacroop(); } 542 bool isMicroop() const { return staticInst->isMicroop(); } 543 bool isDelayedCommit() const { return staticInst->isDelayedCommit(); } 544 bool isLastMicroop() const { return staticInst->isLastMicroop(); } 545 bool isFirstMicroop() const { return staticInst->isFirstMicroop(); } 546 bool isMicroBranch() const { return staticInst->isMicroBranch(); } 547 548 /** Temporarily sets this instruction as a serialize before instruction. */ 549 void setSerializeBefore() { status.set(SerializeBefore); } 550 551 /** Clears the serializeBefore part of this instruction. */ 552 void clearSerializeBefore() { status.reset(SerializeBefore); } 553 554 /** Checks if this serializeBefore is only temporarily set. */ 555 bool isTempSerializeBefore() { return status[SerializeBefore]; } 556 557 /** Temporarily sets this instruction as a serialize after instruction. */ 558 void setSerializeAfter() { status.set(SerializeAfter); } 559 560 /** Clears the serializeAfter part of this instruction.*/ 561 void clearSerializeAfter() { status.reset(SerializeAfter); } 562 563 /** Checks if this serializeAfter is only temporarily set. */ 564 bool isTempSerializeAfter() { return status[SerializeAfter]; } 565 566 /** Sets the serialization part of this instruction as handled. */ 567 void setSerializeHandled() { status.set(SerializeHandled); } 568 569 /** Checks if the serialization part of this instruction has been 570 * handled. This does not apply to the temporary serializing 571 * state; it only applies to this instruction's own permanent 572 * serializing state. 573 */ 574 bool isSerializeHandled() { return status[SerializeHandled]; } 575 576 /** Returns the opclass of this instruction. */ 577 OpClass opClass() const { return staticInst->opClass(); } 578 579 /** Returns the branch target address. */ 580 TheISA::PCState branchTarget() const 581 { return staticInst->branchTarget(pc); } 582 583 /** Returns the number of source registers. */ 584 int8_t numSrcRegs() const { return staticInst->numSrcRegs(); } 585 586 /** Returns the number of destination registers. */ 587 int8_t numDestRegs() const { return staticInst->numDestRegs(); } 588 589 // the following are used to track physical register usage 590 // for machines with separate int & FP reg files 591 int8_t numFPDestRegs() const { return staticInst->numFPDestRegs(); } 592 int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); } 593 int8_t numCCDestRegs() const { return staticInst->numCCDestRegs(); } 594 595 /** Returns the logical register index of the i'th destination register. */ 596 const RegId& destRegIdx(int i) const { return staticInst->destRegIdx(i); } 597 598 /** Returns the logical register index of the i'th source register. */ 599 const RegId& srcRegIdx(int i) const { return staticInst->srcRegIdx(i); } 600 601 /** Return the size of the instResult queue. */ 602 uint8_t resultSize() { return instResult.size(); } 603 604 /** Pops a result off the instResult queue. 605 * If the result stack is empty, return the default value. 606 * */ 607 InstResult popResult(InstResult dflt = InstResult()) 608 { 609 if (!instResult.empty()) { 610 InstResult t = instResult.front(); 611 instResult.pop(); 612 return t; 613 } 614 return dflt; 615 } 616 617 /** Pushes a result onto the instResult queue. */ 618 template<typename T> 619 void setScalarResult(T&& t) 620 { 621 if (instFlags[RecordResult]) { 622 instResult.push(InstResult(std::forward<T>(t), 623 InstResult::ResultType::Scalar)); 624 } 625 } 626 627 /** Records an integer register being set to a value. */ 628 void setIntRegOperand(const StaticInst *si, int idx, IntReg val) 629 { 630 setScalarResult(val); 631 } 632 633 /** Records a CC register being set to a value. */ 634 void setCCRegOperand(const StaticInst *si, int idx, CCReg val) 635 { 636 setScalarResult(val); 637 } 638 639 /** Records an fp register being set to a value. */ 640 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val) 641 { 642 setScalarResult(val); 643 } 644 645 /** Records an fp register being set to an integer value. */ 646 void 647 setFloatRegOperandBits(const StaticInst *si, int idx, FloatRegBits val) 648 { 649 setScalarResult(val); 650 } 651 652 /** Records that one of the source registers is ready. */ 653 void markSrcRegReady(); 654 655 /** Marks a specific register as ready. */ 656 void markSrcRegReady(RegIndex src_idx); 657 658 /** Returns if a source register is ready. */ 659 bool isReadySrcRegIdx(int idx) const 660 { 661 return this->_readySrcRegIdx[idx]; 662 } 663 664 /** Sets this instruction as completed. */ 665 void setCompleted() { status.set(Completed); } 666 667 /** Returns whether or not this instruction is completed. */ 668 bool isCompleted() const { return status[Completed]; } 669 670 /** Marks the result as ready. */ 671 void setResultReady() { status.set(ResultReady); } 672 673 /** Returns whether or not the result is ready. */ 674 bool isResultReady() const { return status[ResultReady]; } 675 676 /** Sets this instruction as ready to issue. */ 677 void setCanIssue() { status.set(CanIssue); } 678 679 /** Returns whether or not this instruction is ready to issue. */ 680 bool readyToIssue() const { return status[CanIssue]; } 681 682 /** Clears this instruction being able to issue. */ 683 void clearCanIssue() { status.reset(CanIssue); } 684 685 /** Sets this instruction as issued from the IQ. */ 686 void setIssued() { status.set(Issued); } 687 688 /** Returns whether or not this instruction has issued. */ 689 bool isIssued() const { return status[Issued]; } 690 691 /** Clears this instruction as being issued. */ 692 void clearIssued() { status.reset(Issued); } 693 694 /** Sets this instruction as executed. */ 695 void setExecuted() { status.set(Executed); } 696 697 /** Returns whether or not this instruction has executed. */ 698 bool isExecuted() const { return status[Executed]; } 699 700 /** Sets this instruction as ready to commit. */ 701 void setCanCommit() { status.set(CanCommit); } 702 703 /** Clears this instruction as being ready to commit. */ 704 void clearCanCommit() { status.reset(CanCommit); } 705 706 /** Returns whether or not this instruction is ready to commit. */ 707 bool readyToCommit() const { return status[CanCommit]; } 708 709 void setAtCommit() { status.set(AtCommit); } 710 711 bool isAtCommit() { return status[AtCommit]; } 712 713 /** Sets this instruction as committed. */ 714 void setCommitted() { status.set(Committed); } 715 716 /** Returns whether or not this instruction is committed. */ 717 bool isCommitted() const { return status[Committed]; } 718 719 /** Sets this instruction as squashed. */ 720 void setSquashed() { status.set(Squashed); } 721 722 /** Returns whether or not this instruction is squashed. */ 723 bool isSquashed() const { return status[Squashed]; } 724 725 //Instruction Queue Entry 726 //----------------------- 727 /** Sets this instruction as a entry the IQ. */ 728 void setInIQ() { status.set(IqEntry); } 729 730 /** Sets this instruction as a entry the IQ. */ 731 void clearInIQ() { status.reset(IqEntry); } 732 733 /** Returns whether or not this instruction has issued. */ 734 bool isInIQ() const { return status[IqEntry]; } 735 736 /** Sets this instruction as squashed in the IQ. */ 737 void setSquashedInIQ() { status.set(SquashedInIQ); status.set(Squashed);} 738 739 /** Returns whether or not this instruction is squashed in the IQ. */ 740 bool isSquashedInIQ() const { return status[SquashedInIQ]; } 741 742 743 //Load / Store Queue Functions 744 //----------------------- 745 /** Sets this instruction as a entry the LSQ. */ 746 void setInLSQ() { status.set(LsqEntry); } 747 748 /** Sets this instruction as a entry the LSQ. */ 749 void removeInLSQ() { status.reset(LsqEntry); } 750 751 /** Returns whether or not this instruction is in the LSQ. */ 752 bool isInLSQ() const { return status[LsqEntry]; } 753 754 /** Sets this instruction as squashed in the LSQ. */ 755 void setSquashedInLSQ() { status.set(SquashedInLSQ);} 756 757 /** Returns whether or not this instruction is squashed in the LSQ. */ 758 bool isSquashedInLSQ() const { return status[SquashedInLSQ]; } 759 760 761 //Reorder Buffer Functions 762 //----------------------- 763 /** Sets this instruction as a entry the ROB. */ 764 void setInROB() { status.set(RobEntry); } 765 766 /** Sets this instruction as a entry the ROB. */ 767 void clearInROB() { status.reset(RobEntry); } 768 769 /** Returns whether or not this instruction is in the ROB. */ 770 bool isInROB() const { return status[RobEntry]; } 771 772 /** Sets this instruction as squashed in the ROB. */ 773 void setSquashedInROB() { status.set(SquashedInROB); } 774 775 /** Returns whether or not this instruction is squashed in the ROB. */ 776 bool isSquashedInROB() const { return status[SquashedInROB]; } 777 778 /** Read the PC state of this instruction. */ 779 TheISA::PCState pcState() const { return pc; } 780 781 /** Set the PC state of this instruction. */ 782 void pcState(const TheISA::PCState &val) { pc = val; } 783 784 /** Read the PC of this instruction. */ 785 Addr instAddr() const { return pc.instAddr(); } 786 787 /** Read the PC of the next instruction. */ 788 Addr nextInstAddr() const { return pc.nextInstAddr(); } 789 790 /**Read the micro PC of this instruction. */ 791 Addr microPC() const { return pc.microPC(); } 792 793 bool readPredicate() 794 { 795 return instFlags[Predicate]; 796 } 797 798 void setPredicate(bool val) 799 { 800 instFlags[Predicate] = val; 801 802 if (traceData) { 803 traceData->setPredicate(val); 804 } 805 } 806 807 /** Sets the ASID. */ 808 void setASID(short addr_space_id) { asid = addr_space_id; } 809 810 /** Sets the thread id. */ 811 void setTid(ThreadID tid) { threadNumber = tid; } 812 813 /** Sets the pointer to the thread state. */ 814 void setThreadState(ImplState *state) { thread = state; } 815 816 /** Returns the thread context. */ 817 ThreadContext *tcBase() { return thread->getTC(); } 818 819 public: 820 /** Sets the effective address. */ 821 void setEA(Addr ea) { instEffAddr = ea; instFlags[EACalcDone] = true; } 822 823 /** Returns the effective address. */ 824 Addr getEA() const { return instEffAddr; } 825 826 /** Returns whether or not the eff. addr. calculation has been completed. */ 827 bool doneEACalc() { return instFlags[EACalcDone]; } 828 829 /** Returns whether or not the eff. addr. source registers are ready. */ 830 bool eaSrcsReady(); 831 832 /** Is this instruction's memory access strictly ordered? */ 833 bool strictlyOrdered() const { return instFlags[IsStrictlyOrdered]; } 834 835 /** Has this instruction generated a memory request. */ 836 bool hasRequest() { return instFlags[ReqMade]; } 837 838 /** Returns iterator to this instruction in the list of all insts. */ 839 ListIt &getInstListIt() { return instListIt; } 840 841 /** Sets iterator for this instruction in the list of all insts. */ 842 void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; } 843 844 public: 845 /** Returns the number of consecutive store conditional failures. */ 846 unsigned int readStCondFailures() const 847 { return thread->storeCondFailures; } 848 849 /** Sets the number of consecutive store conditional failures. */ 850 void setStCondFailures(unsigned int sc_failures) 851 { thread->storeCondFailures = sc_failures; } 852 853 public: 854 // monitor/mwait funtions 855 void armMonitor(Addr address) { cpu->armMonitor(threadNumber, address); } 856 bool mwait(PacketPtr pkt) { return cpu->mwait(threadNumber, pkt); } 857 void mwaitAtomic(ThreadContext *tc) 858 { return cpu->mwaitAtomic(threadNumber, tc, cpu->dtb); } 859 AddressMonitor *getAddrMonitor() 860 { return cpu->getCpuAddrMonitor(threadNumber); } 861}; 862 863template<class Impl> 864Fault 865BaseDynInst<Impl>::initiateMemRead(Addr addr, unsigned size, 866 Request::Flags flags) 867{ 868 instFlags[ReqMade] = true; 869 Request *req = NULL; 870 Request *sreqLow = NULL; 871 Request *sreqHigh = NULL; 872 873 if (instFlags[ReqMade] && translationStarted()) { 874 req = savedReq; 875 sreqLow = savedSreqLow; 876 sreqHigh = savedSreqHigh; 877 } else { 878 req = new Request(asid, addr, size, flags, masterId(), this->pc.instAddr(), 879 thread->contextId()); 880 881 req->taskId(cpu->taskId()); 882 883 // Only split the request if the ISA supports unaligned accesses. 884 if (TheISA::HasUnalignedMemAcc) { 885 splitRequest(req, sreqLow, sreqHigh); 886 } 887 initiateTranslation(req, sreqLow, sreqHigh, NULL, BaseTLB::Read); 888 } 889 890 if (translationCompleted()) { 891 if (fault == NoFault) { 892 effAddr = req->getVaddr(); 893 effSize = size; 894 instFlags[EffAddrValid] = true; 895 896 if (cpu->checker) { 897 if (reqToVerify != NULL) { 898 delete reqToVerify; 899 } 900 reqToVerify = new Request(*req); 901 } 902 fault = cpu->read(req, sreqLow, sreqHigh, lqIdx); 903 } else { 904 // Commit will have to clean up whatever happened. Set this 905 // instruction as executed. 906 this->setExecuted(); 907 } 908 } 909 910 if (traceData) 911 traceData->setMem(addr, size, flags); 912 913 return fault; 914} 915 916template<class Impl> 917Fault 918BaseDynInst<Impl>::writeMem(uint8_t *data, unsigned size, Addr addr, 919 Request::Flags flags, uint64_t *res) 920{ 921 if (traceData) 922 traceData->setMem(addr, size, flags); 923 924 instFlags[ReqMade] = true; 925 Request *req = NULL; 926 Request *sreqLow = NULL; 927 Request *sreqHigh = NULL; 928 929 if (instFlags[ReqMade] && translationStarted()) { 930 req = savedReq; 931 sreqLow = savedSreqLow; 932 sreqHigh = savedSreqHigh; 933 } else { 934 req = new Request(asid, addr, size, flags, masterId(), this->pc.instAddr(), 935 thread->contextId()); 936 937 req->taskId(cpu->taskId()); 938 939 // Only split the request if the ISA supports unaligned accesses. 940 if (TheISA::HasUnalignedMemAcc) { 941 splitRequest(req, sreqLow, sreqHigh); 942 } 943 initiateTranslation(req, sreqLow, sreqHigh, res, BaseTLB::Write); 944 } 945 946 if (fault == NoFault && translationCompleted()) { 947 effAddr = req->getVaddr(); 948 effSize = size; 949 instFlags[EffAddrValid] = true; 950 951 if (cpu->checker) { 952 if (reqToVerify != NULL) { 953 delete reqToVerify; 954 } 955 reqToVerify = new Request(*req); 956 } 957 fault = cpu->write(req, sreqLow, sreqHigh, data, sqIdx); 958 } 959 960 return fault; 961} 962 963template<class Impl> 964inline void 965BaseDynInst<Impl>::splitRequest(RequestPtr req, RequestPtr &sreqLow, 966 RequestPtr &sreqHigh) 967{ 968 // Check to see if the request crosses the next level block boundary. 969 unsigned block_size = cpu->cacheLineSize(); 970 Addr addr = req->getVaddr(); 971 Addr split_addr = roundDown(addr + req->getSize() - 1, block_size); 972 assert(split_addr <= addr || split_addr - addr < block_size); 973 974 // Spans two blocks. 975 if (split_addr > addr) { 976 req->splitOnVaddr(split_addr, sreqLow, sreqHigh); 977 } 978} 979 980template<class Impl> 981inline void 982BaseDynInst<Impl>::initiateTranslation(RequestPtr req, RequestPtr sreqLow, 983 RequestPtr sreqHigh, uint64_t *res, 984 BaseTLB::Mode mode) 985{ 986 translationStarted(true); 987 988 if (!TheISA::HasUnalignedMemAcc || sreqLow == NULL) { 989 WholeTranslationState *state = 990 new WholeTranslationState(req, NULL, res, mode); 991 992 // One translation if the request isn't split. 993 DataTranslation<BaseDynInstPtr> *trans = 994 new DataTranslation<BaseDynInstPtr>(this, state); 995 996 cpu->dtb->translateTiming(req, thread->getTC(), trans, mode); 997 998 if (!translationCompleted()) { 999 // The translation isn't yet complete, so we can't possibly have a 1000 // fault. Overwrite any existing fault we might have from a previous 1001 // execution of this instruction (e.g. an uncachable load that 1002 // couldn't execute because it wasn't at the head of the ROB). 1003 fault = NoFault; 1004 1005 // Save memory requests. 1006 savedReq = state->mainReq; 1007 savedSreqLow = state->sreqLow; 1008 savedSreqHigh = state->sreqHigh; 1009 } 1010 } else { 1011 WholeTranslationState *state = 1012 new WholeTranslationState(req, sreqLow, sreqHigh, NULL, res, mode); 1013 1014 // Two translations when the request is split. 1015 DataTranslation<BaseDynInstPtr> *stransLow = 1016 new DataTranslation<BaseDynInstPtr>(this, state, 0); 1017 DataTranslation<BaseDynInstPtr> *stransHigh = 1018 new DataTranslation<BaseDynInstPtr>(this, state, 1); 1019 1020 cpu->dtb->translateTiming(sreqLow, thread->getTC(), stransLow, mode); 1021 cpu->dtb->translateTiming(sreqHigh, thread->getTC(), stransHigh, mode); 1022 1023 if (!translationCompleted()) { 1024 // The translation isn't yet complete, so we can't possibly have a 1025 // fault. Overwrite any existing fault we might have from a previous 1026 // execution of this instruction (e.g. an uncachable load that 1027 // couldn't execute because it wasn't at the head of the ROB). 1028 fault = NoFault; 1029 1030 // Save memory requests. 1031 savedReq = state->mainReq; 1032 savedSreqLow = state->sreqLow; 1033 savedSreqHigh = state->sreqHigh; 1034 } 1035 } 1036} 1037 1038template<class Impl> 1039inline void 1040BaseDynInst<Impl>::finishTranslation(WholeTranslationState *state) 1041{ 1042 fault = state->getFault(); 1043 1044 instFlags[IsStrictlyOrdered] = state->isStrictlyOrdered(); 1045 1046 if (fault == NoFault) { 1047 // save Paddr for a single req 1048 physEffAddrLow = state->getPaddr(); 1049 1050 // case for the request that has been split 1051 if (state->isSplit) { 1052 physEffAddrLow = state->sreqLow->getPaddr(); 1053 physEffAddrHigh = state->sreqHigh->getPaddr(); 1054 } 1055 1056 memReqFlags = state->getFlags(); 1057 1058 if (state->mainReq->isCondSwap()) { 1059 assert(state->res); 1060 state->mainReq->setExtraData(*state->res); 1061 } 1062 1063 } else { 1064 state->deleteReqs(); 1065 } 1066 delete state; 1067 1068 translationCompleted(true); 1069} 1070 1071#endif // __CPU_BASE_DYN_INST_HH__ 1072